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skrzyp |
#ifndef _CYGONCE_PLATFORM_INC_H_
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#define _CYGONCE_PLATFORM_INC_H_
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// #========================================================================
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// #
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// # platform.inc
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// #
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// # Fujitsu platform specific setups (assembler macros)
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// #
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// #========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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// #========================================================================
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// ######DESCRIPTIONBEGIN####
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// #
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// # Author(s): gthomas
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// # Contributors: gthomas
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// # Date: 2001-09-16
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// # Purpose: Fujitsu (FRV400) platform specific setups
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// # Description: This file defines various macros used by the generic
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// # HAL startup code.
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// #
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// #####DESCRIPTIONEND####
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// #
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// #========================================================================
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// This does not work in standalone mode on CB70.
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//#define DEBUG_LEDS
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// Display a value in the system LEDs
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.macro LED n
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#ifdef DEBUG_LEDS
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li _MB93091_FPGA_GPHL,gr15
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lduhi @(gr15,0),gr14
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srli gr14,#8,gr14
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andicc gr14,#0x80,gr14,icc0
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bne icc0,0,999f
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sethi #(_MB93091_MB_LEDS>>16),gr15
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setlo #(_MB93091_MB_LEDS&0xFFFF),gr15
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setlos #\n,gr14
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not gr14,gr14
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sti gr14,@(gr15,0)
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999:
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#endif
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membar
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.endm
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// Platform initialization - only the necessary bits required to get the
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// board started from a cold reset.
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.macro platform_init
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li 0x7FFF,gr4 // First, a good long spin
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05: nop
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subi gr4,1,gr4
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cmp gr4,gr0,icc0
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bne icc0,0,05b
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// First work out what kind of board we are, and set the bitmask which
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// determines which elements from _platform_tab we use. In gr8:
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// bit 0 -- FR401, 64MiB (CB11)
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// bit 1 -- FR403+, 128MiB (CB30,CB60)
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// bit 2 -- FR405, 64MiB (CB70)
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// bit 3 -- FR555, 256MiB (CB41)
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// bit 4 -- VDK motherboard
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// bit 5 -- FR451-P 128MiB
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movsg psr,gr4
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srli gr4,#24,gr4
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setlos #0x18,gr8
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cmpi gr4,#0x31,icc0 // FR555
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beq icc0,#0,plf_set
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cmpi gr4,#0x11,icc0 // FR501
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beq icc0,#0,plf_set
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cmpi gr4,#0x12,icc0 // FR501A
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beq icc0,#0,plf_set
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setlos #0x11,gr8
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cmpi gr4,#0x20,icc0 // FR401
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beq icc0,#0,plf_set
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cmpi gr4,#0x21,icc0 // FR401A
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beq icc0,#0,plf_set
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setlos #0x12,gr8
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cmpi gr4,#0x22,icc0 // FR403
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beq icc0,#0,plf_set
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cmpi gr4,#0x50,icc0 // FR451
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beq icc0,#0,plf_set_maybe_cb70
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cmpi gr4,#0x40,icc0 // FR405
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bne icc0,#0,plf_set // if _not_ FR405, try this one and pray
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plf_set_maybe_cb70:
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// OK, it's an FR405 or an FR451.
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// Need to distinguish between CB60/CB70 or CB451-FPGA/CB451-F
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li _MB93091_FPGA_VDKID,gr4
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lduhi @(gr4,0),gr5
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cmpi gr5,#0x46,icc0 // CB70 has this and it's 0x0046. CB60 doesn't.
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bne icc0,#0,plf_set
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setlos #0x04,gr8 // It's a CB70
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li _MB93091_FPGA_GPHL,gr4
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lduhi @(gr4,0),gr5
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andicc gr5,#0x0100,gr0,icc0
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bne icc0,0,no_mobo
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ori gr8,0x10,gr8 // Add in the motherboard bit
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no_mobo:
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srli gr5,#8,gr5
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andicc gr5,#0x02,gr5,icc0
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bne icc0,0,plf_set
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ori gr8,0x20,gr8 // Add in the 451-P (extra SDRAM) bit
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// gr8 now holds correct bitmask
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plf_set:
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call 10f // position independent way to get @_platform_tab
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_platform_tab_fr4xx:
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//
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// SDRAM setups for FR4xx
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//
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// .long _MB93091_MB_LEDS,0x3003
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// .long _FRV400_SDRAM_BR0,0x00000000 // SDRAM 0x0XXXXXXX
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// .long _FRV400_SDRAM_AM0,0x0FF00000
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//
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// LOCAL bus setups for FR4xx
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//
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.long 7,_FRV400_LBUS_CR0,0x03010D01 // ROM/FLASH 0xFF000000..0xFFFFFFFF
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// 16 bits wide, 13 wait states, 1 idle
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.long 7,_FRV400_LBUS_BR1,0x10000000 // PCI bridge 0x10000000..0x100FFFFF
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.long 7,_FRV400_LBUS_AM1,0x000FFFFF
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.long 7,_FRV400_LBUS_CR1,0x00000000
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.long 7,_FRV400_LBUS_BR2,0x20000000 // SRAM, FPGA, PCI 0x20000000..0x2FFFFFFF
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.long 7,_FRV400_LBUS_AM2,0x0FFFFFFF
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.long 7,_FRV400_LBUS_CR2,0x00000000
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// organize rest into something sane
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.long 7,_FRV400_LBUS_BR3,0xF0300000
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.long 7,_FRV400_LBUS_AM3,0x000FFFFF
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.long 7,_FRV400_LBUS_CR3,0x00000000
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.long 6,_FRV400_LBUS_BR4,0xF0400000
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.long 6,_FRV400_LBUS_AM4,0x000FFFFF
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.long 6,_FRV400_LBUS_CR4,0x00000000
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.long 6,_FRV400_LBUS_BR5,0xF0500000
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.long 6,_FRV400_LBUS_AM5,0x000FFFFF
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.long 6,_FRV400_LBUS_CR5,0x00000000
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.long 4,_FRV400_LBUS_BR6,0xF0600000 // DM9000 on CB70 CPU card
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.long 4,_FRV400_LBUS_AM6,0x000FFFFF
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.long 4,_FRV400_LBUS_CR6,0x00400707
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.long 6,_FRV400_LBUS_BR7,0xF0700000
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.long 6,_FRV400_LBUS_AM7,0x000FFFFF
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.long 6,_FRV400_LBUS_CR7,0x00000000
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.long 7,_FRV400_GPIO_SIR,0x000c954f // Routing for Rx0, Rx1, CTS
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.long 7,_FRV400_GPIO_SOR,0x00036ab0 // Routing for Tx0, Tx1, RTS, TOUT0, TOUT1
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.long 7,_FRV400_SDRAM_CTL,0x05022000 // SDRAM mode/control
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.long 4,_FRV400_SDRAM_AN0,0x00010201
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.long 2,_FRV400_SDRAM_AN0,0x00010102
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.long 1,_FRV400_SDRAM_AN0,0x00010101
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.long 7,_FRV400_SDRAM_BR0,0x00000000
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.long 7,_FRV400_SDRAM_AM0,0x03ffffff
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.long 2,_FRV400_SDRAM_AN1,0x00010102
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.long 0x20,_FRV400_SDRAM_AN1,0x00010201
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.long 0x22,_FRV400_SDRAM_BR1,0x04000000
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.long 0x22,_FRV400_SDRAM_AM1,0x03ffffff
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.long 7,_FRV400_SDRAM_ART,0x00000820
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.long 7,_FRV400_SDRAM_RCN,0x00000000
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.long 5,_FRV400_SDRAM_MS, 0x00020200
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.long 2,_FRV400_SDRAM_MS, 0x00010000
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// .long 1,_FRV400_SDRAM_MS, 0x00020201
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.long 6,_FRV400_SDRAM_CFG,0x80000100
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.long 1,_FRV400_SDRAM_CFG,0x80000000
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//? .long 7,_FRV400_CLK_CTRL, 0x00000001 // External clock divisor (/2)
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//
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// SDRAM setups for FR5xx
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//
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.long 8,_FRV550_SDRAM_ARS0,0x00000000 // SDRAM 0x0XXXXXXX
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.long 8,_FRV550_SDRAM_AMK0,0x000000FF
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//
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// LOCAL bus setups for FR5xx
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//
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.long 8,_FRV550_LBUS_CR0,0x03010701 // ROM/FLASH 0xFF000000..0xFFFFFFFF
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// 16 bits wide, 7 wait states, 1 idle
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.long 8,_FRV550_LBUS_BR1,0x10000000 // PCI bridge 0x10000000..0x100FFFFF
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.long 8,_FRV550_LBUS_AM1,0x000FFFFF
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.long 8,_FRV550_LBUS_CR1,0x00000000
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.long 8,_FRV550_LBUS_BR2,0x20000000 // SRAM, FPGA, PCI 0x20000000..0x2FFFFFFF
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.long 8,_FRV550_LBUS_AM2,0x0FFFFFFF
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.long 8,_FRV550_LBUS_CR2,0x00000000
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.long 8,_FRV550_LBUS_BR3,0x00000000 // SDRAM?
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.long 8,_FRV550_LBUS_AM3,0xFFFFFFFF
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.long 8,_FRV550_LBUS_CR3,0x00000F07
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.long 8,_FRV550_GPIO_SIR,0x000c957f // Routing for Rx0, Rx1, CTS
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.long 8,_FRV550_GPIO_SOR,0x00336ab0 // Routing for Tx0, Tx1, RTS, TOUT0, TOUT1
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| 233 |
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.long 8,_FRV550_SDRAM_CTL,0x000C6320 // SDRAM mode/control
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.long 8,_FRV550_SDRAM_AN, 0x32323232 // assume BA[0:1], RA[12:0], CA[9:0] (32Mbit*64)
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.long 8,_FRV550_SDRAM_ART,0x00000616
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| 237 |
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.long 8,_FRV550_SDRAM_RCN,0x00000100
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| 238 |
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.long 8,_FRV550_SDRAM_CFG,0x00000000
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| 239 |
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.long 8,_FRV550_SDRAM_MS, 0x00003300
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| 240 |
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| 241 |
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//? .long 8,_FRV550_CLK_CTRL, 0x00000001 // External clock divisor (/2)
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| 242 |
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| 243 |
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//
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| 244 |
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// PCI controller/bridge
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| 245 |
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//
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| 246 |
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// .long 0x10,_MB93091_MB_LEDS,0x100b
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| 247 |
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.long 0x10,_MB93091_PCI_SLBUS_CONFIG, 0x000800E2 // This matches the docs
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| 248 |
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// .long 0x10,_MB93091_PCI_SLBUS_CONFIG, 0x000000E0 // This matches the samples
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| 249 |
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.long 0x10,_MB93091_PCI_ECS0_CONFIG, 0x00000000
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| 250 |
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.long 0x10,_MB93091_PCI_ECS1_CONFIG, 0x000003C1
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| 251 |
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.long 0x10,_MB93091_PCI_ECS2_CONFIG, 0x000001C1
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| 252 |
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.long 0x10,_MB93091_PCI_ECS0_RANGE, 0x00000000
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| 253 |
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.long 0x10,_MB93091_PCI_ECS0_ADDR, 0x00000000
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| 254 |
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.long 0x10,_MB93091_PCI_ECS1_RANGE, 0x00007FFE
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| 255 |
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.long 0x10,_MB93091_PCI_ECS1_ADDR, 0x08108000
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| 256 |
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.long 0x10,_MB93091_PCI_ECS2_RANGE, 0x00007FFE
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| 257 |
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.long 0x10,_MB93091_PCI_ECS2_ADDR, 0x08100000
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| 258 |
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.long 0x10,_MB93091_PCI_PCIIO_RANGE, 0x0001FFFE
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| 259 |
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.long 0x10,_MB93091_PCI_PCIIO_ADDR, 0x00120000
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| 260 |
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.long 0x10,_MB93091_PCI_PCIMEM_RANGE, 0x0003FFFE
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| 261 |
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.long 0x10,_MB93091_PCI_PCIMEM_ADDR, 0x00140000
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| 262 |
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.long 0x10,_MB93091_PCI_PCIIO_PCI_ADDR, 0x24000001
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| 263 |
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.long 0x10,_MB93091_PCI_PCIMEM_PCI_ADDR, 0x28000000
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| 264 |
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.long 0x10,_MB93091_MB_PCI_ARBITER, 0x00000001
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| 265 |
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.long 0x10,_MB93091_MB_PCI_ARBITER, 0x00000001
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| 266 |
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.long 0x10,_MB93091_PCI_SLBUS_CONFIG, 0x800800E2
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| 267 |
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// .long 0x10,_MB93091_PCI_SLBUS_CONFIG, 0x800000E0
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| 268 |
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// Turn the LEDs off.
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| 269 |
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.long 0x10,_MB93091_MB_LEDS,0x0000ffff
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| 270 |
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| 271 |
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// End list with SDRAM controller poll address
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| 272 |
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| 273 |
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.long 7,0,_FRV400_SDRAM_STS
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| 274 |
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.long 8,0,_FRV550_SDRAM_STS
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| 275 |
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| 276 |
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| 277 |
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10: movsg lr,gr4 // _platform_tab -> list of initializations
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| 278 |
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20: ldi @(gr4,4),gr5 // Register
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| 279 |
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ldi @(gr4,8),gr6 // Value
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| 280 |
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ldi @(gr4,0),gr7 // Platform Bitmask
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| 281 |
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and gr7,gr8,gr7
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| 282 |
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cmpi gr7,#0,icc0
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| 283 |
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beq icc0,0,25f // Skip over tuples not for us
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| 284 |
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cmp gr5,gr0,icc0 // End of list (with SDRAM poll addr)?
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| 285 |
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beq icc0,0,30f
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| 286 |
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sti gr6,@(gr5,0)
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| 287 |
|
|
25: addi gr4,3*4,gr4
|
| 288 |
|
|
bra 20b // Next item
|
| 289 |
|
|
|
| 290 |
|
|
30: ldi @(gr6,0),gr5 // gr6 == _FRVxxx_SDRAM_STS
|
| 291 |
|
|
cmp gr5,gr0,icc0
|
| 292 |
|
|
bne icc0,0,30b // Wait for SDRAM ready
|
| 293 |
|
|
call 40f
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
40:
|
| 297 |
|
|
|
| 298 |
|
|
// Clear all AMPR registers. They must not overlap.
|
| 299 |
|
|
movgs gr0,DAMPR0
|
| 300 |
|
|
movgs gr0,DAMPR1
|
| 301 |
|
|
movgs gr0,DAMPR2
|
| 302 |
|
|
movgs gr0,DAMPR3
|
| 303 |
|
|
movgs gr0,DAMPR4
|
| 304 |
|
|
movgs gr0,DAMPR5
|
| 305 |
|
|
movgs gr0,DAMPR6
|
| 306 |
|
|
movgs gr0,DAMPR7
|
| 307 |
|
|
movgs gr0,IAMPR0
|
| 308 |
|
|
movgs gr0,IAMPR1
|
| 309 |
|
|
movgs gr0,IAMPR2
|
| 310 |
|
|
movgs gr0,IAMPR3
|
| 311 |
|
|
movgs gr0,IAMPR4
|
| 312 |
|
|
movgs gr0,IAMPR5
|
| 313 |
|
|
movgs gr0,IAMPR6
|
| 314 |
|
|
movgs gr0,IAMPR7
|
| 315 |
|
|
|
| 316 |
|
|
li 0x000000C9,gr4 // Set 0x0XXXXXXX supervisor only, cache - SDRAM
|
| 317 |
|
|
movgs gr4,DAMPR1
|
| 318 |
|
|
|
| 319 |
|
|
li 0xF000007D,gr4 // Set 0xF0XXXXXX supervisor only, no cache - chip selects (16MB)
|
| 320 |
|
|
movgs gr4,DAMPR2
|
| 321 |
|
|
|
| 322 |
|
|
li 0x200000BD,gr4 // Set 0x2XXXXXXX supervisor only, no cache - Motherboard resources
|
| 323 |
|
|
movgs gr4,DAMPR6
|
| 324 |
|
|
|
| 325 |
|
|
LED 0x1003
|
| 326 |
|
|
|
| 327 |
|
|
li 0x100000BD,gr4 // Set 0x1XXXXXXX supervisor only, no cache - PCI bridge
|
| 328 |
|
|
movgs gr4,DAMPR7
|
| 329 |
|
|
|
| 330 |
|
|
andi gr8,#8,gr7 // Check CPU type again. 0x8 is FR5xx
|
| 331 |
|
|
cmpi gr7,#0,icc0
|
| 332 |
|
|
beq icc0,#0,70f
|
| 333 |
|
|
|
| 334 |
|
|
// And the rest, for FR555...
|
| 335 |
|
|
movgs gr0,IAMPR8
|
| 336 |
|
|
movgs gr0,IAMPR9
|
| 337 |
|
|
movgs gr0,IAMPR10
|
| 338 |
|
|
movgs gr0,IAMPR11
|
| 339 |
|
|
movgs gr0,IAMPR12
|
| 340 |
|
|
movgs gr0,IAMPR13
|
| 341 |
|
|
movgs gr0,IAMPR14
|
| 342 |
|
|
movgs gr0,IAMPR15
|
| 343 |
|
|
movgs gr0,DAMPR8
|
| 344 |
|
|
movgs gr0,DAMPR9
|
| 345 |
|
|
movgs gr0,DAMPR10
|
| 346 |
|
|
movgs gr0,DAMPR11
|
| 347 |
|
|
movgs gr0,DAMPR12
|
| 348 |
|
|
movgs gr0,DAMPR13
|
| 349 |
|
|
movgs gr0,DAMPR14
|
| 350 |
|
|
movgs gr0,DAMPR15
|
| 351 |
|
|
|
| 352 |
|
|
movgs gr0,DAMLR1
|
| 353 |
|
|
li 0x20000000,gr4
|
| 354 |
|
|
movgs gr4,DAMLR6
|
| 355 |
|
|
li 0x10000000,gr4
|
| 356 |
|
|
movgs gr4,DAMLR7
|
| 357 |
|
|
|
| 358 |
|
|
70:
|
| 359 |
|
|
LED 0x1004
|
| 360 |
|
|
movsg hsr0,gr4
|
| 361 |
|
|
li (1<<25),gr5 // Enable data MMU
|
| 362 |
|
|
or gr4,gr5,gr4
|
| 363 |
|
|
movgs gr4,hsr0
|
| 364 |
|
|
LED 0x1005
|
| 365 |
|
|
.endm
|
| 366 |
|
|
|
| 367 |
|
|
#endif // _CYGONCE_PLATFORM_INC_H_
|
