| 1 |
786 |
skrzyp |
#ifndef CYGONCE_HAL_HAL_INTR_H
|
| 2 |
|
|
#define CYGONCE_HAL_HAL_INTR_H
|
| 3 |
|
|
//==========================================================================
|
| 4 |
|
|
//
|
| 5 |
|
|
// hal_intr.h
|
| 6 |
|
|
//
|
| 7 |
|
|
// HAL Interrupt and clock support
|
| 8 |
|
|
//
|
| 9 |
|
|
//==========================================================================
|
| 10 |
|
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
| 11 |
|
|
// -------------------------------------------
|
| 12 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 13 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
| 14 |
|
|
//
|
| 15 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 16 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 17 |
|
|
// Software Foundation; either version 2 or (at your option) any later
|
| 18 |
|
|
// version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
| 21 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 22 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 23 |
|
|
// for more details.
|
| 24 |
|
|
//
|
| 25 |
|
|
// You should have received a copy of the GNU General Public License
|
| 26 |
|
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 27 |
|
|
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 28 |
|
|
//
|
| 29 |
|
|
// As a special exception, if other files instantiate templates or use
|
| 30 |
|
|
// macros or inline functions from this file, or you compile this file
|
| 31 |
|
|
// and link it with other works to produce a work based on this file,
|
| 32 |
|
|
// this file does not by itself cause the resulting work to be covered by
|
| 33 |
|
|
// the GNU General Public License. However the source code for this file
|
| 34 |
|
|
// must still be made available in accordance with section (3) of the GNU
|
| 35 |
|
|
// General Public License v2.
|
| 36 |
|
|
//
|
| 37 |
|
|
// This exception does not invalidate any other reasons why a work based
|
| 38 |
|
|
// on this file might be covered by the GNU General Public License.
|
| 39 |
|
|
// -------------------------------------------
|
| 40 |
|
|
// ####ECOSGPLCOPYRIGHTEND####
|
| 41 |
|
|
//==========================================================================
|
| 42 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 43 |
|
|
//
|
| 44 |
|
|
// Author(s): yoshinori sato
|
| 45 |
|
|
// Contributors: yoshinori sato
|
| 46 |
|
|
// Date: 2002-02-13
|
| 47 |
|
|
// Purpose: Define Interrupt support
|
| 48 |
|
|
// Description: The macros defined here provide the HAL APIs for handling
|
| 49 |
|
|
// interrupts and the clock.
|
| 50 |
|
|
// Usage:
|
| 51 |
|
|
// #include <cyg/hal/hal_intr.h>
|
| 52 |
|
|
// ...
|
| 53 |
|
|
//
|
| 54 |
|
|
//
|
| 55 |
|
|
//####DESCRIPTIONEND####
|
| 56 |
|
|
//
|
| 57 |
|
|
//==========================================================================
|
| 58 |
|
|
|
| 59 |
|
|
#include <pkgconf/hal.h>
|
| 60 |
|
|
|
| 61 |
|
|
#include <cyg/infra/cyg_type.h>
|
| 62 |
|
|
#include <cyg/hal/hal_io.h>
|
| 63 |
|
|
|
| 64 |
|
|
#include <cyg/hal/var_intr.h>
|
| 65 |
|
|
|
| 66 |
|
|
//--------------------------------------------------------------------------
|
| 67 |
|
|
// Static data used by HAL
|
| 68 |
|
|
|
| 69 |
|
|
// ISR tables
|
| 70 |
|
|
externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
|
| 71 |
|
|
externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
|
| 72 |
|
|
externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
|
| 73 |
|
|
|
| 74 |
|
|
// VSR table
|
| 75 |
|
|
externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
|
| 76 |
|
|
|
| 77 |
|
|
//--------------------------------------------------------------------------
|
| 78 |
|
|
// Default ISR
|
| 79 |
|
|
// The #define is used to test whether this routine exists, and to allow
|
| 80 |
|
|
// us to call it.
|
| 81 |
|
|
|
| 82 |
|
|
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
|
| 83 |
|
|
|
| 84 |
|
|
#define HAL_DEFAULT_ISR hal_default_isr
|
| 85 |
|
|
|
| 86 |
|
|
//--------------------------------------------------------------------------
|
| 87 |
|
|
// Interrupt state storage
|
| 88 |
|
|
|
| 89 |
|
|
typedef cyg_uint32 CYG_INTERRUPT_STATE;
|
| 90 |
|
|
|
| 91 |
|
|
//--------------------------------------------------------------------------
|
| 92 |
|
|
|
| 93 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 94 |
|
|
|
| 95 |
|
|
// Routine to execute DSRs using separate interrupt stack
|
| 96 |
|
|
externC void hal_interrupt_stack_call_pending_DSRs(void);
|
| 97 |
|
|
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
|
| 98 |
|
|
hal_interrupt_stack_call_pending_DSRs()
|
| 99 |
|
|
|
| 100 |
|
|
// these are offered solely for stack usage testing
|
| 101 |
|
|
// if they are not defined, then there is no interrupt stack.
|
| 102 |
|
|
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
|
| 103 |
|
|
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
|
| 104 |
|
|
// use them to declare these extern however you want:
|
| 105 |
|
|
// extern char HAL_INTERRUPT_STACK_BASE[];
|
| 106 |
|
|
// extern char HAL_INTERRUPT_STACK_TOP[];
|
| 107 |
|
|
// is recommended
|
| 108 |
|
|
|
| 109 |
|
|
#endif
|
| 110 |
|
|
|
| 111 |
|
|
|
| 112 |
|
|
#ifndef HAL_TRANSLATE_VECTOR
|
| 113 |
|
|
|
| 114 |
|
|
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
|
| 115 |
|
|
|
| 116 |
|
|
#endif
|
| 117 |
|
|
|
| 118 |
|
|
//--------------------------------------------------------------------------
|
| 119 |
|
|
// Interrupt and VSR attachment macros
|
| 120 |
|
|
|
| 121 |
|
|
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
|
| 122 |
|
|
CYG_MACRO_START \
|
| 123 |
|
|
cyg_uint32 _index_; \
|
| 124 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 125 |
|
|
\
|
| 126 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
|
| 127 |
|
|
(_state_) = 0; \
|
| 128 |
|
|
else \
|
| 129 |
|
|
(_state_) = 1; \
|
| 130 |
|
|
CYG_MACRO_END
|
| 131 |
|
|
|
| 132 |
|
|
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
|
| 133 |
|
|
CYG_MACRO_START \
|
| 134 |
|
|
cyg_uint32 _index_; \
|
| 135 |
|
|
HAL_TRANSLATE_VECTOR(_vector_,_index_); \
|
| 136 |
|
|
\
|
| 137 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
|
| 138 |
|
|
{ \
|
| 139 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
|
| 140 |
|
|
hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
|
| 141 |
|
|
hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
|
| 142 |
|
|
} \
|
| 143 |
|
|
CYG_MACRO_END
|
| 144 |
|
|
|
| 145 |
|
|
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
|
| 146 |
|
|
CYG_MACRO_START \
|
| 147 |
|
|
cyg_uint32 _index_; \
|
| 148 |
|
|
HAL_TRANSLATE_VECTOR(_vector_,_index_); \
|
| 149 |
|
|
\
|
| 150 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
|
| 151 |
|
|
{ \
|
| 152 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
|
| 153 |
|
|
hal_interrupt_data[_index_] = 0; \
|
| 154 |
|
|
hal_interrupt_objects[_index_] = 0; \
|
| 155 |
|
|
} \
|
| 156 |
|
|
CYG_MACRO_END
|
| 157 |
|
|
|
| 158 |
|
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
|
| 159 |
|
|
*((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_];
|
| 160 |
|
|
|
| 161 |
|
|
|
| 162 |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
|
| 163 |
|
|
if( _poldvsr_ != NULL ) \
|
| 164 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
|
| 165 |
|
|
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;
|
| 166 |
|
|
|
| 167 |
|
|
|
| 168 |
|
|
//--------------------------------------------------------------------------
|
| 169 |
|
|
// Interrupt controller access
|
| 170 |
|
|
// Read interrupt control registers back after writing to them. This
|
| 171 |
|
|
// ensures that the written value is not sitting in the store buffers
|
| 172 |
|
|
// when interrupts are re-enabled.
|
| 173 |
|
|
|
| 174 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ ) \
|
| 175 |
|
|
hal_interrupt_mask( _vector_ )
|
| 176 |
|
|
|
| 177 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
|
| 178 |
|
|
hal_interrupt_unmask( _vector_ )
|
| 179 |
|
|
|
| 180 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 181 |
|
|
hal_interrupt_acknowledge( _vector_ )
|
| 182 |
|
|
|
| 183 |
|
|
#if !defined(HAL_INTERRUPT_CONFIGURE)
|
| 184 |
|
|
|
| 185 |
|
|
#error HAL_INTERRUPT_CONFIGURE not defined by variant
|
| 186 |
|
|
|
| 187 |
|
|
#endif
|
| 188 |
|
|
|
| 189 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
|
| 190 |
|
|
hal_interrupt_set_level( _vector_, _level_ )
|
| 191 |
|
|
|
| 192 |
|
|
|
| 193 |
|
|
externC void hal_interrupt_mask(int vector);
|
| 194 |
|
|
externC void hal_interrupt_unmask(int vector);
|
| 195 |
|
|
externC void hal_interrupt_acknowledge(int vector);
|
| 196 |
|
|
externC void hal_interrupt_set_level(int vector,int level);
|
| 197 |
|
|
//--------------------------------------------------------------------------
|
| 198 |
|
|
// Clock control.
|
| 199 |
|
|
// This is almost all handled in the var_intr.h.
|
| 200 |
|
|
|
| 201 |
|
|
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
|
| 202 |
|
|
#define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
|
| 203 |
|
|
#endif
|
| 204 |
|
|
|
| 205 |
|
|
//--------------------------------------------------------------------------
|
| 206 |
|
|
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
|
| 207 |
|
|
// EOF hal_intr.h
|
