OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [h8300/] [arch/] [current/] [src/] [context.S] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
##=============================================================================
2
##
3
##      context.S
4
##
5
##      H8/300 context switch code
6
##
7
##=============================================================================
8
## ####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later
16
## version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT
19
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License
24
## along with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26
##
27
## As a special exception, if other files instantiate templates or use
28
## macros or inline functions from this file, or you compile this file
29
## and link it with other works to produce a work based on this file,
30
## this file does not by itself cause the resulting work to be covered by
31
## the GNU General Public License. However the source code for this file
32
## must still be made available in accordance with section (3) of the GNU
33
## General Public License v2.
34
##
35
## This exception does not invalidate any other reasons why a work based
36
## on this file might be covered by the GNU General Public License.
37
## -------------------------------------------
38
## ####ECOSGPLCOPYRIGHTEND####
39
##=============================================================================
40
#######DESCRIPTIONBEGIN####
41
##
42
## Author(s):   yoshinori sato
43
## Contributors:        yoshinori sato
44
## Date:        2002-02-17
45
## Purpose:     H8/300 context switch code
46
## Description: This file contains implementations of the thread context
47
##              switch routines. It also contains the longjmp() and setjmp()
48
##              routines.
49
##
50
######DESCRIPTIONEND####
51
##
52
##=============================================================================
53
 
54
#include 
55
 
56
#include 
57
#include 
58
 
59
 
60
#ifdef CYGPKG_HAL_H8300_H8300H
61
        .h8300h
62
#endif
63
#ifdef CYGPKG_HAL_H8300_H8S
64
        .h8300s
65
#endif
66
 
67
#------------------------------------------------------------------------------
68
# hal_thread_switch_context
69
# Switch thread contexts
70
# er0 = address of sp of next thread to execute
71
# er1 = address of sp save location of current thread
72
 
73
        .global CYG_LABEL_DEFN(hal_thread_switch_context)
74
CYG_LABEL_DEFN(hal_thread_switch_context):
75
        mov.w   @sp,r2          ; save ccr
76
        stc     ccr,r2h
77
        mov.w   r2,@sp
78
        hal_cpu_save_context
79
        mov.l   sp,@er1
80
 
81
        # Now load the destination thread by dropping through
82
        # to hal_thread_load_context
83
 
84
#------------------------------------------------------------------------------
85
# hal_thread_load_context
86
# Load thread context
87
# D0 = address of sp of next thread to execute
88
# Note that this function is also the second half of hal_thread_switch_context
89
# and is simply dropped into from it.
90
 
91
        .global CYG_LABEL_DEFN(hal_thread_load_context)
92
CYG_LABEL_DEFN(hal_thread_load_context):
93
 
94
        mov.l   @er0,sp
95
        hal_cpu_load_all
96
        rte
97
 
98
##-----------------------------------------------------------------------------
99
## HAL longjmp(), setjmp() implementations
100
## These implementations omit the usual movm [d2,d3,a2,a3],(sp)
101
## Which is the first instruction of all C compiled functions.
102
## Note: These definitions are repeated in hal_arch.h. If changes are required
103
## remember to update both sets.
104
 
105
#define CYGARC_JMP_BUF_SP        0
106
#define CYGARC_JMP_BUF_ER3       1
107
#define CYGARC_JMP_BUF_ER4       2
108
#define CYGARC_JMP_BUF_ER5       3
109
#define CYGARC_JMP_BUF_ER6       4
110
#define CYGARC_JMP_BUF_PC        5
111
 
112
#define CYGARC_JMP_BUF_SIZE      6
113
 
114
 
115
        # This just preserves the callee save registers
116
        # namely a2,a3,d2,d3
117
        # setjmp cannot use movm to do this as we need to keep
118
        # the sp underneath all live data at all times.
119
        .globl CYG_LABEL_DEFN(hal_setjmp)
120
CYG_LABEL_DEFN(hal_setjmp):                              ; er0=env
121
        mov.l   er3,@(CYGARC_JMP_BUF_ER3*4,er0)
122
        mov.l   er4,@(CYGARC_JMP_BUF_ER4*4,er0)
123
        mov.l   er5,@(CYGARC_JMP_BUF_ER5*4,er0)
124
        mov.l   er6,@(CYGARC_JMP_BUF_ER6*4,er0)
125
        mov.l   @sp,er1
126
        mov.l   er1,@(CYGARC_JMP_BUF_PC*4,er0)
127
        mov     sp,er1
128
        mov     er1,@(CYGARC_JMP_BUF_SP*4,er0)
129
        sub.l   er0,er0
130
        rts
131
 
132
        # longjmp returns to caller of setjmp
133
        # after restoring callee save registers
134
        .globl CYG_LABEL_DEFN(hal_longjmp)
135
CYG_LABEL_DEFN(hal_longjmp):
136
        mov.l   @(CYGARC_JMP_BUF_ER3*4,er0),er3
137
        mov.l   @(CYGARC_JMP_BUF_ER4*4,er0),er4
138
        mov.l   @(CYGARC_JMP_BUF_ER5*4,er0),er5
139
        mov.l   @(CYGARC_JMP_BUF_ER6*4,er0),er6
140
        mov.l   @(CYGARC_JMP_BUF_PC*4,er0),er2
141
        mov.l   @(CYGARC_JMP_BUF_SP*4,er0),sp
142
        mov.l   er2,@sp
143
        mov.l   er1,er0
144
        rts
145
 
146
 
147
#------------------------------------------------------------------------------
148
# end of context.S
149
 
150
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.