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# ====================================================================
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#
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# hal_h8300_h8s_edosk2674.cdl
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#
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# EDOSK-2674 HAL package configuration data
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#
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# ====================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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# ====================================================================
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######DESCRIPTIONBEGIN####
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#
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# Author(s): yoshinori sato
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# Original data: yoshinori sato
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# Contributors:
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# Date: 2003-02-24
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#
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#####DESCRIPTIONEND####
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#
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# ====================================================================
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cdl_package CYGPKG_HAL_H8300_H8S_EDOSK2674 {
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display "EDOSK2674"
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parent CYGPKG_HAL_H8300
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requires CYGPKG_HAL_H8300_H8S
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implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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implements CYGINT_HAL_DEBUG_GDB_STUBS
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implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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define_header hal_h8300_h8s_edosk2674.h
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include_dir cyg/hal
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description "
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The edosk2674 HAL package provides the support needed to run
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eCos on a Hitach Micro System Europe EDOSK2674 evalution board."
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compile hal_diag.c plf_misc.c delay_us.S
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define_proc {
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puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H "
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puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "
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puts $::cdl_header "#define CYG_HAL_H8300"
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puts $::cdl_header "#define CYGNUM_HAL_H8300_SCI_PORTS 2"
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puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0xffbd00"
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puts $::cdl_header "#define HAL_PLATFORM_CPU \"H8S\""
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puts $::cdl_header "#define HAL_PLATFORM_BOARD \"EDOSK-2674\""
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puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
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}
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cdl_component CYG_HAL_STARTUP {
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display "Startup type"
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flavor data
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legal_values {"ROM" "RAM"}
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default_value {"ROM"}
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no_define
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define -file system.h CYG_HAL_STARTUP
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description "
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When targetting the EDOSK2674 board it is possible to
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build the system for either RAM bootstrap or ROM bootstrap.
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RAM bootstrap generally requires that the board
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is equipped with ROMs containing a suitable ROM monitor or
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equivalent software that allows GDB to download the eCos
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application and extend Memory on to the board.
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The ROM bootstrap typically
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requires that the eCos application be blown into EPROMs or
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equivalent technology."
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}
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cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
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display "Number of communication channels on the board"
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flavor data
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calculated 1
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}
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cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
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display "Debug serial port"
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flavor data
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legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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default_value 0
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description "
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The EDOSK2674 board has only one serial port. This option
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chooses which port will be used to connect to a host
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running GDB."
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}
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cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
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display "Diagnostic serial port"
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flavor data
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legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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default_value 0
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description "
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The CQ/7708 board has only one serial port. This option
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chooses which port will be used for diagnostic output."
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}
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# Real-time clock/counter specifics
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cdl_component CYGNUM_HAL_RTC_CONSTANTS {
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display "Real-time clock constants."
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flavor none
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cdl_option CYGNUM_HAL_RTC_NUMERATOR {
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display "Real-time clock numerator"
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flavor data
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calculated 1000000000
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}
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cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
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display "Real-time clock denominator"
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flavor data
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calculated 100
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}
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cdl_option CYGNUM_HAL_H8300_RTC_PRESCALE {
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display "Real-time clock base prescale"
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flavor data
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calculated 8192
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}
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# Isn't a nice way to handle freq requirement!
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cdl_option CYGNUM_HAL_RTC_PERIOD {
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display "Real-time clock period"
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flavor data
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calculated 10
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}
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}
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cdl_option CYGHWR_HAL_H8300_CPG_INPUT {
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display "OSC/Clock Freqency"
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flavor data
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default_value 33000000
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}
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cdl_component CYGBLD_GLOBAL_OPTIONS {
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display "Global build options"
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flavor none
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parent CYGPKG_NONE
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description "
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Global build options including control over
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compiler flags, linker flags and choice of toolchain."
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cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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display "Global command prefix"
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flavor data
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no_define
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default_value { "h8300-elf" }
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description "
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This option specifies the command prefix used when
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invoking the build tools."
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}
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cdl_option CYGBLD_GLOBAL_CFLAGS {
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display "Global compiler flags"
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flavor data
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no_define
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default_value { CYGBLD_GLOBAL_WARNFLAGS . " -g -O2 -ms -mint32 -fsigned-char -fdata-sections -fno-rtti -fno-exceptions " }
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description "
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This option controls the global compiler flags which
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are used to compile all packages by
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default. Individual packages may define
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options which override these global flags."
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}
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cdl_option CYGBLD_GLOBAL_LDFLAGS {
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display "Global linker flags"
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flavor data
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no_define
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default_value { "-g -nostdlib -Wl,--gc-sections -Wl,-static -mrelax -ms -mint32" }
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description "
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This option controls the global linker flags. Individual
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packages may define options which override these global flags."
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}
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cdl_option CYGBLD_BUILD_GDB_STUBS {
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display "Build GDB stub ROM image"
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default_value 0
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requires CYGSEM_HAL_ROM_MONITOR
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requires CYGBLD_BUILD_COMMON_GDB_STUBS
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requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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no_define
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description "
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This option enables the building of the GDB stubs for the
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board. The common HAL controls takes care of most of the
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build process, but the final conversion from ELF image to
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binary data is handled by the platform CDL, allowing
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relocation of the data if necessary."
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make -priority 320 {
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/bin/gdb_module.bin : /bin/gdb_module.img
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$(OBJCOPY) -O binary $< $@
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}
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}
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}
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cdl_component CYGHWR_MEMORY_LAYOUT {
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display "Memory layout"
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flavor data
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no_define
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calculated { CYG_HAL_STARTUP == "RAM" ? "h8300_h8s_edosk2674_ram" : \
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"h8300_h8s_edosk2674_rom" }
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cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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display "Memory layout linker script fragment"
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flavor data
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no_define
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define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
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"" }
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}
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cdl_option CYGHWR_MEMORY_LAYOUT_H {
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display "Memory layout header file"
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flavor data
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no_define
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define -file system.h CYGHWR_MEMORY_LAYOUT_H
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calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
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"" }
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}
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}
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cdl_option CYGSEM_HAL_ROM_MONITOR {
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display "Behave as a ROM monitor"
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flavor bool
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default_value 0
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parent CYGPKG_HAL_ROM_MONITOR
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requires { CYG_HAL_STARTUP == "ROM" }
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description "
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Enable this option if this program is to be used as a ROM monitor,
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i.e. applications will be loaded into RAM on the board, and this
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ROM monitor may process exceptions or interrupts generated from the
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application. This enables features such as utilizing a separate
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interrupt stack when exceptions are generated."
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}
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cdl_option CYGHWR_HAL_H8300_VECTOR_ADDRESS {
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display "Hook Vector Address"
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flavor data
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default_value 0xffbe00
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active_if CYGSEM_HAL_H8300_VECTOR_HOOK
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parent CYGPKG_HAL_ROM_MONITOR
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description "
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Hooking Vector Table Address"
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}
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cdl_option CYGHAL_PLF_SCI_BASE {
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display "SCI Base address"
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flavor data
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default_value 0xffff88
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description "
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Used SCI Channel base address."
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}
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cdl_option CYGDAT_REDBOOT_H8300_LINUX_COMMAND_START {
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display "Default kernel command line start address"
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flavor data
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default_value 0xbffe00
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description "
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This option uClinux kernel command line start address of default."
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}
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cdl_option CYGDAT_REDBOOT_H8300_LINUX_BOOT_COMMAND_LINE {
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display "Default command line"
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flavor data
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default_value { "console=/dev/ttySC2" }
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description "
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This option uClinux kernel startup command line of default."
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}
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}
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