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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [h8300/] [h8s/] [current/] [src/] [var_misc.c] - Blame information for rev 786

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1 786 skrzyp 
//==========================================================================
2 
//
3 
//      var_misc.c
4 
//
5 
//      HAL CPU variant miscellaneous functions
6 
//
7 
//==========================================================================
8 
// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26 
//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
31 
// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
41 
//
42 
// Author(s):    ysato
43 
// Contributors: ysato
44 
// Date:         2002-12-31
45 
// Purpose:      HAL miscellaneous functions
46 
// Description:  This file contains miscellaneous functions provided by the
47 
//               HAL.
48 
//
49 
//####DESCRIPTIONEND####
50 
//
51 
//========================================================================*/
52 
 
53 
#include <pkgconf/hal.h>
54 
 
55 
#include <cyg/infra/cyg_type.h>         // Base types
56 
#include <cyg/infra/cyg_trac.h>         // tracing macros
57 
#include <cyg/infra/cyg_ass.h>          // assertion macros
58 
#include <cyg/hal/var_arch.h>
59 
#include <cyg/hal/var_intr.h>
60 
#include <cyg/hal/hal_io.h>
61 
 
62 
/*------------------------------------------------------------------------*/
63 
/* Variant specific initialization routine.                               */
64 
 
65 
void hal_variant_init(void)
66 
{
67 
}
68 
 
69 
struct int_regs {
70 
    CYG_BYTE *ier;
71 
    CYG_BYTE *isr;
72 
    CYG_BYTE mask;
73 
    CYG_BYTE status;
74 
};
75 
 
76 
#define REGS_DEF(ier,isr,mask,status) \
77 
        {(CYG_BYTE *)ier,(CYG_BYTE *)isr,mask,status}
78 
 
79 
const struct int_regs interrupt_registers[]= {
80 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x01,0x01),
81 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x02,0x02),
82 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x04,0x04),
83 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x08,0x08),
84 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x10,0x10),
85 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x20,0x20),
86 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x40,0x40),
87 
    REGS_DEF(CYGARC_IERL,CYGARC_ISRL,0x80,0x80),
88 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x01,0x01),
89 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x02,0x02),
90 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x04,0x04),
91 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x08,0x08),
92 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x10,0x10),
93 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x20,0x20),
94 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x40,0x40),
95 
    REGS_DEF(CYGARC_IERH,CYGARC_ISRH,0x80,0x80),
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    REGS_DEF(NULL,NULL,0,0),
97 
    REGS_DEF(CYGARC_TCSR,CYGARC_TCSR,0x20,0x80),
98 
    REGS_DEF(NULL,NULL,0,0),
99 
    REGS_DEF(CYGARC_REFCR,CYGARC_REFCR,0x40,0x80),
100 
    REGS_DEF(NULL,NULL,0,0),
101 
    REGS_DEF(NULL,NULL,0,0),
102 
    REGS_DEF(CYGARC_ADCSR,CYGARC_ADCSR,0x40,0x80),
103 
    REGS_DEF(NULL,NULL,0,0),
104 
    REGS_DEF(CYGARC_TIER0,CYGARC_TSR0,0x01,0x01),
105 
    REGS_DEF(CYGARC_TIER0,CYGARC_TSR0,0x02,0x02),
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    REGS_DEF(CYGARC_TIER0,CYGARC_TSR0,0x04,0x04),
107 
    REGS_DEF(CYGARC_TIER0,CYGARC_TSR0,0x08,0x08),
108 
    REGS_DEF(CYGARC_TIER0,CYGARC_TSR0,0x10,0x10),
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    REGS_DEF(NULL,NULL,0,0),
110 
    REGS_DEF(NULL,NULL,0,0),
111 
    REGS_DEF(NULL,NULL,0,0),
112 
    REGS_DEF(CYGARC_TIER1,CYGARC_TSR1,0x01,0x01),
113 
    REGS_DEF(CYGARC_TIER1,CYGARC_TSR1,0x02,0x02),
114 
    REGS_DEF(CYGARC_TIER1,CYGARC_TSR1,0x10,0x10),
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    REGS_DEF(CYGARC_TIER1,CYGARC_TSR1,0x20,0x20),
116 
    REGS_DEF(CYGARC_TIER2,CYGARC_TSR2,0x01,0x01),
117 
    REGS_DEF(CYGARC_TIER2,CYGARC_TSR2,0x02,0x02),
118 
    REGS_DEF(CYGARC_TIER2,CYGARC_TSR2,0x10,0x10),
119 
    REGS_DEF(CYGARC_TIER2,CYGARC_TSR2,0x20,0x20),
120 
    REGS_DEF(CYGARC_TIER3,CYGARC_TSR3,0x01,0x01),
121 
    REGS_DEF(CYGARC_TIER3,CYGARC_TSR3,0x02,0x02),
122 
    REGS_DEF(CYGARC_TIER3,CYGARC_TSR3,0x04,0x04),
123 
    REGS_DEF(CYGARC_TIER3,CYGARC_TSR3,0x08,0x08),
124 
    REGS_DEF(CYGARC_TIER3,CYGARC_TSR3,0x10,0x10),
125 
    REGS_DEF(NULL,NULL,0,0),
126 
    REGS_DEF(NULL,NULL,0,0),
127 
    REGS_DEF(NULL,NULL,0,0),
128 
    REGS_DEF(CYGARC_TIER4,CYGARC_TSR4,0x01,0x01),
129 
    REGS_DEF(CYGARC_TIER4,CYGARC_TSR4,0x02,0x02),
130 
    REGS_DEF(CYGARC_TIER4,CYGARC_TSR4,0x10,0x10),
131 
    REGS_DEF(CYGARC_TIER4,CYGARC_TSR4,0x20,0x20),
132 
    REGS_DEF(CYGARC_TIER5,CYGARC_TSR5,0x01,0x01),
133 
    REGS_DEF(CYGARC_TIER5,CYGARC_TSR5,0x02,0x02),
134 
    REGS_DEF(CYGARC_TIER5,CYGARC_TSR5,0x10,0x10),
135 
    REGS_DEF(CYGARC_TIER5,CYGARC_TSR5,0x20,0x20),
136 
    REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x40,0x40),
137 
    REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x80,0x80),
138 
    REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x20,0x20),
139 
    REGS_DEF(NULL,NULL,0,0),
140 
    REGS_DEF(CYGARC_8TCR1,CYGARC_8TCSR1,0x40,0x40),
141 
    REGS_DEF(CYGARC_8TCR1,CYGARC_8TCSR1,0x80,0x80),
142 
    REGS_DEF(CYGARC_8TCR1,CYGARC_8TCSR1,0x20,0x20),
143 
    REGS_DEF(NULL,NULL,0,0),
144 
    REGS_DEF(CYGARC_DMABCRL,CYGARC_DMABCRL,0x01,0x10),
145 
    REGS_DEF(CYGARC_DMABCRL,CYGARC_DMABCRL,0x02,0x20),
146 
    REGS_DEF(CYGARC_DMABCRL,CYGARC_DMABCRL,0x04,0x40),
147 
    REGS_DEF(CYGARC_DMABCRL,CYGARC_DMABCRL,0x08,0x80),
148 
    REGS_DEF(CYGARC_EDMDR0L,CYGARC_EDMDR0L,0x80,0x40),
149 
    REGS_DEF(CYGARC_EDMDR1L,CYGARC_EDMDR1L,0x80,0x40),
150 
    REGS_DEF(CYGARC_EDMDR2L,CYGARC_EDMDR2L,0x80,0x40),
151 
    REGS_DEF(CYGARC_EDMDR3L,CYGARC_EDMDR3L,0x80,0x40),
152 
    REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x40,0x30),
153 
    REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x40,0x40),
154 
    REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x80,0x80),
155 
    REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x04,0x04),
156 
    REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x40,0x30),
157 
    REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x40,0x40),
158 
    REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x80,0x80),
159 
    REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x04,0x04),
160 
    REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x40,0x30),
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    REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x40,0x40),
162 
    REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x80,0x80),
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    REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x04,0x04),
164 
    REGS_DEF(NULL,NULL,0,0),
165 
    REGS_DEF(NULL,NULL,0,0),
166 
    REGS_DEF(NULL,NULL,0,0),
167 
    REGS_DEF(NULL,NULL,0,0),
168 
    REGS_DEF(NULL,NULL,0,0),
169 
    REGS_DEF(NULL,NULL,0,0),
170 
    REGS_DEF(NULL,NULL,0,0),
171 
    REGS_DEF(NULL,NULL,0,0),
172 
    REGS_DEF(NULL,NULL,0,0),
173 
    REGS_DEF(NULL,NULL,0,0),
174 
    REGS_DEF(NULL,NULL,0,0),
175 
    REGS_DEF(NULL,NULL,0,0),
176 
    REGS_DEF(NULL,NULL,0,0),
177 
    REGS_DEF(NULL,NULL,0,0),
178 
    REGS_DEF(NULL,NULL,0,0),
179 
    REGS_DEF(NULL,NULL,0,0),
180 
    REGS_DEF(NULL,NULL,0,0),
181 
    REGS_DEF(NULL,NULL,0,0),
182 
    REGS_DEF(NULL,NULL,0,0),
183 
    REGS_DEF(NULL,NULL,0,0),
184 
    REGS_DEF(NULL,NULL,0,0),
185 
    REGS_DEF(NULL,NULL,0,0),
186 
    REGS_DEF(NULL,NULL,0,0),
187 
    REGS_DEF(NULL,NULL,0,0),
188 
    REGS_DEF(NULL,NULL,0,0),
189 
    REGS_DEF(NULL,NULL,0,0),
190 
    REGS_DEF(NULL,NULL,0,0),
191 
    REGS_DEF(NULL,NULL,0,0),
192 
};
193 
 
194 
void
195 
hal_interrupt_mask(int vector)
196 
{
197 
    CYG_BYTE ier;
198 
    const struct int_regs *regs=&interrupt_registers[vector-CYGNUM_HAL_INTERRUPT_EXTERNAL_0];
199 
    if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
200 
        HAL_READ_UINT8(CYGARC_TCSR,ier);
201 
        ier &= ~0x20;
202 
        HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | ier);
203 
    } else {
204 
        if ((vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0) && regs->ier) {
205 
            HAL_READ_UINT8(regs->ier,ier);
206 
            ier &= ~(regs->mask);
207 
            HAL_WRITE_UINT8(regs->ier,ier);
208 
        } else {
209 
            CYG_FAIL("Unknown interrupt vector");
210 
        }
211 
    }
212 
}
213 
 
214 
void
215 
hal_interrupt_unmask(int vector)
216 
{
217 
    CYG_BYTE ier;
218 
    const struct int_regs *regs=&interrupt_registers[vector-CYGNUM_HAL_INTERRUPT_EXTERNAL_0];
219 
    if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
220 
        HAL_READ_UINT8(CYGARC_TCSR,ier);
221 
        ier |= 0x20;
222 
        HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | ier);
223 
    } else {
224 
        if ((vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0) && regs->ier) {
225 
            HAL_READ_UINT8(regs->ier,ier);
226 
            ier |= regs->mask;
227 
            HAL_WRITE_UINT8(regs->ier,ier);
228 
        } else {
229 
            CYG_FAIL("Unknown interrupt vector");
230 
        }
231 
    }
232 
}
233 
 
234 
void
235 
hal_interrupt_acknowledge(int vector)
236 
{
237 
    CYG_BYTE isr;
238 
    const struct int_regs *regs=&interrupt_registers[vector-CYGNUM_HAL_INTERRUPT_EXTERNAL_0];
239 
    if (vector >= CYGNUM_HAL_INTERRUPT_DEND0A &&
240 
        vector <= CYGNUM_HAL_INTERRUPT_DEND1B)
241 
        return;
242 
    if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
243 
        HAL_READ_UINT8(CYGARC_TCSR,isr);
244 
        isr &= ~0x80;
245 
        HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | isr);
246 
    } else {
247 
        if ((vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0) && regs->isr) {
248 
            HAL_READ_UINT8(regs->isr,isr);
249 
            isr &= ~(regs->status);
250 
            HAL_WRITE_UINT8(regs->isr,isr);
251 
        } else {
252 
            CYG_FAIL("Unknown interrupt vector");
253 
        }
254 
    }
255 
}
256 
 
257 
void
258 
hal_interrupt_set_level(int vector,int level)
259 
{
260 
    CYG_WORD *ipr;
261 
    CYG_WORD ipr_mask;
262 
    int offset;
263 
    if ((vector < CYGNUM_HAL_INTERRUPT_EXTERNAL_0) ||
264 
        (vector > CYGNUM_HAL_INTERRUPT_EXTERNAL_15)) {
265 
        return;
266 
    } else {
267 
        vector -= 16;
268 
        ipr = (CYG_WORD *)CYGARC_IPRA + vector/4;
269 
        offset = (3 - (vector & 3)) * 4;
270 
        ipr_mask = 0x0f << offset;
271 
        *ipr &= ~ipr_mask;
272 
        *ipr |= (level & 0x07) << offset;
273 
    }
274 
}
275 
 
276 
void
277 
hal_interrupt_configure(int vector,int level,int up)
278 
{
279 
    CYG_WORD iscr,mask;
280 
    CYG_WORD *iscr_ptr;
281 
    int conf=1;
282 
    if (level) conf = 0;
283 
    if (up) conf = 2;
284 
    CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
285 
    if (vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 &&
286 
        vector <= CYGNUM_HAL_INTERRUPT_EXTERNAL_15) {
287 
        iscr_ptr = (vector <= CYGNUM_HAL_INTERRUPT_EXTERNAL_7)?CYGARC_ISCRL:CYGARC_ISCRH;
288 
        mask = 3 << ((vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0) & 7) * 2;
289 
        HAL_READ_UINT16(iscr_ptr,iscr);
290 
        iscr &= ~mask;
291 
        iscr |= conf << ((vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0) & 7) * 2;
292 
        HAL_WRITE_UINT16(iscr_ptr,iscr);
293 
    } else {
294 
        CYG_FAIL("Unhandled interrupt vector");
295 
    }
296 
}
297 
 
298 
/*------------------------------------------------------------------------*/
299 
/* End of var_misc.c                                                      */

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