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#ifndef CYGONCE_HAL_HAL_IO_H
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#define CYGONCE_HAL_HAL_IO_H
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//=============================================================================
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//
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// hal_io.h
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//
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// HAL device IO register support.
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//####DESCRIPTIONBEGIN####
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//
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// Author(s): bartv
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// Date: 2003-06-04
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//####DESCRIPTIONEND####
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//=============================================================================
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#if !defined(__ASSEMBLER__) && !defined(__LDI__)
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#include <cyg/infra/cyg_type.h>
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#endif
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#include <cyg/hal/var_io.h>
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#if !defined(__ASSEMBLER__) && !defined(__LDI__)
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//-----------------------------------------------------------------------------
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// IO Register address.
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// This type is for recording the address of an IO register.
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typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
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//-----------------------------------------------------------------------------
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// BYTE Register access.
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// Individual and vectorized access to 8 bit registers.
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#define HAL_READ_UINT8( _register_, _value_ ) \
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CYG_MACRO_START \
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((_value_) = *((volatile CYG_BYTE *)(_register_))); \
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CYG_MACRO_END
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#define HAL_WRITE_UINT8( _register_, _value_ ) \
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CYG_MACRO_START \
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(*((volatile CYG_BYTE *)(_register_)) = (_value_)); \
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CYG_MACRO_END
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#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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CYG_MACRO_START \
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cyg_count32 _i_,_j_; \
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for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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(_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
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} \
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CYG_MACRO_END
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#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
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CYG_MACRO_START \
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cyg_count32 _i_,_j_; \
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for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
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} \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// 16 bit access.
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// Individual and vectorized access to 16 bit registers.
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#define HAL_READ_UINT16( _register_, _value_ ) \
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CYG_MACRO_START \
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((_value_) = *((volatile CYG_WORD16 *)(_register_))); \
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CYG_MACRO_END
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#define HAL_WRITE_UINT16( _register_, _value_ ) \
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CYG_MACRO_START \
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(*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \
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CYG_MACRO_END
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#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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CYG_MACRO_START \
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cyg_count32 _i_,_j_; \
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for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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(_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
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} \
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CYG_MACRO_END
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#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
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CYG_MACRO_START \
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cyg_count32 _i_,_j_; \
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for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
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} \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// 32 bit access.
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// Individual and vectorized access to 32 bit registers.
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#define HAL_READ_UINT32( _register_, _value_ ) \
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CYG_MACRO_START \
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((_value_) = *((volatile CYG_WORD32 *)(_register_))); \
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CYG_MACRO_END
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#define HAL_WRITE_UINT32( _register_, _value_ ) \
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CYG_MACRO_START \
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(*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \
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CYG_MACRO_END
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#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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CYG_MACRO_START \
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cyg_count32 _i_,_j_; \
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for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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(_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
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} \
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CYG_MACRO_END
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#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
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CYG_MACRO_START \
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cyg_count32 _i_,_j_; \
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for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
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((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
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} \
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CYG_MACRO_END
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#endif
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//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_HAL_IO_H
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// End of hal_io.h
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