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skrzyp |
# ====================================================================
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#
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# hal_m68k_mcf5272.cdl
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#
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# Processor settings for a Freescale mcf5272
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#
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# ====================================================================
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# ####ECOSGPLCOPYRIGHTBEGIN####
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# -------------------------------------------
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# This file is part of eCos, the Embedded Configurable Operating System.
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# Copyright (C) 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc.
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#
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# eCos is free software; you can redistribute it and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 or (at your option) any later
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# version.
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#
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# eCos is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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# for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with eCos; if not, write to the Free Software Foundation, Inc.,
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# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# As a special exception, if other files instantiate templates or use
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# macros or inline functions from this file, or you compile this file
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# and link it with other works to produce a work based on this file,
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# this file does not by itself cause the resulting work to be covered by
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# the GNU General Public License. However the source code for this file
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# must still be made available in accordance with section (3) of the GNU
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# General Public License v2.
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#
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# This exception does not invalidate any other reasons why a work based
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# on this file might be covered by the GNU General Public License.
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# -------------------------------------------
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# ####ECOSGPLCOPYRIGHTEND####
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# ====================================================================
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#######DESCRIPTIONBEGIN####
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#
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# Author(s): bartv
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# Date: 2003-06-04
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#
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#####DESCRIPTIONEND####
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#========================================================================
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cdl_package CYGPKG_HAL_M68K_MCF5272 {
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display "MCF5272 ColdFire variant HAL"
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doc ref/hal-m68k-mcf5272.html
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parent CYGPKG_HAL_M68K_MCFxxxx
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requires CYGPKG_HAL_M68K_MCFxxxx
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implements CYGINT_HAL_M68K_VARIANT_CACHE
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implements CYGINT_HAL_M68K_VARIANT_IRAM
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hardware
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include_dir cyg/hal
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description "The mcf5272 M68k/ColdFire processor HAL package provides
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generic support for this processor."
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compile mcf5272.c
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define_proc {
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puts $::cdl_system_header "#define CYGBLD_HAL_PROC_H "
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}
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cdl_component CYGPKG_HAL_M68K_MCF5272_HARDWARE {
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display "Board-specific details"
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flavor none
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cdl_component CYGHWR_HAL_M68K_MCF5272_GPIO {
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display "Configure GPIO pins"
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flavor none
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active_if CYGHWR_HAL_M68K_MCF5272_BOARD_PINS
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script gpio.cdl
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description "
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MCF5272 processors have 48 multi-purpose pins which can
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be used for on-chip peripherals or for general purpose I/O.
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Provided the platform HAL provides the appropriate information
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the processor HAL will automatically set up each pin early on
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during system initialization."
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}
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cdl_component CYGHWR_HAL_M68K_MCFxxxx_UART0 {
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display "UART0 details"
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flavor bool
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default_value { (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB0 == "txd0") || (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB1 == "rxd0") }
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description "
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MCF5272 processors have three built-in UARTs which can be
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used for HAL diagnostics or through the serial driver
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CYGPKG_DEVS_SERIAL_MCFxxxx. By default support for each
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UART is enabled if the relevant GPIO configuration options
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are appropriate, disabled otherwise. Users can override this if
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necessary, for example if the pins should come up in GPIO mode
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but may be switched to UART mode later on."
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cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS {
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display "UART0 RTS connected"
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flavor bool
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default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB3 == "rts0" }
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implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
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description "
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This option enables support elsewhere in the system
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when the UART0 RTS signal is connected to a processor pin."
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}
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cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_CTS {
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display "UART0 CTS connected"
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flavor bool
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default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTB_PB2 == "cts0" }
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implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
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description "
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This option enables support elsewhere in the system
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when the UART0 CTS signal is connected to a processor pin."
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}
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cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART0_RS485_RTS {
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display "UART0 RS485 support"
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flavor bool
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default_value 0
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active_if CYGHWR_HAL_M68K_MCFxxxx_UART0_RTS
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requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "uart0" }
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description "
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If the UART0 signals are connected to an RS485 transceiver instead of
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an RS232 transceiver and the UART0 RTS line activates that transceiver
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then this option can be enabled. It primarily affects h/w flow control
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and transmit code within the generic mcfxxxx serial driver."
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}
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}
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cdl_component CYGHWR_HAL_M68K_MCFxxxx_UART1 {
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display "UART1 details"
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flavor bool
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default_value { (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD4 == "txd1") || (CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD1 == "rxd1") }
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description "
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MCF5272 processors have two built-in UARTs which can be
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used for HAL diagnostics or through the serial driver
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CYGPKG_DEVS_SERIAL_MCFxxxx. By default support for each
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UART is enabled if the relevant GPIO configuration options
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are appropriate, disabled otherwise. Users can override this if
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necessary, for example if the pins should come up in GPIO mode
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but may be switched to UART mode later on."
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cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_RTS {
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display "UART1 RTS connected"
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flavor bool
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default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD3 == "rts1" }
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implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
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description "
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This option enables support elsewhere in the system
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when the UART1 RTS signal is connected to a processor pin."
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}
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cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_CTS {
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display "UART1 CTS connected"
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flavor bool
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default_value { CYGHWR_HAL_M68K_MCF5272_GPIO_PORTD_PD2 == "cts1" }
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implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW
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description "
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This option enables support elsewhere in the system
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when the UART1 CTS signal is connected to a processor pin."
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}
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cdl_option CYGHWR_HAL_M68K_MCFxxxx_UART1_RS485_RTS {
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display "UART1 RS485 support"
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flavor bool
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default_value 0
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active_if CYGHWR_HAL_M68K_MCFxxxx_UART1_RTS
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requires { CYGHWR_HAL_M68K_MCFxxxx_DIAGNOSTICS_PORT != "uart1" }
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description "
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If the UART1 signals are connected to an RS485 transceiver instead of
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an RS232 transceiver and the UART1 RTS line activates that transceiver
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then this option can be enabled. This primarily affects h/w flow control
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and transmit code within the generic mcfxxxx serial driver."
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}
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}
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}
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cdl_option CYGIMP_HAL_M68K_MCF5272_IDLE {
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display "Idle thread behaviour"
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flavor data
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legal_values { "run" "sleep" "stop" }
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default_value { is_loaded(CYGPKG_CPULOAD) ? "run" : "sleep" }
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description "
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The processor can automatically enter a low power mode whenever
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the system is idle. In run mode the cpu just spins. In sleep mode
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the cpu clock is disabled but peripherals continue running, and any
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interrupt will wake up the cpu. In stop mode the on-chip peripherals
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are shut down as well and an external interrupt is required. The
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MCF5272 provides finer-grained control over power management via
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the PMR power management register but the processor HAL leaves
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this to the application."
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}
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cdl_option CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER {
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display "Support profiling"
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active_if CYGPKG_PROFILE_GPROF
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default_value 1
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implements CYGINT_PROFILE_HAL_TIMER
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compile mcf5272_profile.S
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description "
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The MCF5272 processor HAL can provide support for gprof-based
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profiling. This uses timer TMR2 to generate regular interrupts,
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and the interrupt handler records the PC at the time of the
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interrupt."
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}
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cdl_option CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MIN {
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display "Lowest permitted interrupt priority"
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flavor data
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calculated 1
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description "
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In the MCF5272 processor HAL interrupt priorities are mapped
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directly onto M68K IPL levels, so valid priorities are in the
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range 1 to 7. However IPL level 7 is non-maskable so should not
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be used by typical eCos code."
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}
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cdl_option CYGNUM_HAL_M68K_MCFxxxx_ISR_PRIORITY_MAX {
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display "Lowest permitted interrupt priority"
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flavor data
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calculated 6
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description "
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In the MCF5272 processor HAL interrupt priorities are mapped
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directly onto M68K IPL levels, so valid priorities are in the
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range 1 to 7. However IPL level 7 is non-maskable so should not
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be used by typical eCos code."
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}
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}
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