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##=============================================================================
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##
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## proc.inc
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##
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## mcf5272 processor
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): bartv
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## Date: 2003-06-04
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######DESCRIPTIONEND####
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##=============================================================================
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#include
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// Vectors support.
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// The 5272's interrupt vectors go up to slot 96: the standard 64 plus another
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// 32 for the on-chip peripherals.
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#define HAL_M68K_VSR_COUNT 96
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// The chip has 4K on-chip RAM so enable the relevant init code in vectors.S
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#define _HAL_M68K_INITIALIZE_IRAM_ 1
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// Fixed vectors data. The cacr cache control register is write-only so
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// a shadow copy is needed. This has to be shared between RedBoot and the
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// application, otherwise confusing things can happen when both manipulate
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// the cache e.g. during debugging. Shadow copies are also needed to
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// implement interrupt priorities. Some space is allocated for future
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// expansion.
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.macro _hal_mcf5272_ram_vectors_
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.global hal_mcf5272_cacr
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hal_mcf5272_cacr:
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.long 0
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.global hal_mcf5272_icr_pri_mirror
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hal_mcf5272_icr_pri_mirror:
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.long 0, 0, 0, 0
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.rept 11
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.long 0
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.endr
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.endm
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#define _HAL_M68K_PROCESSOR_RAM_VECTORS_ _hal_mcf5272_ram_vectors_
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// ----------------------------------------------------------------------------
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// Utility macros for initialization. It is assumed that the platform HAL
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// has provided the magic numbers.
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// Remap. Typically on an MCF5272 board flash memory starts of at location
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// 0, everything else is still disabled. The flash needs to be moved to
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// its final location, usually in high memory, while we are still running
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// out of flash. The way to do this is to set the mask in the cs option
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// register to 0, causing the flash to be mirrored throughout the address
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// space, then branch to the actual flash location, and then the rest of
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// the memory map can be sorted out. To access CSOR0, first we need to map
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// the MBAR into memory. MBAR has priority over chip selects so it will
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// remain visible even if the flash is mirrored.
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.macro _hal_mcf5272_remap_flash_
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move.l # _HAL_MCF5272_MBAR_VALUE_, %d0
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movec.l %d0, %mbar
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move.l # HAL_MCFxxxx_MBAR, %a5
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move.l # (_HAL_MCF5272_CSOR0_VALUE_ & ~HAL_MCF5272_CSOR_BA_MASK), %d0
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move.l %d0, HAL_MCF5272_CSOR0 (%a5)
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// dBUG inserts a nop here and another in the branch location.
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// Presumably this avoids pipeline problems if the memory map
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// changes under the pipeline's feet.
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nop
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// Now we can branch to the real location in the flash. The linker
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// script is set up so that this code is mapped to the right place.
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jmp _hal_mcf5272_flash_
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// Put the next code in a separate section to stop the assembler turning
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// the above jump into a PC-relative one
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.section ".m68k_start.0", "ax"
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_hal_mcf5272_flash_:
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// Another nop as per dBUG
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nop
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// We are now running out of flash. CSOR0 and MBAR have been changed,
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// everything else is still at reset values.
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.endm
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// Initialize all the system registers. Typically this is done unconditionally
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// on the off-chance that RedBoot and the application need different values.
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.macro _hal_mcf5272_init_sysregs_
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move.l # (HAL_MCFxxxx_CACR_CINV), %d0
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movec.l %d0, %cacr
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move.l # (CYGNUM_HAL_M68K_MCF5272_ACR0), %d0
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movec.l %d0, %acr0
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move.l # (CYGNUM_HAL_M68K_MCF5272_ACR1), %d0
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movec.l %d0, %acr1
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move.l # (CYGNUM_HAL_M68K_MCF5272_ROMBAR), %d0
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movec.l %d0, %rombar
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move.l # (CYGNUM_HAL_M68K_MCF5272_RAMBAR), %d0
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movec.l %d0, %rambar0
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move.l # (CYGNUM_HAL_M68K_MCF5272_CACR), %d0
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movec.l %d0, %cacr
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.endm
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// Initialize memory, including starting the SDRAM controller
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.macro _hal_mcf5272_init_memory_
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move.w # CYGNUM_HAL_M68K_MCF5272_SCR, %d0
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move.w %d0, HAL_MCF5272_SCR (%a5)
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move.w # 0xFFFF, %d0
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move.w %d0, HAL_MCF5272_SPR (%a5)
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// chip selects and SDRAM. CS0 should always be connected to
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// a boot flash. The BW bits are set from external pins
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// QSPI_CS0/CSPI_CLK and are preserved here. Arguably that
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// should not be necessary but it allows for platforms where
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// the hardware has gone through several revisions and it
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// is undesirable to build different images for different
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// revisions. The overhead is small, just two instructions.
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move.l HAL_MCF5272_CSBR0 (%a5), %d0
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andi.l # HAL_MCF5272_CSBR_BW_MASK, %d0
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ori.l # (_HAL_MCF5272_CSBR0_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR0 (%a5)
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move.l # (_HAL_MCF5272_CSOR0_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR0 (%a5)
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// Chip selects 1-6 may or may not be connected. If not just leave
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// them to their default disabled state.
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.ifdef _HAL_MCF5272_CSBR1_VALUE_
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move.l # (_HAL_MCF5272_CSBR1_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR1 (%a5)
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move.l # (_HAL_MCF5272_CSOR1_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR1 (%a5)
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.endif
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.ifdef _HAL_MCF5272_CSBR2_VALUE_
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move.l # (_HAL_MCF5272_CSBR2_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR2 (%a5)
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move.l # (_HAL_MCF5272_CSOR2_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR2 (%a5)
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.endif
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.ifdef _HAL_MCF5272_CSBR3_VALUE_
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move.l # (_HAL_MCF5272_CSBR3_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR3 (%a5)
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move.l # (_HAL_MCF5272_CSOR3_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR3 (%a5)
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.endif
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.ifdef _HAL_MCF5272_CSBR4_VALUE_
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move.l # (_HAL_MCF5272_CSBR4_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR4 (%a5)
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move.l # (_HAL_MCF5272_CSOR4_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR4 (%a5)
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.endif
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.ifdef _HAL_MCF5272_CSBR5_VALUE_
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move.l # (_HAL_MCF5272_CSBR5_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR5 (%a5)
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move.l # (_HAL_MCF5272_CSOR5_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR5 (%a5)
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.endif
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.ifdef _HAL_MCF5272_CSBR6_VALUE_
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move.l # (_HAL_MCF5272_CSBR6_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR6 (%a5)
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move.l # (_HAL_MCF5272_CSOR6_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR6 (%a5)
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.endif
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// CS7 will go the SDRAM.
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move.l # (_HAL_MCF5272_CSBR7_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSBR7 (%a5)
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move.l # (_HAL_MCF5272_CSOR7_VALUE_), %d0
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move.l %d0, HAL_MCF5272_CSOR7 (%a5)
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// The SDRAM should now be ready for its first commands.
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// The timer register needs to be done first, then the
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// control register, and finally a dummy write to memory.
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// That dummy write causes the SDRAM controller to take
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// the necessary actions, and the memory should be usable
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// a few cycles later.
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move.l # (_HAL_MCF5272_SDTR_VALUE_), %d0
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move.l %d0, HAL_MCF5272_SDTR (%a5)
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move.l # (_HAL_MCF5272_SDCR_VALUE_), %d0
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move.l %d0, HAL_MCF5272_SDCR (%a5)
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clr.l 0
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.endm
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// ----------------------------------------------------------------------------
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// Now that the utility macros are defined include the platform HAL.
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#include
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// And if the platform HAL requests it, provide the standard initialization
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// code.
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#if defined(_HAL_MCF5272_STANDARD_INIT_ROM_)
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.macro _hal_m68k_mcf5272_start_
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// Initial stack and program counter
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.long 0
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.long 8
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_hal_mcf5272_remap_flash_
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.endm
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.macro _hal_m68k_mcf5272_setup1_
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_hal_mcf5272_init_sysregs_
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_hal_mcf5272_init_memory_
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.endm
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# define _HAL_M68K_START_ _hal_m68k_mcf5272_start_
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# define _HAL_M68K_PLATFORM_SETUP1_ _hal_m68k_mcf5272_setup1_
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# define _HAL_M68K_COPY_ROM_DATA_TO_RAM_ 1
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#elif defined(_HAL_MCF5272_STANDARD_INIT_RAM_)
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.macro _hal_m68k_mcf5272_start_
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.endm
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.macro _hal_m68k_mcf5272_setup1_
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// Always initialize the remaining system registers, in case the
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// application needs different values from RedBoot for some reason.
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_hal_mcf5272_init_sysregs_
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.endm
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# define _HAL_M68K_START_ _hal_m68k_mcf5272_start_
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# define _HAL_M68K_PLATFORM_SETUP1_ _hal_m68k_mcf5272_setup1_
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#endif
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// ----------------------------------------------------------------------------
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// end of proc.inc
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