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skrzyp |
//=============================================================================
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//
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// proc_io.h
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//
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// Details of mcf5272 memory-mapped hardware
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2003, 2004, 2006, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): bartv
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// Date: 2003-06-04
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//
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//####DESCRIPTIONEND####
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//=============================================================================
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// This header gets #include'd twice by var_io.h. The first time is to
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// define the peripherals which are shared with the 5282. The second
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// time is for overriding, in case of small differences between this
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// processor's on-chip peripherals and the 5282's.
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#if !defined(CYGONCE_HAL_PROC_IO_H_FIRST)
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# define CYGONCE_HAL_PROC_IO_H_FIRST
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# include <pkgconf/system.h>
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# include <pkgconf/hal_m68k_mcf5272.h>
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# include CYGBLD_HAL_PLATFORM_H
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# define HAL_MCFxxxx_HAS_MCF5282_RAMBAR 1
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# define HAL_MCFxxxx_HAS_MCF5282_VBR 1
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# define HAL_MCFxxxx_HAS_MCF5282_CACR_ACR 1
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# define HAL_MCFxxxx_HAS_MCF5282_UART 2
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# define HAL_MCFxxxx_UART0_BASE (HAL_MCFxxxx_MBAR + 0x00000100)
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# define HAL_MCFxxxx_UART1_BASE (HAL_MCFxxxx_MBAR + 0x00000140)
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# define HAL_MCFxxxx_UART0_RXFIFO_SIZE 24
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# define HAL_MCFxxxx_UART1_RXFIFO_SIZE 24
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# define HAL_MCFxxxx_HAS_MCF5282_QSPI 1
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# define HAL_MCFxxxx_QSPI0_BASE (HAL_MCFxxxx_MBAR + 0x000000A0)
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# define HAL_MCFxxxx_QSPI_SINGLETON_BASE HAL_MCFxxxx_QSPI0_BASE
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# define HAL_MCFxxxx_QSPI_SINGLETON_ISRVEC CYGNUM_HAL_ISR_QSPI
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# define HAL_MCFxxxx_QSPI_SINGLETON_ISRPRI CYGNUM_HAL_M68K_MCF5272_QSPI_ISRPRI
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# define HAL_MCFxxxx_HAS_MCF5282_ETH 1
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# define HAL_MCFxxxx_ETH0_BASE (HAL_MCFxxxx_MBAR + 0x0840)
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// ----------------------------------------------------------------------------
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#elif !defined(CYGONCE_HAL_PROC_IO_H_SECOND)
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# define CYGONCE_HAL_PROC_IO_H_SECOND
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// Now to handle the differences between the MCF5272 and the MCF5282
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// MBAR - controls access to the system integration module
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#define HAL_MCF5272_MBAR_BA_MASK 0xFFFF0000
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#define HAL_MCF5272_MBAR_BA_SHIFT 16
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#define HAL_MCF5272_MBAR_SC (0x01 << 4)
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#define HAL_MCF5272_MBAR_SD (0x01 << 3)
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#define HAL_MCF5272_MBAR_UC (0x01 << 2)
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#define HAL_MCF5272_MBAR_UD (0x01 << 1)
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#define HAL_MCF5272_MBAR_V (0x01 << 0)
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# undef HAL_MCFxxxx_RAMBAR
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# define HAL_MCFxxxx_RAMBAR 0x0C04
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# undef HAL_MCFxxxx_RAMBAR_PRI_MASK
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# undef HAL_MCFxxxx_RAMBAR_PRI_SHIFT
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# undef HAL_MCFxxxx_RAMBAR_PRI_CPU_CPU
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# undef HAL_MCFxxxx_RAMBAR_PRI_CPU_DMA
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# undef HAL_MCFxxxx_RAMBAR_PRI_DMA_CPU
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# undef HAL_MCFxxxx_RAMBAR_PRI_DMA_DMA
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# undef HAL_MCFxxxx_RAMBAR_SPV
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# undef HAL_MCFxxxx_CACR_DISI
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# undef HAL_MCFxxxx_CACR_DISD
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# undef HAL_MCFxxxx_CACR_INVI
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# undef HAL_MCFxxxx_CACR_INVD
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# undef HAL_MCFxxxx_CACR_EUSP
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// The UARTs. Five additional registers and some extra bits.
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// Baud rates can be set more precisely using the fractional
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// register.
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# define HAL_MCFxxxx_UARTx_UABU 0x20
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# define HAL_MCFxxxx_UARTx_UABL 0x24
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# define HAL_MCFxxxx_UARTx_UTF 0x28
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# define HAL_MCFxxxx_UARTx_URF 0x2C
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# define HAL_MCFxxxx_UARTx_UFPD 0x30
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#define HAL_MCFxxxx_UARTx_UCR_ENAB (0x01 << 7)
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#define HAL_MCFxxxx_UARTx_UISR_ABC (0x01 << 6)
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#define HAL_MCFxxxx_UARTx_UISR_RXFIFO (0x01 << 5)
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#define HAL_MCFxxxx_UARTx_UISR_TXFIFO (0x01 << 4)
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#define HAL_MCFxxxx_UARTx_UISR_RXFTO (0x01 << 3)
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#define HAL_MCFxxxx_UARTx_UIMR_ABC (0x01 << 6)
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#define HAL_MCFxxxx_UARTx_UIMR_RXFIFO (0x01 << 5)
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#define HAL_MCFxxxx_UARTx_UIMR_TXFIFO (0x01 << 4)
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#define HAL_MCFxxxx_UARTx_UIMR_RXFTO (0x01 << 3)
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// Automatic RTS control depending on fifo levels
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#define HAL_MCFxxxx_UARTx_UACR_RTSL_MASK (0x03 << 1)
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#define HAL_MCFxxxx_UARTx_UACR_RTSL_DISABLED (0x00 << 1)
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#define HAL_MCFxxxx_UARTx_UACR_RTSL_25 (0x01 << 1)
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#define HAL_MCFxxxx_UARTx_UACR_RTSL_50 (0x02 << 1)
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#define HAL_MCFxxxx_UARTx_UACR_RTSL_75 (0x03 << 1)
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// Fifo control
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#define HAL_MCFxxxx_UARTx_UTF_TXS_MASK (0x03 << 6)
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#define HAL_MCFxxxx_UARTx_UTF_TXS_INHIBIT (0x00 << 6)
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#define HAL_MCFxxxx_UARTx_UTF_TXS_25 (0x01 << 6)
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#define HAL_MCFxxxx_UARTx_UTF_TXS_50 (0x02 << 6)
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#define HAL_MCFxxxx_UARTx_UTF_TXS_75 (0x03 << 6)
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#define HAL_MCFxxxx_UARTx_UTF_FULL (0x01 << 5)
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#define HAL_MCFxxxx_UARTx_UTF_TXB_MASK (0x1F << 0)
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#define HAL_MCFxxxx_UARTx_URF_RXS_MASK (0x03 << 6)
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#define HAL_MCFxxxx_UARTx_URF_RXS_INHIBIT (0x00 << 6)
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#define HAL_MCFxxxx_UARTx_URF_RXS_25 (0x01 << 6)
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#define HAL_MCFxxxx_UARTx_URF_RXS_50 (0x02 << 6)
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#define HAL_MCFxxxx_UARTx_URF_RXS_75 (0x03 << 6)
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#define HAL_MCFxxxx_UARTx_URF_FULL (0x01 << 5)
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#define HAL_MCFxxxx_UARTx_URF_RXB_MASK (0x1F << 0)
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#define HAL_MCFxxxx_UARTx_UFPD_FD_MASK (0x0F << 0)
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#undef HAL_MCFxxxx_UARTx_SET_BAUD
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#define HAL_MCFxxxx_UARTx_SET_BAUD(_base_, _baud_) \
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CYG_MACRO_START \
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cyg_uint8 _udu_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (32 * (_baud_))) >> 8)); \
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cyg_uint8 _udl_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (32 * (_baud_))) & 0x00FF)); \
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cyg_uint8 _ufpd_ = ((cyg_uint8) ((CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * (_baud_))) & 0x000F)); \
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HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG1, _udu_); \
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HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG2, _udl_); \
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HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UFPD, _ufpd_); \
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CYG_MACRO_END
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// QSPI. It is not clear the QWR CPTQP bits are defined. Otherwise the device
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// matches the 5282's exactly.
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// Ethernet. There are many differences between the 5272 and the 5282
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// implementations.
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# undef HAL_MCFxxxx_ETHx_ECR
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# define HAL_MCFxxxx_ETHx_ECR 0x0000
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# define HAL_MCFxxxx_ETHx_IVSR 0x000C
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# undef HAL_MCFxxxx_ETHx_MIBC
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# undef HAL_MCFxxxx_ETHx_RCR
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# define HAL_MCFxxxx_ETHx_RCR 0x0104
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# define HAL_MCFxxxx_ETHx_MFLR 0x0108
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# undef HAL_MCFxxxx_ETHx_TCR
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# define HAL_MCFxxxx_ETHx_TCR 0x0144
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# undef HAL_MCFxxxx_ETHx_PALR
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# define HAL_MCFxxxx_ETHx_PALR 0x03C0
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# undef HAL_MCFxxxx_ETHx_PAUR
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# define HAL_MCFxxxx_ETHx_PAUR 0x03C4
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# undef HAL_MCFxxxx_ETHx_OPD
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# undef HAL_MCFxxxx_ETHx_IAUR
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# undef HAL_MCFxxxx_ETHx_IALR
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# undef HAL_MCFxxxx_ETHx_GAUR
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# define HAL_MCFxxxx_ETHx_GAUR 0x03C8
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# undef HAL_MCFxxxx_ETHx_GALR
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# define HAL_MCFxxxx_ETHx_GALR 0x03CC
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# define HAL_MCFxxxx_ETHx_TFSR 0x00AC
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# undef HAL_MCFxxxx_ETHx_TFWR
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# define HAL_MCFxxxx_ETHx_TFWR 0x00A4
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# undef HAL_MCFxxxx_ETHx_FRBR
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# define HAL_MCFxxxx_ETHx_FRBR 0x008C
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# undef HAL_MCFxxxx_ETHx_FRSR
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# define HAL_MCFxxxx_ETHx_FRSR 0x0090
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# undef HAL_MCFxxxx_ETHx_ERDSR
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# define HAL_MCFxxxx_ETHx_ERDSR 0x03D0
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# undef HAL_MCFxxxx_ETHx_ETDSR
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# define HAL_MCFxxxx_ETHx_ETDSR 0x03D4
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# undef HAL_MCFxxxx_ETHx_EMRBR
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# define HAL_MCFxxxx_ETHx_EMRBR 0x03D8
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# undef HAL_MCFxxxx_ETHx_RMON_T_DROP
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# undef HAL_MCFxxxx_ETHx_RMON_T_PACKETS
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# undef HAL_MCFxxxx_ETHx_RMON_T_BC_PKT
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# undef HAL_MCFxxxx_ETHx_RMON_T_MC_PKT
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# undef HAL_MCFxxxx_ETHx_RMON_T_CRC_ALIGN
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# undef HAL_MCFxxxx_ETHx_RMON_T_UNDERSIZE
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# undef HAL_MCFxxxx_ETHx_RMON_T_OVERSIZE
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# undef HAL_MCFxxxx_ETHx_RMON_T_FRAG
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# undef HAL_MCFxxxx_ETHx_RMON_T_JAB
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# undef HAL_MCFxxxx_ETHx_RMON_T_COL
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# undef HAL_MCFxxxx_ETHx_RMON_T_P64
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# undef HAL_MCFxxxx_ETHx_RMON_T_P65TO127
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# undef HAL_MCFxxxx_ETHx_RMON_T_P128TO255
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# undef HAL_MCFxxxx_ETHx_RMON_T_P256TO511
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# undef HAL_MCFxxxx_ETHx_RMON_T_P512TO1023
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| 219 |
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# undef HAL_MCFxxxx_ETHx_RMON_T_P1024TO2047
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# undef HAL_MCFxxxx_ETHx_RMON_T_PGTE2048
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| 221 |
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# undef HAL_MCFxxxx_ETHx_RMON_T_OCTETS
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# undef HAL_MCFxxxx_ETHx_IEEE_T_DROP
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# undef HAL_MCFxxxx_ETHx_IEEE_T_FRAME_OK
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# undef HAL_MCFxxxx_ETHx_IEEE_T_1COL
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# undef HAL_MCFxxxx_ETHx_IEEE_T_MCOL
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# undef HAL_MCFxxxx_ETHx_IEEE_T_DEF
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| 227 |
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# undef HAL_MCFxxxx_ETHx_IEEE_T_LCOL
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| 228 |
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# undef HAL_MCFxxxx_ETHx_IEEE_T_EXCOL
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| 229 |
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# undef HAL_MCFxxxx_ETHx_IEEE_T_MACERR
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# undef HAL_MCFxxxx_ETHx_IEEE_T_CSERR
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| 231 |
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# undef HAL_MCFxxxx_ETHx_IEEE_T_SQE
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| 232 |
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# undef HAL_MCFxxxx_ETHx_IEEE_T_FDXFC
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| 233 |
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# undef HAL_MCFxxxx_ETHx_IEEE_T_OCTETS_OK
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| 234 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_PACKETS
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| 235 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_BC_PKT
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| 236 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_MC_PKT
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| 237 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_CRC_ALIGN
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| 238 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_UNDERSIZE
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| 239 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_OVERSIZE
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| 240 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_FRAG
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| 241 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_JAB
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| 242 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_RESVD_0
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| 243 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_P64
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| 244 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_P65TO127
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| 245 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_P128TO255
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| 246 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_P256TO511
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| 247 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_P512TO1023
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| 248 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_P1024TO2047
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| 249 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_GTE2048
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| 250 |
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# undef HAL_MCFxxxx_ETHx_RMON_R_OCTETS
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| 251 |
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# undef HAL_MCFxxxx_ETHx_IEEE_R_DROP
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| 252 |
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# undef HAL_MCFxxxx_ETHx_IEEE_R_FRAME_OK
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| 253 |
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# undef HAL_MCFxxxx_ETHx_IEEE_R_CRC
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| 254 |
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# undef HAL_MCFxxxx_ETHx_IEEE_R_ALIGN
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| 255 |
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# undef HAL_MCFxxxx_ETHx_IEEE_R_MACERR
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| 256 |
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# undef HAL_MCFxxxx_ETHx_IEEE_R_FDXFC
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| 257 |
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# undef HAL_MCFxxxx_ETHx_IEEE_R_OCTETS_OK
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| 258 |
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| 259 |
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# undef HAL_MCFxxxx_ETHx_EIR_LC
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| 260 |
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# undef HAL_MCFxxxx_ETHx_EIR_RL
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| 261 |
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# undef HAL_MCFxxxx_ETHx_EIR_UN
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| 262 |
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|
# define HAL_MCFxxxx_ETHx_EIR_UMINT (0x01 << 21)
|
| 263 |
|
|
|
| 264 |
|
|
# undef HAL_MCFxxxx_ETHx_EIMR_LC
|
| 265 |
|
|
# undef HAL_MCFxxxx_ETHx_EIMR_RL
|
| 266 |
|
|
# undef HAL_MCFxxxx_ETHx_EIMR_UN
|
| 267 |
|
|
|
| 268 |
|
|
# undef HAL_MCFxxxx_ETHx_MIBC_MIB_DISABLE
|
| 269 |
|
|
# undef HAL_MCFxxxx_ETHx_MIBC_MIB_IDLE
|
| 270 |
|
|
|
| 271 |
|
|
# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_MASK
|
| 272 |
|
|
# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_SHIFT
|
| 273 |
|
|
# undef HAL_MCFxxxx_ETHx_RCR_MAX_FL_VALUE
|
| 274 |
|
|
# undef HAL_MCFxxxx_ETHx_RCR_FCE
|
| 275 |
|
|
# undef HAL_MCFxxxx_ETHx_RCR_BC_REJ
|
| 276 |
|
|
|
| 277 |
|
|
# undef HAL_MCFxxxx_ETHx_TCR_RFC_PAUSE
|
| 278 |
|
|
# undef HAL_MCFxxxx_ETHx_TCR_TFC_PAUSE
|
| 279 |
|
|
|
| 280 |
|
|
# undef HAL_MCFxxxx_ETHx_OPD_OPCODE_MASK
|
| 281 |
|
|
# undef HAL_MCFxxxx_ETHx_OPD_OPCODE_SHIFT
|
| 282 |
|
|
# undef HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_MASK
|
| 283 |
|
|
# undef HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_SHIFT
|
| 284 |
|
|
|
| 285 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_SH (0x01 << 3)
|
| 286 |
|
|
|
| 287 |
|
|
# undef HAL_MCFxxxx_ETHx_TXBD_ABC
|
| 288 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_DEF (0x01 << 9)
|
| 289 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_HB (0x01 << 8)
|
| 290 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_LC (0x01 << 7)
|
| 291 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_RL (0x01 << 6)
|
| 292 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_RC_MASK (0x0F << 2)
|
| 293 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_RC_SHIFT 2
|
| 294 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_UN (0x01 << 1)
|
| 295 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_CSL (0x01 << 0)
|
| 296 |
|
|
|
| 297 |
|
|
// ----------------------------------------------------------------------------
|
| 298 |
|
|
// ----------------------------------------------------------------------------
|
| 299 |
|
|
// Next the units specific to the 5272
|
| 300 |
|
|
|
| 301 |
|
|
// The ROM base address register. The ROM size depends on the particular
|
| 302 |
|
|
// processor, and that controls how many of bits 9 to 31 are significant.
|
| 303 |
|
|
#define HAL_MCF5272_ROMBAR_WP (0x01 << 8)
|
| 304 |
|
|
// Mask cpu space and interrupt acknowledge accesses
|
| 305 |
|
|
#define HAL_MCF5272_ROMBAR_AS5 (0x01 << 5)
|
| 306 |
|
|
// Mask supervisor code accesses
|
| 307 |
|
|
#define HAL_MCF5272_ROMBAR_AS4 (0x01 << 4)
|
| 308 |
|
|
// Mask supervisor data accesses
|
| 309 |
|
|
#define HAL_MCF5272_ROMBAR_AS3 (0x01 << 3)
|
| 310 |
|
|
// Mask user code accesses
|
| 311 |
|
|
#define HAL_MCF5272_ROMBAR_AS2 (0x01 << 2)
|
| 312 |
|
|
// Mask user data accesses
|
| 313 |
|
|
#define HAL_MCF5272_ROMBAR_AS1 (0x01 << 1)
|
| 314 |
|
|
// Has the ROMBAR register been initialized yet?
|
| 315 |
|
|
#define HAL_MCF5272_ROMBAR_VALID (0x01 << 0)
|
| 316 |
|
|
|
| 317 |
|
|
// ----------------------------------------------------------------------------
|
| 318 |
|
|
// System registers in the system integration module. PMR and DIR are
|
| 319 |
|
|
// 32-bit. SCR, SPR, and ALPR are 16-bit.
|
| 320 |
|
|
|
| 321 |
|
|
#define HAL_MCF5272_SCR 0x0004
|
| 322 |
|
|
#define HAL_MCF5272_SPR 0x0006
|
| 323 |
|
|
#define HAL_MCF5272_PMR 0x0008
|
| 324 |
|
|
#define HAL_MCF5272_ALPR 0x000E
|
| 325 |
|
|
#define HAL_MCF5272_DIR 0x0010
|
| 326 |
|
|
|
| 327 |
|
|
// System configuration register
|
| 328 |
|
|
#define HAL_MCF5272_SCR_RSTSRC_MASK (0x03 << 12)
|
| 329 |
|
|
#define HAL_MCF5272_SCR_RSTSRC_RSTI (0x01 << 12)
|
| 330 |
|
|
#define HAL_MCF5272_SCR_RSTSRC_WATCHDOG (0x02 << 12)
|
| 331 |
|
|
#define HAL_MCF5272_SCR_RSTSRC_RSTI_DRESETEN (0x03 << 12)
|
| 332 |
|
|
#define HAL_MCF5272_SCR_PRIORITY_MASK (0x01 << 8)
|
| 333 |
|
|
#define HAL_MCF5272_SCR_PRIORITY_ETHERNET (0x00 << 8)
|
| 334 |
|
|
#define HAL_MCF5272_SCR_PRIORITY_CPU (0x01 << 8)
|
| 335 |
|
|
#define HAL_MCF5272_SCR_AR_MASK (0x01 << 7)
|
| 336 |
|
|
#define HAL_MCF5272_SCR_AR_RELINQUISH (0x00 << 7)
|
| 337 |
|
|
#define HAL_MCF5272_SCR_AR_INCLUDE (0x01 << 7)
|
| 338 |
|
|
#define HAL_MCF5272_SCR_AR_SOFTRST (0x01 << 6)
|
| 339 |
|
|
#define HAL_MCF5272_SCR_BUSLOCK_MASK (0x01 << 3)
|
| 340 |
|
|
#define HAL_MCF5272_SCR_BUSLOCK_ARBITRATION (0x00 << 3)
|
| 341 |
|
|
#define HAL_MCF5272_SCR_BUSLOCK_RETAIN (0x01 << 3)
|
| 342 |
|
|
#define HAL_MCF5272_SCR_HWR_MASK (0x07 << 0)
|
| 343 |
|
|
#define HAL_MCF5272_SCR_HWR_128 (0x00 << 0)
|
| 344 |
|
|
#define HAL_MCF5272_SCR_HWR_256 (0x01 << 0)
|
| 345 |
|
|
#define HAL_MCF5272_SCR_HWR_512 (0x02 << 0)
|
| 346 |
|
|
#define HAL_MCF5272_SCR_HWR_1024 (0x03 << 0)
|
| 347 |
|
|
#define HAL_MCF5272_SCR_HWR_2048 (0x04 << 0)
|
| 348 |
|
|
#define HAL_MCF5272_SCR_HWR_4096 (0x05 << 0)
|
| 349 |
|
|
#define HAL_MCF5272_SCR_HWR_8192 (0x06 << 0)
|
| 350 |
|
|
#define HAL_MCF5272_SCR_HWR_16384 (0x07 << 0)
|
| 351 |
|
|
|
| 352 |
|
|
// System protection register
|
| 353 |
|
|
#define HAL_MCF5272_SPR_ADC (0x01 << 15)
|
| 354 |
|
|
#define HAL_MCF5272_SPR_WPV (0x01 << 14)
|
| 355 |
|
|
#define HAL_MCF5272_SPR_SMV (0x01 << 13)
|
| 356 |
|
|
#define HAL_MCF5272_SPR_PE (0x01 << 12)
|
| 357 |
|
|
#define HAL_MCF5272_SPR_HWT (0x01 << 11)
|
| 358 |
|
|
#define HAL_MCF5272_SPR_RPV (0x01 << 10)
|
| 359 |
|
|
#define HAL_MCF5272_SPR_EXT (0x01 << 9)
|
| 360 |
|
|
#define HAL_MCF5272_SPR_SUV (0x01 << 8)
|
| 361 |
|
|
#define HAL_MCF5272_SPR_ADCEN (0x01 << 7)
|
| 362 |
|
|
#define HAL_MCF5272_SPR_WPVEN (0x01 << 6)
|
| 363 |
|
|
#define HAL_MCF5272_SPR_SMVEN (0x01 << 5)
|
| 364 |
|
|
#define HAL_MCF5272_SPR_PEEN (0x01 << 4)
|
| 365 |
|
|
#define HAL_MCF5272_SPR_HWTEN (0x01 << 3)
|
| 366 |
|
|
#define HAL_MCF5272_SPR_RPVEN (0x01 << 2)
|
| 367 |
|
|
#define HAL_MCF5272_SPR_EXTEN (0x01 << 1)
|
| 368 |
|
|
#define HAL_MCF5272_SPR_SUVEN (0x01 << 0)
|
| 369 |
|
|
|
| 370 |
|
|
// Power management register. For power-down, 0 is enabled, 1 disabled.
|
| 371 |
|
|
// For wakeup 0 is disabled, 1 enabled
|
| 372 |
|
|
#define HAL_MCF5272_PMR_BDMPDN (0x01 << 31)
|
| 373 |
|
|
#define HAL_MCF5272_PMR_ENETPDN (0x01 << 26)
|
| 374 |
|
|
#define HAL_MCF5272_PMR_PLIPDN (0x01 << 25)
|
| 375 |
|
|
#define HAL_MCF5272_PMR_DRAMPDN (0x01 << 24)
|
| 376 |
|
|
#define HAL_MCF5272_PMR_DMAPDN (0x01 << 23)
|
| 377 |
|
|
#define HAL_MCF5272_PMR_PWMPDN (0x01 << 22)
|
| 378 |
|
|
#define HAL_MCF5272_PMR_QSPIPDN (0x01 << 21)
|
| 379 |
|
|
#define HAL_MCF5272_PMR_TIMERPDN (0x01 << 20)
|
| 380 |
|
|
#define HAL_MCF5272_PMR_GPIOPDN (0x01 << 19)
|
| 381 |
|
|
#define HAL_MCF5272_PMR_USBPDN (0x01 << 18)
|
| 382 |
|
|
#define HAL_MCF5272_PMR_UART1PDN (0x01 << 17)
|
| 383 |
|
|
#define HAL_MCF5272_PMR_UART0PDN (0x01 << 16)
|
| 384 |
|
|
#define HAL_MCF5272_PMR_USBWK (0x01 << 10)
|
| 385 |
|
|
#define HAL_MCF5272_PMR_UART1WK (0x01 << 9)
|
| 386 |
|
|
#define HAL_MCF5272_PMR_UART0WK (0x01 << 8)
|
| 387 |
|
|
#define HAL_MCF5272_PMR_MOS (0x01 << 5)
|
| 388 |
|
|
#define HAL_MCF5272_PMR_SLPEN (0x01 << 4)
|
| 389 |
|
|
|
| 390 |
|
|
// Device identification register
|
| 391 |
|
|
#define HAL_MCF5272_DIR_VERSION_MASK (0x0F << 28)
|
| 392 |
|
|
#define HAL_MCF5272_DIR_VERSION_SHIFT 28
|
| 393 |
|
|
#define HAL_MCF5272_DIR_DESIGN_CENTER_MASK (0x3F << 22)
|
| 394 |
|
|
#define HAL_MCF5272_DIR_DESIGN_CENTER_SHIFT 22
|
| 395 |
|
|
#define HAL_MCF5272_DIR_DEVICE_NUMBER_MASK (0x3FF << 12)
|
| 396 |
|
|
#define HAL_MCF5272_DIR_DEVICE_NUMBER_SHIFT 12
|
| 397 |
|
|
#define HAL_MCF5272_DIR_JEDEC_ID_MASK (0x7FF << 1)
|
| 398 |
|
|
#define HAL_MCF5272_DIR_JEDEC_ID_SHIFT 1
|
| 399 |
|
|
|
| 400 |
|
|
// ----------------------------------------------------------------------------
|
| 401 |
|
|
// The software watchdog. All registers are 2-bytes wide.
|
| 402 |
|
|
|
| 403 |
|
|
#define HAL_MCF5272_WRRR 0x0280
|
| 404 |
|
|
#define HAL_MCF5272_WIRR 0x0284
|
| 405 |
|
|
#define HAL_MCF5272_WCR 0x0288
|
| 406 |
|
|
#define HAL_MCF5272_WER 0x028C
|
| 407 |
|
|
|
| 408 |
|
|
// ----------------------------------------------------------------------------
|
| 409 |
|
|
// The interrupt controller. PIVR is a single byte, the others are 32-bit.
|
| 410 |
|
|
// The bits within the registers are defined by the ISR numbers in proc_intr.h
|
| 411 |
|
|
#define HAL_MCF5272_ICR1 0x0020
|
| 412 |
|
|
#define HAL_MCF5272_ICR2 0x0024
|
| 413 |
|
|
#define HAL_MCF5272_ICR3 0x0028
|
| 414 |
|
|
#define HAL_MCF5272_ICR4 0x002C
|
| 415 |
|
|
#define HAL_MCF5272_ISR 0x0030
|
| 416 |
|
|
#define HAL_MCF5272_PITR 0x0034
|
| 417 |
|
|
#define HAL_MCF5272_PIWR 0x0038
|
| 418 |
|
|
#define HAL_MCF5272_PIVR 0x003F
|
| 419 |
|
|
|
| 420 |
|
|
// ----------------------------------------------------------------------------
|
| 421 |
|
|
// Chip select module. All registers are 32-bit
|
| 422 |
|
|
#define HAL_MCF5272_CSBR0 0x0040
|
| 423 |
|
|
#define HAL_MCF5272_CSOR0 0x0044
|
| 424 |
|
|
#define HAL_MCF5272_CSBR1 0x0048
|
| 425 |
|
|
#define HAL_MCF5272_CSOR1 0x004C
|
| 426 |
|
|
#define HAL_MCF5272_CSBR2 0x0050
|
| 427 |
|
|
#define HAL_MCF5272_CSOR2 0x0054
|
| 428 |
|
|
#define HAL_MCF5272_CSBR3 0x0058
|
| 429 |
|
|
#define HAL_MCF5272_CSOR3 0x005C
|
| 430 |
|
|
#define HAL_MCF5272_CSBR4 0x0060
|
| 431 |
|
|
#define HAL_MCF5272_CSOR4 0x0064
|
| 432 |
|
|
#define HAL_MCF5272_CSBR5 0x0068
|
| 433 |
|
|
#define HAL_MCF5272_CSOR5 0x006C
|
| 434 |
|
|
#define HAL_MCF5272_CSBR6 0x0070
|
| 435 |
|
|
#define HAL_MCF5272_CSOR6 0x0074
|
| 436 |
|
|
#define HAL_MCF5272_CSBR7 0x0078
|
| 437 |
|
|
#define HAL_MCF5272_CSOR7 0x007C
|
| 438 |
|
|
|
| 439 |
|
|
#define HAL_MCF5272_CSBR_BA_MASK (0xFFFFF000)
|
| 440 |
|
|
#define HAL_MCF5272_CSBR_EBI_MASK (0x03 << 10)
|
| 441 |
|
|
#define HAL_MCF5272_CSBR_EBI_16_32 (0x00 << 10)
|
| 442 |
|
|
#define HAL_MCF5272_CSBR_EBI_SDRAM (0x01 << 10)
|
| 443 |
|
|
#define HAL_MCF5272_CSBR_EBI_8 (0x03 << 10)
|
| 444 |
|
|
#define HAL_MCF5272_CSBR_BW_MASK (0x03 << 8)
|
| 445 |
|
|
#define HAL_MCF5272_CSBR_BW_32 (0x00 << 8)
|
| 446 |
|
|
#define HAL_MCF5272_CSBR_BW_8 (0x01 << 8)
|
| 447 |
|
|
#define HAL_MCF5272_CSBR_BW_16 (0x02 << 8)
|
| 448 |
|
|
#define HAL_MCF5272_CSBR_BW_CACHELINE (0x03 << 8)
|
| 449 |
|
|
#define HAL_MCF5272_CSBR_SUPER (0x01 << 7)
|
| 450 |
|
|
#define HAL_MCF5272_CSBR_TT_MASK (0x03 << 5)
|
| 451 |
|
|
#define HAL_MCF5272_CSBR_TM_MASK (0x07 << 2)
|
| 452 |
|
|
#define HAL_MCF5272_CSBR_CTM (0x01 << 1)
|
| 453 |
|
|
#define HAL_MCF5272_CSBR_ENABLE (0x01 << 0)
|
| 454 |
|
|
|
| 455 |
|
|
#define HAL_MCF5272_CSOR_BA_MASK (0xFFFFF000)
|
| 456 |
|
|
#define HAL_MCF5272_CSOR_ASET (0x01 << 11)
|
| 457 |
|
|
#define HAL_MCF5272_CSOR_WRAH (0x01 << 10)
|
| 458 |
|
|
#define HAL_MCF5272_CSOR_RDAH (0x01 << 9)
|
| 459 |
|
|
#define HAL_MCF5272_CSOR_EXTBURST (0x01 << 8)
|
| 460 |
|
|
#define HAL_MCF5272_CSOR_WS_MASK (0x1F << 2)
|
| 461 |
|
|
#define HAL_MCF5272_CSOR_WS_SHIFT 2
|
| 462 |
|
|
#define HAL_MCF5272_CSOR_RW (0x01 << 1)
|
| 463 |
|
|
#define HAL_MCF5272_CSOR_MRW (0x01 << 0)
|
| 464 |
|
|
|
| 465 |
|
|
// ----------------------------------------------------------------------------
|
| 466 |
|
|
// SDRAM controller. Two 16-bit registers.
|
| 467 |
|
|
|
| 468 |
|
|
#define HAL_MCF5272_SDCR 0x0180
|
| 469 |
|
|
#define HAL_MCF5272_SDTR 0x0184
|
| 470 |
|
|
|
| 471 |
|
|
#define HAL_MCF5272_SDCR_MCAS_MASK (0x03 << 13)
|
| 472 |
|
|
#define HAL_MCF5272_SDCR_MCAS_A7 (0x00 << 13)
|
| 473 |
|
|
#define HAL_MCF5272_SDCR_MCAS_A8 (0x01 << 13)
|
| 474 |
|
|
#define HAL_MCF5272_SDCR_MCAS_A9 (0x02 << 13)
|
| 475 |
|
|
#define HAL_MCF5272_SDCR_MCAS_A10 (0x03 << 13)
|
| 476 |
|
|
#define HAL_MCF5272_SDCR_BALOC_MASK (0x07 << 8)
|
| 477 |
|
|
#define HAL_MCF5272_SDCR_BALOC_A21_A20 (0x01 << 8)
|
| 478 |
|
|
#define HAL_MCF5272_SDCR_BALOC_A22_A21 (0x02 << 8)
|
| 479 |
|
|
#define HAL_MCF5272_SDCR_BALOC_A23_A22 (0x03 << 8)
|
| 480 |
|
|
#define HAL_MCF5272_SDCR_BALOC_A24_A23 (0x04 << 8)
|
| 481 |
|
|
#define HAL_MCF5272_SDCR_BALOC_A25_A24 (0x05 << 8)
|
| 482 |
|
|
#define HAL_MCF5272_SDCR_GSL (0x01 << 7)
|
| 483 |
|
|
#define HAL_MCF5272_SDCR_REG (0x01 << 4)
|
| 484 |
|
|
#define HAL_MCF5272_SDCR_INV (0x01 << 3)
|
| 485 |
|
|
#define HAL_MCF5272_SDCR_SLEEP (0x01 << 2)
|
| 486 |
|
|
#define HAL_MCF5272_SDCR_ACT (0x01 << 1)
|
| 487 |
|
|
#define HAL_MCF5272_SDCR_INIT (0x01 << 0)
|
| 488 |
|
|
|
| 489 |
|
|
#define HAL_MCF5272_SDTR_RTP_MASK (0x3F << 10)
|
| 490 |
|
|
#define HAL_MCF5272_SDTR_RTP_66 (0x3D << 10)
|
| 491 |
|
|
#define HAL_MCF5272_SDTR_RTP_48 (0x2B << 10)
|
| 492 |
|
|
#define HAL_MCF5272_SDTR_RTP_33 (0x1D << 10)
|
| 493 |
|
|
#define HAL_MCF5272_SDTR_RTP_25 (0x15 << 10)
|
| 494 |
|
|
#define HAL_MCF5272_SDTR_RTP_5 (0x04 << 10)
|
| 495 |
|
|
#define HAL_MCF5272_SDTR_RC_MASK (0x03 << 8)
|
| 496 |
|
|
#define HAL_MCF5272_SDTR_RC_5 (0x00 << 8)
|
| 497 |
|
|
#define HAL_MCF5272_SDTR_RC_6 (0x01 << 8)
|
| 498 |
|
|
#define HAL_MCF5272_SDTR_RC_7 (0x02 << 8)
|
| 499 |
|
|
#define HAL_MCF5272_SDTR_RC_8 (0x03 << 8)
|
| 500 |
|
|
#define HAL_MCF5272_SDTR_RP_MASK (0x03 << 4)
|
| 501 |
|
|
#define HAL_MCF5272_SDTR_RP_1 (0x00 << 4)
|
| 502 |
|
|
#define HAL_MCF5272_SDTR_RP_2 (0x01 << 4)
|
| 503 |
|
|
#define HAL_MCF5272_SDTR_RP_3 (0x02 << 4)
|
| 504 |
|
|
#define HAL_MCF5272_SDTR_RP_4 (0x03 << 4)
|
| 505 |
|
|
#define HAL_MCF5272_SDTR_RCD_MASK (0x03 << 2)
|
| 506 |
|
|
#define HAL_MCF5272_SDTR_RCD_1 (0x00 << 2)
|
| 507 |
|
|
#define HAL_MCF5272_SDTR_RCD_2 (0x01 << 2)
|
| 508 |
|
|
#define HAL_MCF5272_SDTR_RCD_3 (0x02 << 2)
|
| 509 |
|
|
#define HAL_MCF5272_SDTR_RCD_4 (0x03 << 2)
|
| 510 |
|
|
#define HAL_MCF5272_SDTR_CLT_MASK (0x03 << 0)
|
| 511 |
|
|
#define HAL_MCF5272_SDTR_CLT_2 (0x01 << 0)
|
| 512 |
|
|
|
| 513 |
|
|
// ----------------------------------------------------------------------------
|
| 514 |
|
|
// DMA controller. DCIR is 16-bit, the rest 32-bit
|
| 515 |
|
|
#define HAL_MCF5272_DMA_DCMR 0x00E0
|
| 516 |
|
|
#define HAL_MCF5272_DMA_DCIR 0x00E6
|
| 517 |
|
|
#define HAL_MCF5272_DMA_DBCR 0x00E8
|
| 518 |
|
|
#define HAL_MCF5272_DMA_DSAR 0x00EC
|
| 519 |
|
|
#define HAL_MCF5272_DMA_DDAR 0x00F0
|
| 520 |
|
|
|
| 521 |
|
|
#define HAL_MCF5272_DMA_DCMR_RESET (0x01 << 31)
|
| 522 |
|
|
#define HAL_MCF5272_DMA_DCMR_EN (0x01 << 30)
|
| 523 |
|
|
#define HAL_MCF5272_DMA_DCMR_RQM_MASK (0x03 << 18)
|
| 524 |
|
|
#define HAL_MCF5272_DMA_DCMR_RQM_DUAL (0x03 << 18)
|
| 525 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTM_MASK (0x03 << 13)
|
| 526 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTM_STATIC (0x00 << 13)
|
| 527 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTM_INCREMENT (0x01 << 13)
|
| 528 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTT_MASK (0x07 << 10)
|
| 529 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTT_UDA (0x01 << 10)
|
| 530 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTT_UCA (0x02 << 10)
|
| 531 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTT_SDA (0x05 << 10)
|
| 532 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTT_SCA (0x06 << 10)
|
| 533 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTS_MASK (0x03 << 8)
|
| 534 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTS_4 (0x00 << 8)
|
| 535 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTS_1 (0x01 << 8)
|
| 536 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTS_2 (0x02 << 8)
|
| 537 |
|
|
#define HAL_MCF5272_DMA_DCMR_DSTS_16 (0x03 << 8)
|
| 538 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCM_MASK (0x01 << 5)
|
| 539 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCM_STATIC (0x00 << 5)
|
| 540 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCM_INCREMENT (0x01 << 5)
|
| 541 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCT_MASK (0x07 << 2)
|
| 542 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCT_UDA (0x01 << 2)
|
| 543 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCT_UCA (0x02 << 2)
|
| 544 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCT_SDA (0x05 << 2)
|
| 545 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCT_SCA (0x06 << 2)
|
| 546 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCS_MASK (0x03 << 0)
|
| 547 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCS_4 (0x00 << 0)
|
| 548 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCS_1 (0x01 << 0)
|
| 549 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCS_2 (0x02 << 0)
|
| 550 |
|
|
#define HAL_MCF5272_DMA_DCMR_SRCS_16 (0x03 << 0)
|
| 551 |
|
|
|
| 552 |
|
|
#define HAL_MCF5272_DMA_DIR_INVEN (0x01 << 12)
|
| 553 |
|
|
#define HAL_MCF5272_DMA_DIR_ASCEN (0x01 << 11)
|
| 554 |
|
|
#define HAL_MCF5272_DMA_DIR_TEEN (0x01 << 9)
|
| 555 |
|
|
#define HAL_MCF5272_DMA_DIR_TCEN (0x01 << 8)
|
| 556 |
|
|
#define HAL_MCF5272_DMA_DIR_INV (0x01 << 4)
|
| 557 |
|
|
#define HAL_MCF5272_DMA_DIR_ASC (0x01 << 3)
|
| 558 |
|
|
#define HAL_MCF5272_DMA_DIR_TE (0x01 << 1)
|
| 559 |
|
|
#define HAL_MCF5272_DMA_DIR_TC (0x01 << 0)
|
| 560 |
|
|
|
| 561 |
|
|
// ----------------------------------------------------------------------------
|
| 562 |
|
|
// USB
|
| 563 |
|
|
#define HAL_MCF5272_USB_FNR 0x1002
|
| 564 |
|
|
#define HAL_MCF5272_USB_FNMR 0x1006
|
| 565 |
|
|
#define HAL_MCF5272_USB_RFMR 0x100A
|
| 566 |
|
|
#define HAL_MCF5272_USB_RFMMR 0x100E
|
| 567 |
|
|
#define HAL_MCF5272_USB_FAR 0x1013
|
| 568 |
|
|
#define HAL_MCF5272_USB_ASR 0x1014
|
| 569 |
|
|
#define HAL_MCF5272_USB_DDR1 0x1018
|
| 570 |
|
|
#define HAL_MCF5272_USB_DDR2 0x101C
|
| 571 |
|
|
#define HAL_MCF5272_USB_SPECR 0x1022
|
| 572 |
|
|
#define HAL_MCF5272_USB_EP0SR 0x1026
|
| 573 |
|
|
#define HAL_MCF5272_USB_IEP0CFG 0x1028
|
| 574 |
|
|
#define HAL_MCF5272_USB_OEP0CFG 0x102C
|
| 575 |
|
|
#define HAL_MCF5272_USB_EP1CFG 0x1030
|
| 576 |
|
|
#define HAL_MCF5272_USB_EP2CFG 0x1034
|
| 577 |
|
|
#define HAL_MCF5272_USB_EP3CFG 0x1038
|
| 578 |
|
|
#define HAL_MCF5272_USB_EP4CFG 0x103C
|
| 579 |
|
|
#define HAL_MCF5272_USB_EP5CFG 0x1040
|
| 580 |
|
|
#define HAL_MCF5272_USB_EP6CFG 0x1044
|
| 581 |
|
|
#define HAL_MCF5272_USB_EP7CFG 0x1048
|
| 582 |
|
|
#define HAL_MCF5272_USB_EP0CTL 0x104C
|
| 583 |
|
|
#define HAL_MCF5272_USB_EP1CTL 0x1052
|
| 584 |
|
|
#define HAL_MCF5272_USB_EP2CTL 0x1056
|
| 585 |
|
|
#define HAL_MCF5272_USB_EP3CTL 0x105A
|
| 586 |
|
|
#define HAL_MCF5272_USB_EP4CTL 0x105E
|
| 587 |
|
|
#define HAL_MCF5272_USB_EP5CTL 0x1062
|
| 588 |
|
|
#define HAL_MCF5272_USB_EP6CTL 0x1066
|
| 589 |
|
|
#define HAL_MCF5272_USB_EP7CTL 0x106A
|
| 590 |
|
|
#define HAL_MCF5272_USB_EP0ISR 0x106C
|
| 591 |
|
|
#define HAL_MCF5272_USB_EP1ISR 0x1072
|
| 592 |
|
|
#define HAL_MCF5272_USB_EP2ISR 0x1076
|
| 593 |
|
|
#define HAL_MCF5272_USB_EP3ISR 0x107A
|
| 594 |
|
|
#define HAL_MCF5272_USB_EP4ISR 0x107E
|
| 595 |
|
|
#define HAL_MCF5272_USB_EP5ISR 0x1082
|
| 596 |
|
|
#define HAL_MCF5272_USB_EP6ISR 0x1086
|
| 597 |
|
|
#define HAL_MCF5272_USB_EP7ISR 0x108A
|
| 598 |
|
|
#define HAL_MCF5272_USB_EP0IMR 0x108C
|
| 599 |
|
|
#define HAL_MCF5272_USB_EP1IMR 0x1092
|
| 600 |
|
|
#define HAL_MCF5272_USB_EP2IMR 0x1096
|
| 601 |
|
|
#define HAL_MCF5272_USB_EP3IMR 0x109A
|
| 602 |
|
|
#define HAL_MCF5272_USB_EP4IMR 0x109E
|
| 603 |
|
|
#define HAL_MCF5272_USB_EP5IMR 0x10A2
|
| 604 |
|
|
#define HAL_MCF5272_USB_EP6IMR 0x10A6
|
| 605 |
|
|
#define HAL_MCF5272_USB_EP7IMR 0x10AA
|
| 606 |
|
|
#define HAL_MCF5272_USB_EP0DR 0x10AC
|
| 607 |
|
|
#define HAL_MCF5272_USB_EP1DR 0x10B0
|
| 608 |
|
|
#define HAL_MCF5272_USB_EP2DR 0x10B4
|
| 609 |
|
|
#define HAL_MCF5272_USB_EP3DR 0x10B8
|
| 610 |
|
|
#define HAL_MCF5272_USB_EP4DR 0x10BC
|
| 611 |
|
|
#define HAL_MCF5272_USB_EP5DR 0x10C0
|
| 612 |
|
|
#define HAL_MCF5272_USB_EP6DR 0x10C4
|
| 613 |
|
|
#define HAL_MCF5272_USB_EP7DR 0x10C8
|
| 614 |
|
|
#define HAL_MCF5272_USB_EP0DPR 0x10CE
|
| 615 |
|
|
#define HAL_MCF5272_USB_EP1DPR 0x10D2
|
| 616 |
|
|
#define HAL_MCF5272_USB_EP2DPR 0x10D6
|
| 617 |
|
|
#define HAL_MCF5272_USB_EP3DPR 0x10DA
|
| 618 |
|
|
#define HAL_MCF5272_USB_EP4DPR 0x10DE
|
| 619 |
|
|
#define HAL_MCF5272_USB_EP5DPR 0x10E2
|
| 620 |
|
|
#define HAL_MCF5272_USB_EP6DPR 0x10E6
|
| 621 |
|
|
#define HAL_MCF5272_USB_EP7DPR 0x10EA
|
| 622 |
|
|
#define HAL_MCF5272_USB_CONFIG 0x1400
|
| 623 |
|
|
|
| 624 |
|
|
#define HAL_MCF5272_USB_ASR_IF15_MASK (0x03 << 30)
|
| 625 |
|
|
#define HAL_MCF5272_USB_ASR_IF15_SHIFT 30
|
| 626 |
|
|
#define HAL_MCF5272_USB_ASR_IF14_MASK (0x03 << 28)
|
| 627 |
|
|
#define HAL_MCF5272_USB_ASR_IF14_SHIFT 28
|
| 628 |
|
|
#define HAL_MCF5272_USB_ASR_IF13_MASK (0x03 << 26)
|
| 629 |
|
|
#define HAL_MCF5272_USB_ASR_IF13_SHIFT 26
|
| 630 |
|
|
#define HAL_MCF5272_USB_ASR_IF12_MASK (0x03 << 24)
|
| 631 |
|
|
#define HAL_MCF5272_USB_ASR_IF12_SHIFT 24
|
| 632 |
|
|
#define HAL_MCF5272_USB_ASR_IF11_MASK (0x03 << 22)
|
| 633 |
|
|
#define HAL_MCF5272_USB_ASR_IF11_SHIFT 22
|
| 634 |
|
|
#define HAL_MCF5272_USB_ASR_IF10_MASK (0x03 << 20)
|
| 635 |
|
|
#define HAL_MCF5272_USB_ASR_IF10_SHIFT 20
|
| 636 |
|
|
#define HAL_MCF5272_USB_ASR_IF9_MASK (0x03 << 18)
|
| 637 |
|
|
#define HAL_MCF5272_USB_ASR_IF9_SHIFT 18
|
| 638 |
|
|
#define HAL_MCF5272_USB_ASR_IF8_MASK (0x03 << 16)
|
| 639 |
|
|
#define HAL_MCF5272_USB_ASR_IF8_SHIFT 16
|
| 640 |
|
|
#define HAL_MCF5272_USB_ASR_IF7_MASK (0x03 << 14)
|
| 641 |
|
|
#define HAL_MCF5272_USB_ASR_IF7_SHIFT 14
|
| 642 |
|
|
#define HAL_MCF5272_USB_ASR_IF6_MASK (0x03 << 12)
|
| 643 |
|
|
#define HAL_MCF5272_USB_ASR_IF6_SHIFT 12
|
| 644 |
|
|
#define HAL_MCF5272_USB_ASR_IF5_MASK (0x03 << 10)
|
| 645 |
|
|
#define HAL_MCF5272_USB_ASR_IF5_SHIFT 10
|
| 646 |
|
|
#define HAL_MCF5272_USB_ASR_IF4_MASK (0x03 << 8)
|
| 647 |
|
|
#define HAL_MCF5272_USB_ASR_IF4_SHIFT 8
|
| 648 |
|
|
#define HAL_MCF5272_USB_ASR_IF3_MASK (0x03 << 6)
|
| 649 |
|
|
#define HAL_MCF5272_USB_ASR_IF3_SHIFT 6
|
| 650 |
|
|
#define HAL_MCF5272_USB_ASR_IF2_MASK (0x03 << 4)
|
| 651 |
|
|
#define HAL_MCF5272_USB_ASR_IF2_SHIFT 4
|
| 652 |
|
|
#define HAL_MCF5272_USB_ASR_IF1_MASK (0x03 << 2)
|
| 653 |
|
|
#define HAL_MCF5272_USB_ASR_IF1_SHIFT 2
|
| 654 |
|
|
#define HAL_MCF5272_USB_ASR_IF0_MASK (0x03 << 0)
|
| 655 |
|
|
#define HAL_MCF5272_USB_ASR_IF0_SHIFT 0
|
| 656 |
|
|
|
| 657 |
|
|
#define HAL_MCF5272_USB_DDR1_wValue_MASK (0x0FFFF << 16)
|
| 658 |
|
|
#define HAL_MCF5272_USB_DDR1_wValue_SHIFT 16
|
| 659 |
|
|
#define HAL_MCF5272_USB_DDR1_bRequest_MASK (0x0FF << 8)
|
| 660 |
|
|
#define HAL_MCF5272_USB_DDR1_bRequest_SHIFT 8
|
| 661 |
|
|
#define HAL_MCF5272_USB_DDR1_bmRequestType_MASK (0x0FF << 0)
|
| 662 |
|
|
#define HAL_MCF5272_USB_DDR1_bmRequestType_SHIFT 0
|
| 663 |
|
|
#define HAL_MCF5272_USB_DDR2_wLength_MASK (0x0FFFF << 16)
|
| 664 |
|
|
#define HAL_MCF5272_USB_DDR2_wLength_SHIFT 16
|
| 665 |
|
|
#define HAL_MCF5272_USB_DDR2_wIndex_MASK (0x0FFFF << 0)
|
| 666 |
|
|
#define HAL_MCF5272_USB_DDR2_wIndex_SHIFT 0
|
| 667 |
|
|
|
| 668 |
|
|
#define HAL_MCF5272_USB_SPECR_SPEC_MASK (0x0FFF0 << 4)
|
| 669 |
|
|
#define HAL_MCF5272_USB_SPECR_SPEC_SHIFT 4
|
| 670 |
|
|
#define HAL_MCF5272_USB_SPECR_MRN_MASK (0x0F << 0)
|
| 671 |
|
|
#define HAL_MCF5272_USB_SPECR_MRN_SHIFT (0x0F << 0)
|
| 672 |
|
|
|
| 673 |
|
|
#define HAL_MCF5272_USB_EP0SR_CONFIG_MASK (0x0F << 12)
|
| 674 |
|
|
#define HAL_MCF5272_USB_EP0SR_CONFIG_SHIFT 12
|
| 675 |
|
|
#define HAL_MCF5272_USB_EP0SR_WAKE_ST (0x01 << 11)
|
| 676 |
|
|
#define HAL_MCF5272_USB_EP0SR_HALT_ST (0x01 << 2)
|
| 677 |
|
|
#define HAL_MCF5272_USB_EP0SR_DIR_MASK (0x01 << 1)
|
| 678 |
|
|
#define HAL_MCF5272_USB_EP0SR_DIR_IN (0x01 << 1)
|
| 679 |
|
|
#define HAL_MCF5272_USB_EP0SR_DIR_OUT (0x00 << 1)
|
| 680 |
|
|
|
| 681 |
|
|
#define HAL_MCF5272_USB_IEP0CFG_MAX_PACKET_MASK (0x03FF << 22)
|
| 682 |
|
|
#define HAL_MCF5272_USB_IEP0CFG_MAX_PACKET_SHIFT 22
|
| 683 |
|
|
#define HAL_MCF5272_USB_IEP0CFG_FIFO_SIZE_MASK (0x03FF << 11)
|
| 684 |
|
|
#define HAL_MCF5272_USB_IEP0CFG_FIFO_SIZE_SHIFT 11
|
| 685 |
|
|
#define HAL_MCF5272_USB_IEP0CFG_FIFO_ADDR_MASK (0x03FF << 0)
|
| 686 |
|
|
#define HAL_MCF5272_USB_IEP0CFG_FIFO_ADDR_SHIFT 0
|
| 687 |
|
|
|
| 688 |
|
|
#define HAL_MCF5272_USB_OEP0CFG_MAX_PACKET_MASK (0x03FF << 22)
|
| 689 |
|
|
#define HAL_MCF5272_USB_OEP0CFG_MAX_PACKET_SHIFT 22
|
| 690 |
|
|
#define HAL_MCF5272_USB_OEP0CFG_FIFO_SIZE_MASK (0x03FF << 11)
|
| 691 |
|
|
#define HAL_MCF5272_USB_OEP0CFG_FIFO_SIZE_SHIFT 11
|
| 692 |
|
|
#define HAL_MCF5272_USB_OEP0CFG_FIFO_ADDR_MASK (0x03FF << 0)
|
| 693 |
|
|
#define HAL_MCF5272_USB_OEP0CFG_FIFO_ADDR_SHIFT 0
|
| 694 |
|
|
|
| 695 |
|
|
#define HAL_MCF5272_USB_EPnCFG_MAX_PACKET_MASK (0x03FF << 22)
|
| 696 |
|
|
#define HAL_MCF5272_USB_EPnCFG_MAX_PACKET_SHIFT 22
|
| 697 |
|
|
#define HAL_MCF5272_USB_EPnCFG_FIFO_SIZE_MASK (0x03FF << 11)
|
| 698 |
|
|
#define HAL_MCF5272_USB_EPnCFG_FIFO_SIZE_SHIFT 11
|
| 699 |
|
|
#define HAL_MCF5272_USB_EPnCFG_FIFO_ADDR_MASK (0x03FF << 0)
|
| 700 |
|
|
#define HAL_MCF5272_USB_EPnCFG_FIFO_ADDR_SHIFT 0
|
| 701 |
|
|
|
| 702 |
|
|
#define HAL_MCF5272_USB_EP0CTL_DEBUG (0x01 << 18)
|
| 703 |
|
|
#define HAL_MCF5272_USB_EP0CTL_WOR_LVL (0x01 << 17)
|
| 704 |
|
|
#define HAL_MCF5272_USB_EP0CTL_WOR_EN (0x01 << 16)
|
| 705 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CLK_SEL (0x01 << 15)
|
| 706 |
|
|
#define HAL_MCF5272_USB_EP0CTL_RESUME (0x01 << 14)
|
| 707 |
|
|
#define HAL_MCF5272_USB_EP0CTL_AFE_EN (0x01 << 13)
|
| 708 |
|
|
#define HAL_MCF5272_USB_EP0CTL_BUS_PWR (0x01 << 12)
|
| 709 |
|
|
#define HAL_MCF5272_USB_EP0CTL_USB_EN (0x01 << 11)
|
| 710 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CFG_RAM_VAL (0x01 << 10)
|
| 711 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_ERR (0x01 << 9)
|
| 712 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_OVER (0x01 << 8)
|
| 713 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_CRC_ERR (0x01 << 7)
|
| 714 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_MASK (0x03 << 4)
|
| 715 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_25 (0x00 << 4)
|
| 716 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_50 (0x01 << 4)
|
| 717 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_75 (0x02 << 4)
|
| 718 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_OUT_LVL_100 (0x03 << 4)
|
| 719 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_MASK (0x03 << 2)
|
| 720 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_25 (0x00 << 2)
|
| 721 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_50 (0x01 << 2)
|
| 722 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_75 (0x02 << 2)
|
| 723 |
|
|
#define HAL_MCF5272_USB_EP0CTL_CMD_IN_LVL_100 (0x03 << 2)
|
| 724 |
|
|
#define HAL_MCF5272_USB_EP0CTL_IN_DONE (0x01 << 1)
|
| 725 |
|
|
|
| 726 |
|
|
#define HAL_MCF5272_USB_EPnCR_CRC_ERR (0x01 << 7)
|
| 727 |
|
|
#define HAL_MCF5272_USB_EPnCR_ISO_MODE (0x01 << 6)
|
| 728 |
|
|
#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_MASK (0x03 << 2)
|
| 729 |
|
|
#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_25 (0x00 << 2)
|
| 730 |
|
|
#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_50 (0x01 << 2)
|
| 731 |
|
|
#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_75 (0x02 << 2)
|
| 732 |
|
|
#define HAL_MCF5272_USB_EPnCR_FIFO_LVL_100 (0x03 << 2)
|
| 733 |
|
|
#define HAL_MCF5272_USB_EPnCR_IN_DONE (0x01 << 1)
|
| 734 |
|
|
#define HAL_MCF5272_USB_EPnCR_STALL (0x01 << 0)
|
| 735 |
|
|
|
| 736 |
|
|
#define HAL_MCF5272_USB_EP0IMR_DEV_CFG (0x01 << 16)
|
| 737 |
|
|
#define HAL_MCF5272_USB_EP0IMR_VEND_REQ (0x01 << 15)
|
| 738 |
|
|
#define HAL_MCF5272_USB_EP0IMR_FRM_MAT (0x01 << 14)
|
| 739 |
|
|
#define HAL_MCF5272_USB_EP0IMR_ASOF (0x01 << 13)
|
| 740 |
|
|
#define HAL_MCF5272_USB_EP0IMR_SOF (0x01 << 12)
|
| 741 |
|
|
#define HAL_MCF5272_USB_EP0IMR_WAKE_CHG (0x01 << 11)
|
| 742 |
|
|
#define HAL_MCF5272_USB_EP0IMR_RESUME (0x01 << 10)
|
| 743 |
|
|
#define HAL_MCF5272_USB_EP0IMR_SUSPEND (0x01 << 9)
|
| 744 |
|
|
#define HAL_MCF5272_USB_EP0IMR_RESET (0x01 << 8)
|
| 745 |
|
|
#define HAL_MCF5272_USB_EP0IMR_OUT_EOT (0x01 << 7)
|
| 746 |
|
|
#define HAL_MCF5272_USB_EP0IMR_OUT_EOP (0x01 << 6)
|
| 747 |
|
|
#define HAL_MCF5272_USB_EP0IMR_OUT_LVL (0x01 << 5)
|
| 748 |
|
|
#define HAL_MCF5272_USB_EP0IMR_IN_EOT (0x01 << 4)
|
| 749 |
|
|
#define HAL_MCF5272_USB_EP0IMR_IN_EOP (0x01 << 3)
|
| 750 |
|
|
#define HAL_MCF5272_USB_EP0IMR_UNHALT (0x01 << 2)
|
| 751 |
|
|
#define HAL_MCF5272_USB_EP0IMR_HALT (0x01 << 1)
|
| 752 |
|
|
#define HAL_MCF5272_USB_EP0IMR_IN_LVL (0x01 << 0)
|
| 753 |
|
|
|
| 754 |
|
|
#define HAL_MCF5272_USB_EP0ISR_DEV_CFG HAL_MCF5272_USB_EP0IMR_DEV_CFG
|
| 755 |
|
|
#define HAL_MCF5272_USB_EP0ISR_VEND_REQ HAL_MCF5272_USB_EP0IMR_VEND_REQ
|
| 756 |
|
|
#define HAL_MCF5272_USB_EP0ISR_FRM_MAT HAL_MCF5272_USB_EP0IMR_FRM_MAT
|
| 757 |
|
|
#define HAL_MCF5272_USB_EP0ISR_ASOF HAL_MCF5272_USB_EP0IMR_ASOF
|
| 758 |
|
|
#define HAL_MCF5272_USB_EP0ISR_SOF HAL_MCF5272_USB_EP0IMR_SOF
|
| 759 |
|
|
#define HAL_MCF5272_USB_EP0ISR_WAKE_CHG HAL_MCF5272_USB_EP0IMR_WAKE_CHG
|
| 760 |
|
|
#define HAL_MCF5272_USB_EP0ISR_RESUME HAL_MCF5272_USB_EP0IMR_RESUME
|
| 761 |
|
|
#define HAL_MCF5272_USB_EP0ISR_SUSPEND HAL_MCF5272_USB_EP0IMR_SUSPEND
|
| 762 |
|
|
#define HAL_MCF5272_USB_EP0ISR_RESET HAL_MCF5272_USB_EP0IMR_RESET
|
| 763 |
|
|
#define HAL_MCF5272_USB_EP0ISR_OUT_EOT HAL_MCF5272_USB_EP0IMR_OUT_EOT
|
| 764 |
|
|
#define HAL_MCF5272_USB_EP0ISR_OUT_EOP HAL_MCF5272_USB_EP0IMR_OUT_EOP
|
| 765 |
|
|
#define HAL_MCF5272_USB_EP0ISR_OUT_LVL HAL_MCF5272_USB_EP0IMR_OUT_LVL
|
| 766 |
|
|
#define HAL_MCF5272_USB_EP0ISR_IN_EOT HAL_MCF5272_USB_EP0IMR_IN_EOT
|
| 767 |
|
|
#define HAL_MCF5272_USB_EP0ISR_IN_EOP HAL_MCF5272_USB_EP0IMR_IN_EOP
|
| 768 |
|
|
#define HAL_MCF5272_USB_EP0ISR_UNHALT HAL_MCF5272_USB_EP0IMR_UNHALT
|
| 769 |
|
|
#define HAL_MCF5272_USB_EP0ISR_HALT HAL_MCF5272_USB_EP0IMR_HALT
|
| 770 |
|
|
#define HAL_MCF5272_USB_EP0ISR_IN_LVL HAL_MCF5272_USB_EP0IMR_IN_LVL
|
| 771 |
|
|
|
| 772 |
|
|
#define HAL_MCF5272_USB_EPnISR_HALT_ST (0x01 << 15)
|
| 773 |
|
|
#define HAL_MCF5272_USB_EPnISR_DIR (0x01 << 14)
|
| 774 |
|
|
#define HAL_MCF5272_USB_EPnISR_PRES (0x01 << 13)
|
| 775 |
|
|
#define HAL_MCF5272_USB_EPnISR_EOT (0x01 << 4)
|
| 776 |
|
|
#define HAL_MCF5272_USB_EPnISR_EOP (0x01 << 3)
|
| 777 |
|
|
#define HAL_MCF5272_USB_EPnISR_UNHALT (0x01 << 2)
|
| 778 |
|
|
#define HAL_MCF5272_USB_EPnISR_HALT (0x01 << 1)
|
| 779 |
|
|
#define HAL_MCF5272_USB_EPnISR_FIFO_LVL (0x01 << 0)
|
| 780 |
|
|
|
| 781 |
|
|
#define HAL_MCF5272_USB_EPnIMR_EOT HAL_MCF5272_USB_EPnISR_EOT
|
| 782 |
|
|
#define HAL_MCF5272_USB_EPnIMR_EOP HAL_MCF5272_USB_EPnISR_EOP
|
| 783 |
|
|
#define HAL_MCF5272_USB_EPnIMR_UNHALT HAL_MCF5272_USB_EPnISR_UNHALT
|
| 784 |
|
|
#define HAL_MCF5272_USB_EPnIMR_HALT HAL_MCF5272_USB_EPnISR_HALT
|
| 785 |
|
|
#define HAL_MCF5272_USB_EPnIMR_FIFO_LVL HAL_MCF5272_USB_EPnISR_FIFO_LVL
|
| 786 |
|
|
|
| 787 |
|
|
// ----------------------------------------------------------------------------
|
| 788 |
|
|
// PLIC
|
| 789 |
|
|
|
| 790 |
|
|
#define HAL_MCF5272_PLIC_P0B1RR 0x0300
|
| 791 |
|
|
#define HAL_MCF5272_PLIC_P1B1RR 0x0304
|
| 792 |
|
|
#define HAL_MCF5272_PLIC_P2B1RR 0x0308
|
| 793 |
|
|
#define HAL_MCF5272_PLIC_P3B1RR 0x030C
|
| 794 |
|
|
#define HAL_MCF5272_PLIC_P0B2RR 0x0310
|
| 795 |
|
|
#define HAL_MCF5272_PLIC_P1B2RR 0x0314
|
| 796 |
|
|
#define HAL_MCF5272_PLIC_P2B2RR 0x0318
|
| 797 |
|
|
#define HAL_MCF5272_PLIC_P3B2RR 0x031C
|
| 798 |
|
|
#define HAL_MCF5272_PLIC_P0DDR 0x0320
|
| 799 |
|
|
#define HAL_MCF5272_PLIC_P1DDR 0x0321
|
| 800 |
|
|
#define HAL_MCF5272_PLIC_P2DDR 0x0322
|
| 801 |
|
|
#define HAL_MCF5272_PLIC_P3DDR 0x0323
|
| 802 |
|
|
#define HAL_MCF5272_PLIC_P0B1TR 0x0328
|
| 803 |
|
|
#define HAL_MCF5272_PLIC_P1B1TR 0x032C
|
| 804 |
|
|
#define HAL_MCF5272_PLIC_P2B1TR 0x0330
|
| 805 |
|
|
#define HAL_MCF5272_PLIC_P3B1TR 0x0334
|
| 806 |
|
|
#define HAL_MCF5272_PLIC_P0B2TR 0x0338
|
| 807 |
|
|
#define HAL_MCF5272_PLIC_P1B2TR 0x033C
|
| 808 |
|
|
#define HAL_MCF5272_PLIC_P2B2TR 0x0340
|
| 809 |
|
|
#define HAL_MCF5272_PLIC_P3B2TR 0x0344
|
| 810 |
|
|
#define HAL_MCF5272_PLIC_P0DTR 0x0348
|
| 811 |
|
|
#define HAL_MCF5272_PLIC_P1DTR 0x0349
|
| 812 |
|
|
#define HAL_MCF5272_PLIC_P2DTR 0x034A
|
| 813 |
|
|
#define HAL_MCF5272_PLIC_P3DTR 0x034B
|
| 814 |
|
|
#define HAL_MCF5272_PLIC_P0CR 0x0350
|
| 815 |
|
|
#define HAL_MCF5272_PLIC_P1CR 0x0352
|
| 816 |
|
|
#define HAL_MCF5272_PLIC_P2CR 0x0354
|
| 817 |
|
|
#define HAL_MCF5272_PLIC_P3CR 0x0356
|
| 818 |
|
|
#define HAL_MCF5272_PLIC_P0ICR 0x0358
|
| 819 |
|
|
#define HAL_MCF5272_PLIC_P1ICR 0x035A
|
| 820 |
|
|
#define HAL_MCF5272_PLIC_P2ICR 0x035C
|
| 821 |
|
|
#define HAL_MCF5272_PLIC_P3ICR 0x035E
|
| 822 |
|
|
#define HAL_MCF5272_PLIC_P0GMR 0x0360
|
| 823 |
|
|
#define HAL_MCF5272_PLIC_P1GMR 0x0362
|
| 824 |
|
|
#define HAL_MCF5272_PLIC_P2GMR 0x0364
|
| 825 |
|
|
#define HAL_MCF5272_PLIC_P3GMR 0x0366
|
| 826 |
|
|
#define HAL_MCF5272_PLIC_P0GMT 0x0368
|
| 827 |
|
|
#define HAL_MCF5272_PLIC_P1GMT 0x036A
|
| 828 |
|
|
#define HAL_MCF5272_PLIC_P2GMT 0x036C
|
| 829 |
|
|
#define HAL_MCF5272_PLIC_P3GMT 0x036E
|
| 830 |
|
|
#define HAL_MCF5272_PLIC_PGMTS 0x0371
|
| 831 |
|
|
#define HAL_MCF5272_PLIC_PGMTA 0x0372
|
| 832 |
|
|
#define HAL_MCF5272_PLIC_P0GCIR 0x0374
|
| 833 |
|
|
#define HAL_MCF5272_PLIC_P1GCIR 0x0375
|
| 834 |
|
|
#define HAL_MCF5272_PLIC_P2GCIR 0x0376
|
| 835 |
|
|
#define HAL_MCF5272_PLIC_P3GCIR 0x0377
|
| 836 |
|
|
#define HAL_MCF5272_PLIC_P0GCIT 0x0378
|
| 837 |
|
|
#define HAL_MCF5272_PLIC_P1GCIT 0x0379
|
| 838 |
|
|
#define HAL_MCF5272_PLIC_P2GCIT 0x037A
|
| 839 |
|
|
#define HAL_MCF5272_PLIC_P3GCIT 0x037B
|
| 840 |
|
|
#define HAL_MCF5272_PLIC_PGCITSR 0x037F
|
| 841 |
|
|
#define HAL_MCF5272_PLIC_PDCSR 0x0383
|
| 842 |
|
|
#define HAL_MCF5272_PLIC_P0PSR 0x0384
|
| 843 |
|
|
#define HAL_MCF5272_PLIC_P1PSR 0x0386
|
| 844 |
|
|
#define HAL_MCF5272_PLIC_P2PSR 0x0388
|
| 845 |
|
|
#define HAL_MCF5272_PLIC_P3PSR 0x038A
|
| 846 |
|
|
#define HAL_MCF5272_PLIC_PASR 0x038C
|
| 847 |
|
|
#define HAL_MCF5272_PLIC_PLCR 0x038F
|
| 848 |
|
|
#define HAL_MCF5272_PLIC_PDRQR 0x0392
|
| 849 |
|
|
#define HAL_MCF5272_PLIC_P0SDR 0x0394
|
| 850 |
|
|
#define HAL_MCF5272_PLIC_P1SDR 0x0396
|
| 851 |
|
|
#define HAL_MCF5272_PLIC_P2SDR 0x0398
|
| 852 |
|
|
#define HAL_MCF5272_PLIC_P3SDR 0x039A
|
| 853 |
|
|
#define HAL_MCF5272_PLIC_PCSR 0x039E
|
| 854 |
|
|
|
| 855 |
|
|
#define HAL_MCF5272_PLIC_PnCR_ON_OFF (0x01 << 15)
|
| 856 |
|
|
#define HAL_MCF5272_PLIC_PnCR_M_MASK (0x07 << 12)
|
| 857 |
|
|
#define HAL_MCF5272_PLIC_PnCR_M_SHIFT 12
|
| 858 |
|
|
#define HAL_MCF5272_PLIC_PnCR_IDL8 (0x00 << 12)
|
| 859 |
|
|
#define HAL_MCF5272_PLIC_PnCR_IDL10 (0x01 << 12)
|
| 860 |
|
|
#define HAL_MCF5272_PLIC_PnCR_GCI (0x02 << 12)
|
| 861 |
|
|
#define HAL_MCF5272_PLIC_PnCR_M_S (0x01 << 11)
|
| 862 |
|
|
#define HAL_MCF5272_PLIC_PnCR_G_S (0x01 << 10)
|
| 863 |
|
|
#define HAL_MCF5272_PLIC_PnCR_FSM (0x01 << 9)
|
| 864 |
|
|
#define HAL_MCF5272_PLIC_PnCR_ACT (0x01 << 8)
|
| 865 |
|
|
#define HAL_MCF5272_PLIC_PnCR_DMX (0x01 << 7)
|
| 866 |
|
|
#define HAL_MCF5272_PLIC_PnCR_SHB2 (0x01 << 3)
|
| 867 |
|
|
#define HAL_MCF5272_PLIC_PnCR_SHB1 (0x01 << 2)
|
| 868 |
|
|
#define HAL_MCF5272_PLIC_PnCR_ENB2 (0x01 << 1)
|
| 869 |
|
|
#define HAL_MCF5272_PLIC_PnCR_ENB1 (0x01 << 0)
|
| 870 |
|
|
|
| 871 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM3_MASK (0x03 << 6)
|
| 872 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM3_SHIFT 6
|
| 873 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM2_MASK (0x03 << 4)
|
| 874 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM2_SHIFT 4
|
| 875 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM1_MASK (0x03 << 2)
|
| 876 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM1_SHIFT 2
|
| 877 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM0_MASK (0x03 << 0)
|
| 878 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM0_SHIFT 0
|
| 879 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LMn_NORMAL (0x00)
|
| 880 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LMn_AUTO_ECHO (0x01)
|
| 881 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LMn_LOCAL_LOOPBACK (0x02)
|
| 882 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LMn_REMOTE_LOOPBACK (0x03)
|
| 883 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM3_NORMAL (0x00 << 6)
|
| 884 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM3_AUTO_ECHO (0x01 << 6)
|
| 885 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM3_LOCAL_LOOPBACK (0x02 << 6)
|
| 886 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM3_REMOTE_LOOPBACK (0x03 << 6)
|
| 887 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM2_NORMAL (0x00 << 4)
|
| 888 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM2_AUTO_ECHO (0x01 << 4)
|
| 889 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM2_LOCAL_LOOPBACK (0x02 << 4)
|
| 890 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM2_REMOTE_LOOPBACK (0x03 << 4)
|
| 891 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM1_NORMAL (0x00 << 2)
|
| 892 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM1_AUTO_ECHO (0x01 << 2)
|
| 893 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM1_LOCAL_LOOPBACK (0x02 << 2)
|
| 894 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM1_REMOTE_LOOPBACK (0x03 << 2)
|
| 895 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM0_NORMAL (0x00 << 0)
|
| 896 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM0_AUTO_ECHO (0x01 << 0)
|
| 897 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM0_LOCAL_LOOPBACK (0x02 << 0)
|
| 898 |
|
|
#define HAL_MCF5272_PLIC_PLCR_LM0_REMOTE_LOOPBACK (0x03 << 0)
|
| 899 |
|
|
|
| 900 |
|
|
#define HAL_MCF5272_PLIC_PnICR_IE (0x01 << 15)
|
| 901 |
|
|
#define HAL_MCF5272_PLIC_PnICR_GCR (0x01 << 11)
|
| 902 |
|
|
#define HAL_MCF5272_PLIC_PnICR_GCT (0x01 << 10)
|
| 903 |
|
|
#define HAL_MCF5272_PLIC_PnICR_GMR (0x01 << 9)
|
| 904 |
|
|
#define HAL_MCF5272_PLIC_PnICR_GMT (0x01 << 8)
|
| 905 |
|
|
#define HAL_MCF5272_PLIC_PnICR_DTIE (0x01 << 5)
|
| 906 |
|
|
#define HAL_MCF5272_PLIC_PnICR_B2TIE (0x01 << 4)
|
| 907 |
|
|
#define HAL_MCF5272_PLIC_PnICR_B1TIE (0x01 << 3)
|
| 908 |
|
|
#define HAL_MCF5272_PLIC_PnICR_DRIE (0x01 << 2)
|
| 909 |
|
|
#define HAL_MCF5272_PLIC_PnICR_B2RIE (0x01 << 1)
|
| 910 |
|
|
#define HAL_MCF5272_PLIC_PnICR_B1RIE (0x01 << 0)
|
| 911 |
|
|
|
| 912 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_DTUE (0x01 << 11)
|
| 913 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B2TUE (0x01 << 10)
|
| 914 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B1TUE (0x01 << 9)
|
| 915 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_DROE (0x01 << 8)
|
| 916 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B2ROE (0x01 << 7)
|
| 917 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B1ROE (0x01 << 6)
|
| 918 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_DTDE (0x01 << 5)
|
| 919 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B2TDE (0x01 << 4)
|
| 920 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B1TDE (0x01 << 3)
|
| 921 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_DRDF (0x01 << 2)
|
| 922 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B2RDE (0x01 << 1)
|
| 923 |
|
|
#define HAL_MCF5272_PLIC_PnPSR_B1RDE (0x01 << 0)
|
| 924 |
|
|
|
| 925 |
|
|
#define HAL_MCF5272_PLIC_PASR_3_MASK (0x0F << 12)
|
| 926 |
|
|
#define HAL_MCF5272_PLIC_PASR_3_SHIFT 12
|
| 927 |
|
|
#define HAL_MCF5272_PLIC_PASR_2_MASK (0x0F << 8)
|
| 928 |
|
|
#define HAL_MCF5272_PLIC_PASR_2_SHIFT 8
|
| 929 |
|
|
#define HAL_MCF5272_PLIC_PASR_1_MASK (0x0F << 4)
|
| 930 |
|
|
#define HAL_MCF5272_PLIC_PASR_1_SHIFT 4
|
| 931 |
|
|
#define HAL_MCF5272_PLIC_PASR_0_MASK (0x0F << 0)
|
| 932 |
|
|
#define HAL_MCF5272_PLIC_PASR_0_SHIFT 0
|
| 933 |
|
|
#define HAL_MCF5272_PLCI_PASR_GCRn (0x01 << 3)
|
| 934 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCTn (0x01 << 2)
|
| 935 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMRn (0x01 << 1)
|
| 936 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMTn (0x01 << 0)
|
| 937 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCR3 (0x01 << 15)
|
| 938 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCT3 (0x01 << 14)
|
| 939 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMR3 (0x01 << 13)
|
| 940 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMT3 (0x01 << 12)
|
| 941 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCR2 (0x01 << 11)
|
| 942 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCT2 (0x01 << 10)
|
| 943 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMR2 (0x01 << 9)
|
| 944 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMT2 (0x01 << 8)
|
| 945 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCR1 (0x01 << 7)
|
| 946 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCT1 (0x01 << 6)
|
| 947 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMR1 (0x01 << 5)
|
| 948 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMT1 (0x01 << 4)
|
| 949 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCR0 (0x01 << 3)
|
| 950 |
|
|
#define HAL_MCF5272_PLIC_PASR_GCT0 (0x01 << 2)
|
| 951 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMR0 (0x01 << 1)
|
| 952 |
|
|
#define HAL_MCF5272_PLIC_PASR_GMT0 (0x01 << 0)
|
| 953 |
|
|
|
| 954 |
|
|
#define HAL_MCF5272_PLIC_PnGMR_EOM (0x01 << 10)
|
| 955 |
|
|
#define HAL_MCF5272_PLIC_PnGMR_AB (0x01 << 9)
|
| 956 |
|
|
#define HAL_MCF5272_PLIC_PnGMR_MC (0x01 << 8)
|
| 957 |
|
|
#define HAL_MCF5272_PLIC_PnGMR_M_MASK (0x0FF << 0)
|
| 958 |
|
|
#define HAL_MCF5272_PLIC_PnGMR_M_SHIFT 0
|
| 959 |
|
|
|
| 960 |
|
|
#define HAL_MCF5272_PLIC_PnGMT_L (0x01 << 9)
|
| 961 |
|
|
#define HAL_MCF5272_PLIC_PnGMT_R (0x01 << 8)
|
| 962 |
|
|
#define HAL_MCF5272_PLIC_PnGMT_M_MASK (0x0FF << 0)
|
| 963 |
|
|
#define HAL_MCF5272_PLIC_PnGMT_M_SHIFT 0
|
| 964 |
|
|
|
| 965 |
|
|
#define HAL_MCF5272_PLIC_PGMTA_AR3 (0x01 << 7)
|
| 966 |
|
|
#define HAL_MCF5272_PLIC_PGMTA_AR2 (0x01 << 6)
|
| 967 |
|
|
#define HAL_MCF5272_PLIC_PGMTA_AR1 (0x01 << 5)
|
| 968 |
|
|
#define HAL_MCF5272_PLIC_PGMTA_AR0 (0x01 << 4)
|
| 969 |
|
|
|
| 970 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_ACKn (0x01 << 4)
|
| 971 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_ABn (0x01 << 0)
|
| 972 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_3_SHIFT 3
|
| 973 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_2_SHIFT 2
|
| 974 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_1_SHIFT 1
|
| 975 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_0_SHIFT 0
|
| 976 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_ACK3 (0x01 << 7)
|
| 977 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_ACK2 (0x01 << 6)
|
| 978 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_ACK1 (0x01 << 5)
|
| 979 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_ACK0 (0x01 << 4)
|
| 980 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_AB3 (0x01 << 3)
|
| 981 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_AB2 (0x01 << 2)
|
| 982 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_AB1 (0x01 << 1)
|
| 983 |
|
|
#define HAL_MCF5272_PLIC_PGMTS_AB0 (0x01 << 0)
|
| 984 |
|
|
|
| 985 |
|
|
#define HAL_MCF5272_PLIC_PnGCIR_F (0x01 << 4)
|
| 986 |
|
|
#define HAL_MCF5272_PLIC_PnGCIR_C3 (0x01 << 3)
|
| 987 |
|
|
#define HAL_MCF5272_PLIC_PnGCIR_C2 (0x01 << 2)
|
| 988 |
|
|
#define HAL_MCF5272_PLIC_PnGCIR_C1 (0x01 << 1)
|
| 989 |
|
|
#define HAL_MCF5272_PLIC_PnGCIR_C0 (0x01 << 0)
|
| 990 |
|
|
|
| 991 |
|
|
#define HAL_MCF5272_PLIC_PnGCIT_R (0x01 << 4)
|
| 992 |
|
|
#define HAL_MCF5272_PLIC_PnGCIT_C3 (0x01 << 3)
|
| 993 |
|
|
#define HAL_MCF5272_PLIC_PnGCIT_C2 (0x01 << 2)
|
| 994 |
|
|
#define HAL_MCF5272_PLIC_PnGCIT_C1 (0x01 << 1)
|
| 995 |
|
|
#define HAL_MCF5272_PLIC_PnGCIT_C0 (0x01 << 0)
|
| 996 |
|
|
|
| 997 |
|
|
#define HAL_MCF5272_PLIC_PGCITSR_ACK3 (0x01 << 3)
|
| 998 |
|
|
#define HAL_MCF5272_PLIC_PGCITSR_ACK2 (0x01 << 2)
|
| 999 |
|
|
#define HAL_MCF5272_PLIC_PGCITSR_ACK1 (0x01 << 1)
|
| 1000 |
|
|
#define HAL_MCF5272_PLIC_PGCITSR_ACK0 (0x01 << 0)
|
| 1001 |
|
|
|
| 1002 |
|
|
#define HAL_MCF5272_PLIC_PDCSR_DG1 (0x01 << 5)
|
| 1003 |
|
|
#define HAL_MCF5272_PLIC_PDCSR_DG0 (0x01 << 4)
|
| 1004 |
|
|
#define HAL_MCF5272_PLIC_PDCSR_DC3 (0x01 << 3)
|
| 1005 |
|
|
#define HAL_MCF5272_PLIC_PDCSR_DC2 (0x01 << 2)
|
| 1006 |
|
|
#define HAL_MCF5272_PLIC_PDCSR_DC1 (0x01 << 1)
|
| 1007 |
|
|
#define HAL_MCF5272_PLIC_PDCSR_DC0 (0x01 << 0)
|
| 1008 |
|
|
|
| 1009 |
|
|
#define HAL_MCF5272_PLIC_PDRQR_SHDD1 (0x01 << 11)
|
| 1010 |
|
|
#define HAL_MCF5272_PLIC_PDRQR_DCNT1 (0x01 << 10)
|
| 1011 |
|
|
#define HAL_MCF5272_PLIC_PDRQR_SHDD0 (0x01 << 9)
|
| 1012 |
|
|
#define HAL_MCF5272_PLIC_PDRQR_DCNT0 (0x01 << 8)
|
| 1013 |
|
|
#define HAL_MCF5272_PLIC_PDRQR_DRQ_MASK (0x03 << 0)
|
| 1014 |
|
|
#define HAL_MCF5272_PLIC_PDRQR_DRQ_SHIFT 0
|
| 1015 |
|
|
|
| 1016 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_FSW_MASK (0x03 << 14)
|
| 1017 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_FSW_SHIFT 14
|
| 1018 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_FSW_1 (0x00 << 14)
|
| 1019 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_FSW_2 (0x01 << 14)
|
| 1020 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_FSW_8 (0x02 << 14)
|
| 1021 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_FSW_16 (0x03 << 14)
|
| 1022 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_SD_MASK (0x03FF << 0)
|
| 1023 |
|
|
#define HAL_MCF5272_PLIC_PnSDR_SD_SHIFT 0
|
| 1024 |
|
|
|
| 1025 |
|
|
#define HAL_MCF5272_PLIC_PCSR_NBP (0x01 << 15)
|
| 1026 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CKI_MASK (0x03 << 6)
|
| 1027 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CKI_SHIFT 6
|
| 1028 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CKI_DCL0 (0x00 << 6)
|
| 1029 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CKI_FSC0 (0x01 << 6)
|
| 1030 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_MASK (0x07 << 3)
|
| 1031 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_SHIFT 3
|
| 1032 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_4 (0x00 << 3)
|
| 1033 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_8 (0x01 << 3)
|
| 1034 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_16 (0x02 << 3)
|
| 1035 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_32 (0x03 << 3)
|
| 1036 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_64 (0x04 << 3)
|
| 1037 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_128 (0x05 << 3)
|
| 1038 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_192 (0x06 << 3)
|
| 1039 |
|
|
#define HAL_MCF5272_PLIC_PCSR_FDIV_256 (0x07 << 3)
|
| 1040 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_MASK (0x07 << 0)
|
| 1041 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_SHIFT 0
|
| 1042 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_2 (0x00 << 0)
|
| 1043 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_4 (0x01 << 0)
|
| 1044 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_8 (0x02 << 0)
|
| 1045 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_16 (0x03 << 0)
|
| 1046 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_32 (0x04 << 0)
|
| 1047 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_64 (0x05 << 0)
|
| 1048 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_128 (0x06 << 0)
|
| 1049 |
|
|
#define HAL_MCF5272_PLIC_PCSR_CMULT_256 (0x07 << 0)
|
| 1050 |
|
|
|
| 1051 |
|
|
// ----------------------------------------------------------------------------
|
| 1052 |
|
|
// The system timers. There are four timers at different MBAR offsets
|
| 1053 |
|
|
//
|
| 1054 |
|
|
// Some of these definitions could be re-used on other xxxx processors, but
|
| 1055 |
|
|
// recent ones from the 5282 onwards have very different timer support.
|
| 1056 |
|
|
|
| 1057 |
|
|
#define HAL_MCF5272_TIMER0_BASE 0x0200
|
| 1058 |
|
|
#define HAL_MCF5272_TIMER1_BASE 0x0220
|
| 1059 |
|
|
#define HAL_MCF5272_TIMER2_BASE 0x0240
|
| 1060 |
|
|
#define HAL_MCF5272_TIMER3_BASE 0x0260
|
| 1061 |
|
|
|
| 1062 |
|
|
// The register offsets for each timer. All registers are 16 bits
|
| 1063 |
|
|
#define HAL_MCF5272_TIMER_TMR 0x0000
|
| 1064 |
|
|
#define HAL_MCF5272_TIMER_TRR 0x0004
|
| 1065 |
|
|
#define HAL_MCF5272_TIMER_TCR 0x0008
|
| 1066 |
|
|
#define HAL_MCF5272_TIMER_TCN 0x000C
|
| 1067 |
|
|
#define HAL_MCF5272_TIMER_TER 0x0010
|
| 1068 |
|
|
|
| 1069 |
|
|
// The bits
|
| 1070 |
|
|
#define HAL_MCF5272_TIMER_TMR_PS_MASK 0xFF00
|
| 1071 |
|
|
#define HAL_MCF5272_TIMER_TMR_PS_SHIFT 8
|
| 1072 |
|
|
#define HAL_MCF5272_TIMER_TMR_CE_MASK (0x0003 << 6)
|
| 1073 |
|
|
// OM is only available for timers 0 and 1
|
| 1074 |
|
|
#define HAL_MCF5272_TIMER_TMR_OM (0x0001 << 5)
|
| 1075 |
|
|
#define HAL_MCF5272_TIMER_TMR_ORI (0x0001 << 4)
|
| 1076 |
|
|
#define HAL_MCF5272_TIMER_TMR_FRR (0x0001 << 3)
|
| 1077 |
|
|
#define HAL_MCF5272_TIMER_TMR_CLK_MASK (0x0003 << 1)
|
| 1078 |
|
|
#define HAL_MCF5272_TIMER_TMR_CLK_STOP (0x0000 << 1)
|
| 1079 |
|
|
#define HAL_MCF5272_TIMER_TMR_CLK_MASTER (0x0001 << 1)
|
| 1080 |
|
|
#define HAL_MCF5272_TIMER_TMR_CLK_MASTER_DIV_16 (0x0002 << 1)
|
| 1081 |
|
|
#define HAL_MCF5272_TIMER_TMR_CLK_TIN (0x0003 << 1)
|
| 1082 |
|
|
#define HAL_MCF5272_TIMER_TMR_RST (0x0001 << 0)
|
| 1083 |
|
|
|
| 1084 |
|
|
#define HAL_MCF5272_TIMER_TER_REF (0x0001 << 1)
|
| 1085 |
|
|
#define HAL_MCF5272_TIMER_TER_CAP (0x0001 << 0)
|
| 1086 |
|
|
|
| 1087 |
|
|
// ----------------------------------------------------------------------------
|
| 1088 |
|
|
// GPIO pins. PACNT/PBCNT/PDCNT are 32-bit. The others are 16-bit.
|
| 1089 |
|
|
|
| 1090 |
|
|
#define HAL_MCF5272_PACNT 0x0080
|
| 1091 |
|
|
#define HAL_MCF5272_PADDR 0x0084
|
| 1092 |
|
|
#define HAL_MCF5272_PADAT 0x0086
|
| 1093 |
|
|
#define HAL_MCF5272_PBCNT 0x0088
|
| 1094 |
|
|
#define HAL_MCF5272_PBDDR 0x008C
|
| 1095 |
|
|
#define HAL_MCF5272_PBDAT 0x008E
|
| 1096 |
|
|
#define HAL_MCF5272_PCDDR 0x0094
|
| 1097 |
|
|
#define HAL_MCF5272_PCDAT 0x0096
|
| 1098 |
|
|
#define HAL_MCF5272_PDCNT 0x0098
|
| 1099 |
|
|
|
| 1100 |
|
|
// Then the bits. The direction and data registers are only
|
| 1101 |
|
|
// relevant if the pin is controlled for GPIO, as per the
|
| 1102 |
|
|
// appropriate 2-bit entry in the control register.
|
| 1103 |
|
|
#define HAL_MCF5272_PACNT_PACNT15_MASK (0x03 << 30)
|
| 1104 |
|
|
#define HAL_MCF5272_PACNT_PACNT15_PA15 (0x00 << 30)
|
| 1105 |
|
|
#define HAL_MCF5272_PACNT_PACNT15_DGNT1 (0x01 << 30)
|
| 1106 |
|
|
#define HAL_MCF5272_PACNT_PACNT14_MASK (0x03 << 28)
|
| 1107 |
|
|
#define HAL_MCF5272_PACNT_PACNT14_PA14 (0x00 << 28)
|
| 1108 |
|
|
#define HAL_MCF5272_PACNT_PACNT14_DREQ1 (0x01 << 28)
|
| 1109 |
|
|
#define HAL_MCF5272_PACNT_PACNT13_MASK (0x03 << 26)
|
| 1110 |
|
|
#define HAL_MCF5272_PACNT_PACNT13_PA13 (0x00 << 26)
|
| 1111 |
|
|
#define HAL_MCF5272_PACNT_PACNT13_DFSC3 (0x01 << 26)
|
| 1112 |
|
|
#define HAL_MCF5272_PACNT_PACNT12_MASK (0x03 << 24)
|
| 1113 |
|
|
#define HAL_MCF5272_PACNT_PACNT12_PA12 (0x00 << 24)
|
| 1114 |
|
|
#define HAL_MCF5272_PACNT_PACNT12_DFSC2 (0x01 << 24)
|
| 1115 |
|
|
#define HAL_MCF5272_PACNT_PACNT11_MASK (0x03 << 22)
|
| 1116 |
|
|
#define HAL_MCF5272_PACNT_PACNT11_PA11 (0x00 << 22)
|
| 1117 |
|
|
#define HAL_MCF5272_PACNT_PACNT11_QSPI_CS1 (0x02 << 22)
|
| 1118 |
|
|
#define HAL_MCF5272_PACNT_PACNT10_MASK (0x03 << 20)
|
| 1119 |
|
|
#define HAL_MCF5272_PACNT_PACNT10_PA10 (0x00 << 20)
|
| 1120 |
|
|
#define HAL_MCF5272_PACNT_PACNT10_DREQ0 (0x01 << 20)
|
| 1121 |
|
|
#define HAL_MCF5272_PACNT_PACNT9_MASK (0x03 << 18)
|
| 1122 |
|
|
#define HAL_MCF5272_PACNT_PACNT9_PA9 (0x00 << 18)
|
| 1123 |
|
|
#define HAL_MCF5272_PACNT_PACNT9_DGNT0 (0x01 << 18)
|
| 1124 |
|
|
#define HAL_MCF5272_PACNT_PACNT8_MASK (0x03 << 16)
|
| 1125 |
|
|
#define HAL_MCF5272_PACNT_PACNT8_PA8 (0x00 << 16)
|
| 1126 |
|
|
#define HAL_MCF5272_PACNT_PACNT8_FSC0_FSR0 (0x01 << 16)
|
| 1127 |
|
|
#define HAL_MCF5272_PACNT_PACNT7_MASK (0x03 << 14)
|
| 1128 |
|
|
#define HAL_MCF5272_PACNT_PACNT7_PA7 (0x00 << 14)
|
| 1129 |
|
|
#define HAL_MCF5272_PACNT_PACNT7_QSPI_CS3 (0x01 << 14)
|
| 1130 |
|
|
#define HAL_MCF5272_PACNT_PACNT7_DOUT3 (0x02 << 14)
|
| 1131 |
|
|
#define HAL_MCF5272_PACNT_PACNT6_MASK (0x03 << 12)
|
| 1132 |
|
|
#define HAL_MCF5272_PACNT_PACNT6_PA6 (0x00 << 12)
|
| 1133 |
|
|
#define HAL_MCF5272_PACNT_PACNT6_USB_RXD (0x01 << 12)
|
| 1134 |
|
|
#define HAL_MCF5272_PACNT_PACNT5_MASK (0x03 << 10)
|
| 1135 |
|
|
#define HAL_MCF5272_PACNT_PACNT5_PA5 (0x00 << 10)
|
| 1136 |
|
|
#define HAL_MCF5272_PACNT_PACNT5_USB_TXEN (0x01 << 10)
|
| 1137 |
|
|
#define HAL_MCF5272_PACNT_PACNT4_MASK (0x03 << 8)
|
| 1138 |
|
|
#define HAL_MCF5272_PACNT_PACNT4_PA4 (0x00 << 8)
|
| 1139 |
|
|
#define HAL_MCF5272_PACNT_PACNT4_USB_SUSP (0x01 << 8)
|
| 1140 |
|
|
#define HAL_MCF5272_PACNT_PACNT3_MASK (0x03 << 6)
|
| 1141 |
|
|
#define HAL_MCF5272_PACNT_PACNT3_PA3 (0x00 << 6)
|
| 1142 |
|
|
#define HAL_MCF5272_PACNT_PACNT3_USB_TN (0x01 << 6)
|
| 1143 |
|
|
#define HAL_MCF5272_PACNT_PACNT2_MASK (0x03 << 4)
|
| 1144 |
|
|
#define HAL_MCF5272_PACNT_PACNT2_PA2 (0x00 << 4)
|
| 1145 |
|
|
#define HAL_MCF5272_PACNT_PACNT2_USB_RN (0x01 << 4)
|
| 1146 |
|
|
#define HAL_MCF5272_PACNT_PACNT1_MASK (0x03 << 2)
|
| 1147 |
|
|
#define HAL_MCF5272_PACNT_PACNT1_PA1 (0x00 << 2)
|
| 1148 |
|
|
#define HAL_MCF5272_PACNT_PACNT1_USB_RP (0x01 << 2)
|
| 1149 |
|
|
#define HAL_MCF5272_PACNT_PACNT0_MASK (0x03 << 0)
|
| 1150 |
|
|
#define HAL_MCF5272_PACNT_PACNT0_PA0 (0x00 << 0)
|
| 1151 |
|
|
#define HAL_MCF5272_PACNT_PACNT0_USB_TP (0x01 << 0)
|
| 1152 |
|
|
|
| 1153 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT15_MASK (0x03 << 30)
|
| 1154 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT15_PB15 (0x00 << 30)
|
| 1155 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT15_E_MDC (0x01 << 30)
|
| 1156 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT14_MASK (0x03 << 28)
|
| 1157 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT14_PB14 (0x00 << 28)
|
| 1158 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT14_E_RXER (0x01 << 28)
|
| 1159 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT13_MASK (0x03 << 26)
|
| 1160 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT13_PB13 (0x00 << 26)
|
| 1161 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT13_E_RXD1 (0x01 << 26)
|
| 1162 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT12_MASK (0x03 << 24)
|
| 1163 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT12_PB12 (0x00 << 24)
|
| 1164 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT12_E_RXD2 (0x01 << 24)
|
| 1165 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT11_MASK (0x03 << 22)
|
| 1166 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT11_PB11 (0x00 << 22)
|
| 1167 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT11_E_RXD3 (0x01 << 22)
|
| 1168 |
|
|
// The original user manual defined QSPI_CS for 0x02. This has
|
| 1169 |
|
|
// been removed in the errata.
|
| 1170 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT10_MASK (0x03 << 20)
|
| 1171 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT10_PB10 (0x00 << 20)
|
| 1172 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT10_E_TXD1 (0x01 << 20)
|
| 1173 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT9_MASK (0x03 << 18)
|
| 1174 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT9_PB9 (0x00 << 18)
|
| 1175 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT9_E_TXD2 (0x01 << 18)
|
| 1176 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT8_MASK (0x03 << 16)
|
| 1177 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT8_PB8 (0x00 << 16)
|
| 1178 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT8_E_TXD3 (0x01 << 16)
|
| 1179 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT7_MASK (0x03 << 14)
|
| 1180 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT7_PB7 (0x00 << 14)
|
| 1181 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT7_TOUT0 (0x01 << 14)
|
| 1182 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT6_MASK (0x03 << 12)
|
| 1183 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT6_PB6 (0x00 << 12)
|
| 1184 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT5_MASK (0x03 << 10)
|
| 1185 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT5_PB5 (0x00 << 10)
|
| 1186 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT5_TA (0x01 << 10)
|
| 1187 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT4_MASK (0x03 << 8)
|
| 1188 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT4_PB4 (0x00 << 8)
|
| 1189 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT4_URT0_CLK (0x01 << 8)
|
| 1190 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT3_MASK (0x03 << 6)
|
| 1191 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT3_PB3 (0x00 << 6)
|
| 1192 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT3_URT0_RTS (0x01 << 6)
|
| 1193 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT2_MASK (0x03 << 4)
|
| 1194 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT2_PB2 (0x00 << 4)
|
| 1195 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT2_URT0_CTS (0x01 << 4)
|
| 1196 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT1_MASK (0x03 << 2)
|
| 1197 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT1_PB1 (0x00 << 2)
|
| 1198 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT1_URT0_RXD (0x01 << 2)
|
| 1199 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT0_MASK (0x03 << 0)
|
| 1200 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT0_PB0 (0x00 << 0)
|
| 1201 |
|
|
#define HAL_MCF5272_PBCNT_PBCNT0_URT0_TXD (0x01 << 0)
|
| 1202 |
|
|
|
| 1203 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT7_MASK (0x03 << 14)
|
| 1204 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT7_HIGH (0x00 << 14)
|
| 1205 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT7_PWM_OUT3 (0x01 << 14)
|
| 1206 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT7_TIN1 (0x02 << 14)
|
| 1207 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT6_MASK (0x03 << 12)
|
| 1208 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT6_HIGH (0x00 << 12)
|
| 1209 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT6_PWM_OUT2 (0x01 << 12)
|
| 1210 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT6_TOUT1 (0x02 << 12)
|
| 1211 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT5_MASK (0x03 << 10)
|
| 1212 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT5_HIGH (0x00 << 10)
|
| 1213 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT5_DIN3 (0x02 << 10)
|
| 1214 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT5_INT4 (0x03 << 10)
|
| 1215 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT4_MASK (0x03 << 8)
|
| 1216 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT4_HIGH (0x00 << 8)
|
| 1217 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT4_DOUT0 (0x01 << 8)
|
| 1218 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT4_URT1_TXD (0x02 << 8)
|
| 1219 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT3_MASK (0x03 << 6)
|
| 1220 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT3_HIGH (0x00 << 6)
|
| 1221 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT3_URT1_RTS (0x02 << 6)
|
| 1222 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT3_INT5 (0x03 << 6)
|
| 1223 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT2_MASK (0x03 << 4)
|
| 1224 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT2_HIGH (0x00 << 4)
|
| 1225 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT2_URT1_CTS (0x02 << 4)
|
| 1226 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT2_QSPI_CS2 (0x03 << 4)
|
| 1227 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT1_MASK (0x03 << 2)
|
| 1228 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT1_HIGH (0x00 << 2)
|
| 1229 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT1_DIN0 (0x01 << 2)
|
| 1230 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT1_URT1_RXD (0x02 << 2)
|
| 1231 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT0_MASK (0x03 << 0)
|
| 1232 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT0_HIGH (0x00 << 0)
|
| 1233 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT0_DCL0 (0x01 << 0)
|
| 1234 |
|
|
#define HAL_MCF5272_PDCNT_PDCNT0_URT1_CLK (0x02 << 0)
|
| 1235 |
|
|
|
| 1236 |
|
|
// ----------------------------------------------------------------------------
|
| 1237 |
|
|
// PWM: six 8-bit registers, in three pairs
|
| 1238 |
|
|
#define HAL_MCF5272_PWCR0 0x00C0
|
| 1239 |
|
|
#define HAL_MCF5272_PWCR1 0x00C4
|
| 1240 |
|
|
#define HAL_MCF5272_PWCR2 0x00C8
|
| 1241 |
|
|
#define HAL_MCF5272_PWWD0 0x00D0
|
| 1242 |
|
|
#define HAL_MCF5272_PWWD1 0x00D4
|
| 1243 |
|
|
#define HAL_MCF5272_PWWD2 0x00D8
|
| 1244 |
|
|
|
| 1245 |
|
|
#define HAL_MCF5272_PWCR_EN (0x01 << 7)
|
| 1246 |
|
|
#define HAL_MCF5272_PWCR_FRC1 (0x01 << 6)
|
| 1247 |
|
|
#define HAL_MCF5272_PWCR_LVL (0x01 << 5)
|
| 1248 |
|
|
#define HAL_MCF5272_PWCR_CKSL_MASK (0x0F << 0)
|
| 1249 |
|
|
#define HAL_MCF5272_PWCR_CKSL_SHIFT 0
|
| 1250 |
|
|
#define HAL_MCF5272_PWCR_CKSL_1 (0x00 << 0)
|
| 1251 |
|
|
#define HAL_MCF5272_PWCR_CKSL_2 (0x01 << 0)
|
| 1252 |
|
|
#define HAL_MCF5272_PWCR_CKSL_4 (0x02 << 0)
|
| 1253 |
|
|
#define HAL_MCF5272_PWCR_CKSL_8 (0x03 << 0)
|
| 1254 |
|
|
#define HAL_MCF5272_PWCR_CKSL_16 (0x04 << 0)
|
| 1255 |
|
|
#define HAL_MCF5272_PWCR_CKSL_32 (0x05 << 0)
|
| 1256 |
|
|
#define HAL_MCF5272_PWCR_CKSL_64 (0x06 << 0)
|
| 1257 |
|
|
#define HAL_MCF5272_PWCR_CKSL_128 (0x07 << 0)
|
| 1258 |
|
|
#define HAL_MCF5272_PWCR_CKSL_256 (0x08 << 0)
|
| 1259 |
|
|
#define HAL_MCF5272_PWCR_CKSL_512 (0x09 << 0)
|
| 1260 |
|
|
#define HAL_MCF5272_PWCR_CKSL_1024 (0x0A << 0)
|
| 1261 |
|
|
#define HAL_MCF5272_PWCR_CKSL_2048 (0x0B << 0)
|
| 1262 |
|
|
#define HAL_MCF5272_PWCR_CKSL_4096 (0x0C << 0)
|
| 1263 |
|
|
#define HAL_MCF5272_PWCR_CKSL_8192 (0x0D << 0)
|
| 1264 |
|
|
#define HAL_MCF5272_PWCR_CKSL_16384 (0x0E << 0)
|
| 1265 |
|
|
#define HAL_MCF5272_PWCR_CKSL_32768 (0x0F << 0)
|
| 1266 |
|
|
|
| 1267 |
|
|
// ----------------------------------------------------------------------------
|
| 1268 |
|
|
// Now allow platform-specific overrides and additions
|
| 1269 |
|
|
#include <cyg/hal/plf_io.h>
|
| 1270 |
|
|
|
| 1271 |
|
|
#ifndef HAL_MCFxxxx_MBAR
|
| 1272 |
|
|
# define HAL_MCFxxxx_MBAR 0x10000000
|
| 1273 |
|
|
#endif
|
| 1274 |
|
|
|
| 1275 |
|
|
//-----------------------------------------------------------------------------
|
| 1276 |
|
|
#endif // CYGONCE_HAL_PROC_IO_H_FIRST_SECOND
|
