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//==========================================================================
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//
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// mcf5272.c
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//
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// MCF5272 processor support functions.
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2003, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): bartv
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// Date: 2003-06-04
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//
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//####DESCRIPTIONEND####
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//=============================================================================
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#include <pkgconf/system.h>
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_m68k.h>
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#include <pkgconf/hal_m68k_mcfxxxx.h>
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#include <pkgconf/hal_m68k_mcf5272.h>
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#include CYGBLD_HAL_PLATFORM_H
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#include <cyg/hal/hal_intr.h>
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#include <cyg/infra/cyg_type.h>
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#ifdef CYGHWR_HAL_M68K_MCF5272_GPIO
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# include "gpio.c"
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#endif
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// ----------------------------------------------------------------------------
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// Processor initialization.
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void
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hal_m68k_mcf5272_init(void)
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{
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int i;
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hal_mcf5272_cacr = CYGNUM_HAL_M68K_MCF5272_CACR;
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#ifdef CYGNUM_HAL_M68K_MCF5272_SCR
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// SCR. This is configurable since applications may want different
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// bus arbitration schemes. The #ifdef is for backwards compatibility.
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_SCR, CYGNUM_HAL_M68K_MCF5272_SCR);
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#endif
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// Set up the GPIO pins if the platform HAL defines the appropriate settings.
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#ifdef CYGHWR_HAL_M68K_MCF5272_GPIO
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PADAT, A_DAT);
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PADDR, A_DDR);
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HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PACNT, A_PAR);
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBDAT, B_DAT);
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBDDR, B_DDR);
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HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PBCNT, B_PAR);
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PCDAT, C_DAT);
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_PCDDR, C_DDR);
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HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PDCNT, D_PAR);
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#endif
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// Enable all exceptions.
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_SPR, 0x00FF);
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// If we should enter low power mode when idling, set the PMR here.
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// Application programs may tweak it as required.
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#if defined(CYGIMP_HAL_M68K_MCF5272_IDLE_run)
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// Leave PMR to its default
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#elif defined(CYGIMP_HAL_M68K_MCF5272_IDLE_sleep)
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HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PMR, HAL_MCF5272_PMR_SLPEN);
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#elif defined(CYGIMP_HAL_M68K_MCF5272_IDLE_stop)
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HAL_WRITE_UINT32(HAL_MCFxxxx_MBAR + HAL_MCF5272_PMR, HAL_MCF5272_PMR_MOS);
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#else
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# error Unknown low power mode
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#endif
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// Make sure that the interrupt controller matches the proc_intr.h
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// vector definitions.
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HAL_WRITE_UINT8( HAL_MCFxxxx_MBAR + HAL_MCF5272_PIVR, HAL_MCF5272_INT_VEC_BASE);
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// The interrupt controller. All interrupts are set to priority 0,
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// disabled until configured. This cannot be done when running on
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// top of RedBoot, it would interfere with any devices in use for
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// communication e.g. ethernet.
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#ifndef CYGSEM_HAL_USE_ROM_MONITOR
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for (i = 0; i < 4; i++) {
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hal_mcf5272_icr_pri_mirror[i] = 0x0;
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}
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#endif
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// Exception vectors. First the exceptions themselves. If running
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// with a ROM monitor then leave these alone, otherwise claim the
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// lot.
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#ifndef CYGSEM_HAL_USE_ROM_MONITOR
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HAL_VSR_SET(CYGNUM_HAL_VECTOR_SSP, (void*) 0, (void*) 0);
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HAL_VSR_SET(CYGNUM_HAL_VECTOR_RESET, &hal_m68k_exception_reset, (void*) 0);
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for (i = CYGNUM_HAL_VECTOR_BUSERR; i < CYGNUM_HAL_VECTOR_SPURINT; i++) {
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HAL_VSR_SET(i, &hal_m68k_exception_vsr, (void*) 0);
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}
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for (i = CYGNUM_HAL_VECTOR_TRAP0; i <= CYGNUM_HAL_VECTOR_TRAPLAST; i++) {
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HAL_VSR_SET(i, &hal_m68k_exception_vsr, (void*) 0);
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}
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#endif
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// All the external interrupts can be handled by the same VSR, the default
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// architectural one.
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for (i = HAL_MCF5272_INT_VEC_BASE; i < CYGNUM_HAL_VECTOR_RES1; i++) {
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HAL_VSR_SET(i, &hal_m68k_interrupt_vsr, (void*) 0);
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}
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}
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// ----------------------------------------------------------------------------
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// Profiling support. This requires a hardware timer set to interrupt at
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// a rate determined by application code. The interrupt handler should
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// call __profile_hit() with a single argument, the interrupted PC.
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// Timer 2 is used to implement the profiling timer. Timer 3 is already
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// allocated for the system clock. Timers 0 and 1 have some extra
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// functionality so these are left for application code.
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//
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// Usually this would involve installing an ISR. However there is no
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// easy way for an ISR to get hold of the interrupted PC. In some
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// configurations the save state will be stored in hal_saved_interrupt_state,
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// but not always. It might be possible to extract the PC from the stack,
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// but that gets messy if a separate interrupt stack is used and would be
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// vulnerable to changes in the architectural VSR. Instead a custom VSR
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// is installed.
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#ifdef CYGFUN_HAL_M68K_MCF5272_PROFILE_TIMER
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extern void hal_mcf5272_profile_vsr(void);
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# include <cyg/profile/profile.h>
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int
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hal_enable_profile_timer(int resolution)
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{
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// Reset the timer
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TMR, 0);
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// The resolution is a time interval in microseconds. The clock is
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// set to tick in microseconds by dividing by the system clock
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// value.
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TRR,
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resolution - 1);
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// Timer captures are of no interest, but reset them just in case.
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TCN, 0);
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TER,
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HAL_MCF5272_TIMER_TER_REF | HAL_MCF5272_TIMER_TER_CAP);
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// Set up the interrupt handler. This is a high-priority interrupt
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// so that we can get profiling information for other interrupt
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// sources.
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HAL_VSR_SET(CYGNUM_HAL_VECTOR_TMR2, &hal_mcf5272_profile_vsr, (cyg_uint32)0);
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HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_ISR_TMR2, 6);
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HAL_INTERRUPT_UNMASK(CYGNUM_HAL_ISR_TMR2);
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// Now start the timer running.
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HAL_WRITE_UINT16(HAL_MCFxxxx_MBAR + HAL_MCF5272_TIMER2_BASE + HAL_MCF5272_TIMER_TMR,
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((CYGHWR_HAL_SYSTEM_CLOCK_MHZ - 1) << HAL_MCF5272_TIMER_TMR_PS_SHIFT) |
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HAL_MCF5272_TIMER_TMR_ORI | HAL_MCF5272_TIMER_TMR_FRR |
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HAL_MCF5272_TIMER_TMR_CLK_MASTER | HAL_MCF5272_TIMER_TMR_RST);
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// The desired resolution is always supported
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return resolution;
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}
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#endif
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