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#ifndef CYGONCE_HAL_VAR_ARCH_H
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#define CYGONCE_HAL_VAR_ARCH_H
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//=============================================================================
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//
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// var_arch.h
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//
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// Architecture variant specific abstractions
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2003, 2006, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): bartv
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// Date: 2003-06-04
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//
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//####DESCRIPTIONEND####
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_m68k_mcfxxxx.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/proc_arch.h>
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// ----------------------------------------------------------------------------
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// Context support. ColdFire exceptions/interrupts are simpler than the
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// 68000 variants, with a much more regular exception frame. Usually the
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// hardware simply pushes two longs on to the stack. The program counter
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// is at the top. Then the 16-bit status register. Then some extra
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// information identifying the exception number etc. If the stack was not
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// aligned when the exception occurred) (which should not happen for
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// eCos code) then the hardware will do some extra stack alignment and
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// store this information in a fmt field. That possibility is ignored
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// for now.
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#define HAL_CONTEXT_PCSR \
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cyg_uint32 sr_vec; \
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CYG_ADDRESS pc;
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// An exception aligns the stack to a 32-bit boundary, and the fmt part
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// of the exception frame encodes how much adjustment was done. The
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// 0x40000000 specifies 0 bytes adjustment since the code should be
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// running with stacks always aligned.
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#define HAL_CONTEXT_PCSR_INIT(_regs_, _entry_, _sr_) \
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CYG_MACRO_START \
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(_regs_)->sr_vec = 0x40000000 | (cyg_uint32)(_sr_); \
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(_regs_)->pc = (CYG_ADDRESS)(_entry_); \
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CYG_MACRO_END
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#define HAL_CONTEXT_PCSR_GET_SR(_regs_, _sr_) \
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CYG_MACRO_START \
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_sr_ = (_regs_)->sr_vec & 0x0000FFFF; \
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CYG_MACRO_END
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#define HAL_CONTEXT_PCSR_GET_PC(_regs_, _pc_) \
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CYG_MACRO_START \
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_pc_ = (_regs_)->pc; \
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CYG_MACRO_END
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#define HAL_CONTEXT_PCSR_SET_SR(_regs_, _sr_) \
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CYG_MACRO_START \
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(_regs_)->sr_vec = ((_regs_)->sr_vec & 0xFFFF0000) | (_sr_); \
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CYG_MACRO_END
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#define HAL_CONTEXT_PCSR_SET_PC(_regs_, _pc_) \
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CYG_MACRO_START \
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(_regs_)->pc = (CYG_ADDRESS)(_pc_); \
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CYG_MACRO_END
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#define HAL_CONTEXT_PCSR_GET_EXCEPTION(_regs_, _code_) \
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CYG_MACRO_START \
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(_code_) = (((_regs_)->sr_vec) >> 18) & 0x000000FF; \
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CYG_MACRO_END
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// ----------------------------------------------------------------------------
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// LSBIT/MSBIT. Most ColdFires have ff1 and bitrev instructions which
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// allow for more efficient implementations than the default ones in
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// the architectural HAL.
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#ifndef _HAL_M68K_MCFxxxx_NO_FF1_
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# define HAL_LSBIT_INDEX(_index_, _mask_) \
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CYG_MACRO_START \
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cyg_uint32 _tmp_ = (_mask_); \
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int _idx_; \
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if (0 == _tmp_) { \
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_idx_ = -1; \
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} else { \
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__asm__ volatile ( \
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"move.l %1, %0 ; \n" \
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"bitrev.l %0 ; \n" \
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"ff1.l %0 ; \n" \
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: "=d" (_idx_) \
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: "d" (_mask_) \
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); \
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} \
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_index_ = _idx_; \
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CYG_MACRO_END
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# define HAL_MSBIT_INDEX(_index_, _mask_) \
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CYG_MACRO_START \
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cyg_uint32 _tmp_ = (_mask_); \
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int _idx_; \
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__asm__ volatile ( \
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"move.l %1, %0 ; \n" \
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"ff1.l %0\n" \
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: "=d" (_idx_) \
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: "d" (_tmp_) \
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); \
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_index_ = 31 - _idx_; \
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CYG_MACRO_END
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#endif
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//-----------------------------------------------------------------------------
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#endif // CYGONCE_HAL_VAR_ARCH_H
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