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skrzyp |
#ifndef CYGONCE_HAL_VAR_INTR_H
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#define CYGONCE_HAL_VAR_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// mcfxxxx Variant interrupt and clock support
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//
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2003, 2006, 2007, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//####DESCRIPTIONBEGIN####
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//
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// Author(s): bartv
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// Date: 2003-06-04
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//
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//####DESCRIPTIONEND####
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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// Include any processor specific interrupt definitions.
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#include <cyg/hal/proc_intr.h>
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// ColdFire defines some extra exceptions
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// The debug vector is for hardware breakpoints. These are not used
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// at present.
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#define CYGNUM_HAL_VECTOR_DEBUG 12
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#define CYGNUM_HAL_VECTOR_FORMAT 14
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// The following implementation should suffice for most platforms. If
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// any of them need special VSR's then they can define their own version.
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#if !defined(HAL_VSR_SET_TO_ECOS_HANDLER) && !defined(_HAL_M68K_NO_VSR_SET_)
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# define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_) \
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CYG_MACRO_START \
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if ( (_vector_) <= CYGNUM_HAL_VECTOR_TRAPLAST) { \
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HAL_VSR_SET( (_vector_), &hal_m68k_exception_vsr, (_poldvsr_) ); \
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} else { \
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HAL_VSR_SET( (_vector_), &hal_m68k_interrupt_vsr, (_poldvsr_) ); \
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} \
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CYG_MACRO_END
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#endif
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// ----------------------------------------------------------------------------
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// On ColdFires with 5282-style interrupt controllers, many of the
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// interrupt-related macros can be provided here rather than duplicated
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// in the processor HALs. Of course there complications, for example there
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// may be one or two interrupt controllers.
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#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC
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# ifndef HAL_INTERRUPT_MASK
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// Masking interrupts is straightforward: there are 32-bit read-write
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// mask registers. Often the vector argument will be a constant so the
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// compiler gets a chance to optimise these macros. There is also some
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// compile-time optimization based around the maximum number of
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// interrupt vectors. to avoid worrying about interrupts 32-63 if only
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// the bottom half of INTC0 is of interest, or interrupts 96-127 if
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// only the bottom half of INTC1 is of interest.
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//
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// Some newer ColdFires have additional set/clear mask registers.
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# ifdef HAL_MCFxxxx_INTCx_SIMR
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# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_MASK(_vector_) \
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CYG_MACRO_START \
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HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_SIMR, (_vector_)); \
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CYG_MACRO_END
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# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_MASK(_vector_) \
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CYG_MACRO_START \
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cyg_uint32 _vec_ = (_vector_); \
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if (_vec_ < 64) { \
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HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_SIMR, _vec_); \
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} else { \
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HAL_WRITE_UINT8(HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_SIMR, _vec_ - 64); \
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} \
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CYG_MACRO_END
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# else
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# error At most two interrupt controllers supported at present.
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# endif
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# else // ! SIMR
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# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_MASK(_vector_) \
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CYG_MACRO_START \
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cyg_uint32 _shift_ = (_vector_); \
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cyg_uint32 _reg_; \
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cyg_uint32 _bits_; \
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if ( (CYGNUM_HAL_ISR_MAX < 32) || (_shift_ < 32)) { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \
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} else { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \
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_shift_ -= 32; \
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} \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ |= (0x01 << _shift_); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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CYG_MACRO_END
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# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_MASK(_vector_) \
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CYG_MACRO_START \
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cyg_uint32 _shift_ = (_vector_); \
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cyg_uint32 _reg_; \
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cyg_uint32 _bits_; \
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if ( (CYGNUM_HAL_ISR_MAX < 32) || (_shift_ < 32)) { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \
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} else if ((CYGNUM_HAL_ISR_MAX < 64) || (_shift_ < 64)) { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \
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_shift_ -= 32; \
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} else if ((CYGNUM_HAL_ISR_MAX < 96) || (_shift_ < 96)) { \
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_reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRL; \
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_shift_ -= 64; \
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} else { \
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_reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRH; \
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_shift_ -= 96; \
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} \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ |= (0x01 << _shift_); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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CYG_MACRO_END
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# else
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# error At most two interrupt controllers supported at present.
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# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many
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# endif // SIMR
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# endif // !defined(HAL_INTERRUPT_MASK)
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// Care has to be taken with bit 0 of the IMRL registers. Writing a 1 to
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// this masks all interrupts.
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# ifndef HAL_INTERRUPT_UNMASK
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# ifdef HAL_MCFxxxx_INTCx_CIMR
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# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_UNMASK(_vector_) \
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CYG_MACRO_START \
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HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_CIMR, (_vector_)); \
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CYG_MACRO_END
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# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_UNMASK(_vector_) \
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CYG_MACRO_START \
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cyg_uint32 _vec_ = (_vector_); \
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if (_vec_ < 64) { \
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HAL_WRITE_UINT8(HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_CIMR, _vec_); \
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} else { \
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HAL_WRITE_UINT8(HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_CIMR, _vec_ - 64); \
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} \
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CYG_MACRO_END
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# else
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# error At most two interrupt controllers supported at present.
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# endif
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# else
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# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_UNMASK(_vector_) \
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CYG_MACRO_START \
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cyg_uint32 _vec_ = (_vector_); \
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cyg_uint32 _reg_; \
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cyg_uint32 _bits_; \
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if ( (CYGNUM_HAL_ISR_MAX < 32) || (_vec_ < 32)) { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ &= ~((0x01 << _vec_) | 0x01); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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} else { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ &= ~(0x01 << (_vec_ - 32)); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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} \
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CYG_MACRO_END
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# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_UNMASK(_vector_) \
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CYG_MACRO_START \
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cyg_uint32 _vec_ = (_vector_); \
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cyg_uint32 _reg_; \
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cyg_uint32 _bits_; \
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if ( (CYGNUM_HAL_ISR_MAX < 32) || (_vec_ < 32)) { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRL; \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ &= ~((0x01 << _vec_) | 0x01); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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} else if ((CYGNUM_HAL_ISR_MAX < 64) || (_vec_ < 64)) { \
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_IMRH; \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ &= ~(0x01 << (_vec_ - 32)); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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} else if ((CYGNUM_HAL_ISR_MAX < 96) || (_vec_ < 96)) { \
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_reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRL; \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ &= ~((0x01 << (_vec_ - 64)) | 0x01); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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} else { \
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_reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_IMRH; \
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HAL_READ_UINT32(_reg_, _bits_); \
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_bits_ &= ~(0x01 << (_vec_ - 96)); \
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HAL_WRITE_UINT32(_reg_, _bits_); \
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} \
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CYG_MACRO_END
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# else
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# error At most two interrupt controllers supported at present.
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# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many
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# endif // HAL_MCFxxxx_INTCx_CIMR
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# endif // !defined(HAL_INTERRUPT_UNMASK)
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# ifndef HAL_INTERRUPT_SET_LEVEL
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// Each interrupt vector has its own priority register. This consists
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// of an M68K IPL level between 1 and 7, plus a priority within each
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// level between 0 and 7, giving a total of 56 legal priorities. All
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// active interrupt vectors within each interrupt vector must be given
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// unique priorities, otherwise the system's behaviour is undefined
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// (and can include the interrupt controller supplying the wrong
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// interrupt vector in the IACK cycle).
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# if (1 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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| 244 |
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# define HAL_INTERRUPT_SET_LEVEL(_vector_, _prilevel_) \
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| 245 |
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CYG_MACRO_START \
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| 246 |
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cyg_uint32 _vec_ = (_vector_); \
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| 247 |
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cyg_uint32 _reg_; \
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| 248 |
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_; \
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HAL_WRITE_UINT8(_reg_, _prilevel_); \
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| 250 |
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CYG_MACRO_END
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| 251 |
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| 252 |
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# elif (2 == HAL_MCFxxxx_HAS_MCF5282_INTC)
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# define HAL_INTERRUPT_SET_LEVEL(_vector_, _prilevel_) \
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| 254 |
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CYG_MACRO_START \
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| 255 |
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cyg_uint32 _vec_ = (_vector_); \
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| 256 |
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cyg_uint32 _reg_; \
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| 257 |
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if( _vec_ < 64 ) \
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| 258 |
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_reg_ = HAL_MCFxxxx_INTC0_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_; \
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| 259 |
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else \
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| 260 |
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_reg_ = HAL_MCFxxxx_INTC1_BASE + HAL_MCFxxxx_INTCx_ICR00 + _vec_ - 64;\
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HAL_WRITE_UINT8(_reg_, _prilevel_); \
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| 262 |
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CYG_MACRO_END
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| 263 |
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| 264 |
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# else
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| 265 |
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# error At most two interrupt controllers supported at present.
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| 266 |
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# endif // HAL_MCFxxxx_HAS_MCF5282_INTC == 1/2/many
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| 267 |
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# endif // !defined(HAL_INTERRUPT_SET_LEVEL)
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| 268 |
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| 269 |
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#endif // HAL_MCFxxxx_HAS_MCF5282_INTC
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| 270 |
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| 271 |
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#ifdef HAL_MCFxxxx_HAS_MCF5282_EPORT
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| 272 |
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// There is no acknowledgement support inside the interrupt
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| 273 |
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// controller. Instead each device has its own way of clearing the
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| 274 |
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// interrupt, so it is left to device drivers to clear interrupts at
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| 275 |
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// an appropriate time. The exception is for the edge port interrupts
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| 276 |
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// which can be handled easily here.
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| 277 |
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# ifndef HAL_INTERRUPT_ACKNOWLEDGE
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| 278 |
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# if (1 == HAL_MCFxxxx_HAS_MCF5282_EPORT)
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| 279 |
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| 280 |
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# define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \
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| 281 |
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CYG_MACRO_START \
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| 282 |
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cyg_uint32 _vec_ = (_vector_); \
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| 283 |
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if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \
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| 284 |
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HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT0_BASE + HAL_MCFxxxx_EPORTx_EPFR, \
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| 285 |
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0x01 << (_vec_ - HAL_MCFxxxx_EPORT0_VECBASE)); \
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| 286 |
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} \
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| 287 |
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CYG_MACRO_END
|
| 288 |
|
|
|
| 289 |
|
|
# elif (2 == HAL_MCFxxxx_HAS_MCF5282_EPORT)
|
| 290 |
|
|
# define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \
|
| 291 |
|
|
CYG_MACRO_START \
|
| 292 |
|
|
cyg_uint32 _vec_ = (_vector_); \
|
| 293 |
|
|
if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \
|
| 294 |
|
|
HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT0_BASE + HAL_MCFxxxx_EPORTx_EPFR, \
|
| 295 |
|
|
0x01 << (_vec_ - HAL_MCFxxxx_EPORT0_VECBASE)); \
|
| 296 |
|
|
} else if ((_vec_ >= HAL_MCFxxxx_EPORT1_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT1_VECMAX)) { \
|
| 297 |
|
|
HAL_WRITE_UINT8(HAL_MCFxxxx_EPORT1_BASE + HAL_MCFxxxx_EPORTx_EPFR, \
|
| 298 |
|
|
0x01 << (_vec_ - HAL_MCFxxxx_EPORT1_VECBASE)); \
|
| 299 |
|
|
} \
|
| 300 |
|
|
CYG_MACRO_END
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
# else
|
| 304 |
|
|
# error At most two edge port modules are supported at present.
|
| 305 |
|
|
# endif // HAL_MCFxxxx_HAS_MCF5282_EPORT == 1/2/many
|
| 306 |
|
|
# endif // !defined(HAL_INTERRUPT_ACKNOWLEDGE)
|
| 307 |
|
|
|
| 308 |
|
|
# ifndef HAL_INTERRUPT_CONFIGURE
|
| 309 |
|
|
|
| 310 |
|
|
// Interrupt level/edge control only applies to the edge port
|
| 311 |
|
|
// interrupts. It is possible to select level-low, rising edge, or
|
| 312 |
|
|
// falling edge. The hardware does not support level-high. It does
|
| 313 |
|
|
// support rising-or-falling edge, but the eCos API does not export
|
| 314 |
|
|
// that functionality. Instead code can manipulate the edge port
|
| 315 |
|
|
// registers directly.
|
| 316 |
|
|
//
|
| 317 |
|
|
// This macro also manipulates the edge port data direction and
|
| 318 |
|
|
// interrupt enable registers, to ensure that the edge port really
|
| 319 |
|
|
// will generate interrupts.
|
| 320 |
|
|
|
| 321 |
|
|
# if (1 == HAL_MCFxxxx_HAS_MCF5282_EPORT)
|
| 322 |
|
|
|
| 323 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_triggered_, _up_) \
|
| 324 |
|
|
CYG_MACRO_START \
|
| 325 |
|
|
cyg_uint32 _vec_ = (_vector_); \
|
| 326 |
|
|
if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \
|
| 327 |
|
|
cyg_uint32 _base_; \
|
| 328 |
|
|
cyg_uint16 _reg16_; \
|
| 329 |
|
|
cyg_uint8 _reg8_; \
|
| 330 |
|
|
_base_ = HAL_MCFxxxx_EPORT0_BASE; \
|
| 331 |
|
|
_vec_ -= HAL_MCFxxxx_EPORT0_VECBASE; \
|
| 332 |
|
|
HAL_READ_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \
|
| 333 |
|
|
_reg16_ &= ~(0x03 << (2 * _vec_)); \
|
| 334 |
|
|
if (_level_triggered_) { \
|
| 335 |
|
|
/* 00 is level-triggered so nothing to be done */ \
|
| 336 |
|
|
} else if (_up_) { \
|
| 337 |
|
|
_reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING << (2 * _vec_)); \
|
| 338 |
|
|
} else { \
|
| 339 |
|
|
_reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING << (2 * _vec_)); \
|
| 340 |
|
|
} \
|
| 341 |
|
|
HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \
|
| 342 |
|
|
HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \
|
| 343 |
|
|
_reg8_ &= ~(0x01 << _vec_); \
|
| 344 |
|
|
HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \
|
| 345 |
|
|
HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \
|
| 346 |
|
|
_reg8_ |= (0x01 << _vec_); \
|
| 347 |
|
|
HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \
|
| 348 |
|
|
} \
|
| 349 |
|
|
CYG_MACRO_END
|
| 350 |
|
|
|
| 351 |
|
|
# elif (2 == HAL_MCFxxxx_HAS_MCF5282_EPORT)
|
| 352 |
|
|
|
| 353 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_triggered_, _up_) \
|
| 354 |
|
|
CYG_MACRO_START \
|
| 355 |
|
|
cyg_uint32 _vec_ = (_vector_); \
|
| 356 |
|
|
if (((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) || \
|
| 357 |
|
|
((_vec_ >= HAL_MCFxxxx_EPORT1_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT1_VECMAX))) { \
|
| 358 |
|
|
cyg_uint32 _base_; \
|
| 359 |
|
|
cyg_uint16 _reg16_; \
|
| 360 |
|
|
cyg_uint8 _reg8_; \
|
| 361 |
|
|
if ((_vec_ >= HAL_MCFxxxx_EPORT0_VECMIN) && (_vec_ <= HAL_MCFxxxx_EPORT0_VECMAX)) { \
|
| 362 |
|
|
_base_ = HAL_MCFxxxx_EPORT0_BASE; \
|
| 363 |
|
|
_vec_ -= HAL_MCFxxxx_EPORT0_VECBASE; \
|
| 364 |
|
|
} else { \
|
| 365 |
|
|
_base_ = HAL_MCFxxxx_EPORT1_BASE; \
|
| 366 |
|
|
_vec_ -= HAL_MCFxxxx_EPORT1_VECBASE; \
|
| 367 |
|
|
} \
|
| 368 |
|
|
HAL_READ_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \
|
| 369 |
|
|
_reg16_ &= ~(0x03 << (2 * _vec_)); \
|
| 370 |
|
|
if (_level_triggered_) { \
|
| 371 |
|
|
/* 00 is level-triggered so nothing to be done */ \
|
| 372 |
|
|
} else if (_up_) { \
|
| 373 |
|
|
_reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING << (2 * _vec_)); \
|
| 374 |
|
|
} else { \
|
| 375 |
|
|
_reg16_ |= (HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING << (2 * _vec_)); \
|
| 376 |
|
|
} \
|
| 377 |
|
|
HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_EPORTx_EPPAR, _reg16_); \
|
| 378 |
|
|
HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \
|
| 379 |
|
|
_reg8_ &= ~(0x01 << _vec_); \
|
| 380 |
|
|
HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPDDR, _reg8_); \
|
| 381 |
|
|
HAL_READ_UINT8( _base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \
|
| 382 |
|
|
_reg8_ |= (0x01 << _vec_); \
|
| 383 |
|
|
HAL_WRITE_UINT8(_base_ + HAL_MCFxxxx_EPORTx_EPIER, _reg8_); \
|
| 384 |
|
|
} \
|
| 385 |
|
|
CYG_MACRO_END
|
| 386 |
|
|
|
| 387 |
|
|
# else
|
| 388 |
|
|
# endif // HAL_MCFxxxx_HAS_MCF5282_EPORT == 1/2/many
|
| 389 |
|
|
# endif // !defined(HAL_INTERRUPT_CONFIGURE)
|
| 390 |
|
|
|
| 391 |
|
|
#endif
|
| 392 |
|
|
|
| 393 |
|
|
#ifndef HAL_INTERRUPT_MASK
|
| 394 |
|
|
# error Processor or platform HAL_ should have provided HAL_INTERRUPT_MASK() macro
|
| 395 |
|
|
#endif
|
| 396 |
|
|
#ifndef HAL_INTERRUPT_UNMASK
|
| 397 |
|
|
# error Processor or platform HAL_ should have provided HAL_INTERRUPT_UNMASK() macro
|
| 398 |
|
|
#endif
|
| 399 |
|
|
#ifndef HAL_INTERRUPT_SET_LEVEL
|
| 400 |
|
|
# error Processor or platform HAL_ should have provided HAL_INTERRUPT_SET_LEVEL() macro
|
| 401 |
|
|
#endif
|
| 402 |
|
|
#ifndef HAL_INTERRUPT_ACKNOWLEDGE
|
| 403 |
|
|
# error Processor or platform HAL_ should have provided HAL_INTERRUPT_ACKNOWLEDGE() macro
|
| 404 |
|
|
#endif
|
| 405 |
|
|
#ifndef HAL_INTERRUPT_CONFIGURE
|
| 406 |
|
|
# error Processor or platform HAL_ should have provided HAL_INTERRUPT_CONFIGURE() macro
|
| 407 |
|
|
#endif
|
| 408 |
|
|
|
| 409 |
|
|
// ----------------------------------------------------------------------------
|
| 410 |
|
|
// On ColdFires with 5282-style programmable interrupt timers, typically
|
| 411 |
|
|
// one of those will be used for the system clock.
|
| 412 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_PIT
|
| 413 |
|
|
|
| 414 |
|
|
# if (!defined(HAL_CLOCK_INIITALIZE) || !defined(HAL_CLOCK_RESET) || !defined(HAL_CLOCK_READ))
|
| 415 |
|
|
# if !defined(_HAL_MCFxxxx_CLOCK_PIT_BASE_)
|
| 416 |
|
|
# error The processor HAL should specify the programmable interrupt timer used for the system clock
|
| 417 |
|
|
# elif !defined(_HAL_MCFxxxx_CLOCK_PIT_PRE_)
|
| 418 |
|
|
# error The processor or platform HAL should specify the timer prescaler
|
| 419 |
|
|
# else
|
| 420 |
|
|
|
| 421 |
|
|
# if !defined(HAL_CLOCK_INITIALIZE)
|
| 422 |
|
|
# define HAL_CLOCK_INITIALIZE(_period_) \
|
| 423 |
|
|
CYG_MACRO_START \
|
| 424 |
|
|
cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \
|
| 425 |
|
|
HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \
|
| 426 |
|
|
_HAL_MCFxxxx_CLOCK_PIT_PRE_ | \
|
| 427 |
|
|
HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \
|
| 428 |
|
|
HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD); \
|
| 429 |
|
|
HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PMR, _period_); \
|
| 430 |
|
|
HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \
|
| 431 |
|
|
_HAL_MCFxxxx_CLOCK_PIT_PRE_ | \
|
| 432 |
|
|
HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \
|
| 433 |
|
|
HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD | \
|
| 434 |
|
|
HAL_MCFxxxx_PITx_PCSR_EN); \
|
| 435 |
|
|
CYG_MACRO_END
|
| 436 |
|
|
# endif
|
| 437 |
|
|
|
| 438 |
|
|
# if !defined(HAL_CLOCK_RESET)
|
| 439 |
|
|
// The clock resets automatically but the interrupt must be cleared. This could
|
| 440 |
|
|
// be done by rewriting the period, but that introduces a risk of drift. A
|
| 441 |
|
|
// better approach is to write the PIF bit in the control register, which means
|
| 442 |
|
|
// writing all the other bits as well.
|
| 443 |
|
|
//
|
| 444 |
|
|
// Note: this could interfere with power management since the doze/halted
|
| 445 |
|
|
// bits may get cleared inadvertently.
|
| 446 |
|
|
# define HAL_CLOCK_RESET(_vector_, _period_) \
|
| 447 |
|
|
CYG_MACRO_START \
|
| 448 |
|
|
cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \
|
| 449 |
|
|
HAL_WRITE_UINT16(_base_ + HAL_MCFxxxx_PITx_PCSR, \
|
| 450 |
|
|
_HAL_MCFxxxx_CLOCK_PIT_PRE_ | \
|
| 451 |
|
|
HAL_MCFxxxx_PITx_PCSR_OVW | HAL_MCFxxxx_PITx_PCSR_PIE | \
|
| 452 |
|
|
HAL_MCFxxxx_PITx_PCSR_PIF | HAL_MCFxxxx_PITx_PCSR_RLD | \
|
| 453 |
|
|
HAL_MCFxxxx_PITx_PCSR_EN); \
|
| 454 |
|
|
CYG_MACRO_END
|
| 455 |
|
|
# endif
|
| 456 |
|
|
|
| 457 |
|
|
# if !defined(HAL_CLOCK_READ)
|
| 458 |
|
|
# define HAL_CLOCK_READ(_pvalue_) \
|
| 459 |
|
|
CYG_MACRO_START \
|
| 460 |
|
|
cyg_uint32 _base_ = _HAL_MCFxxxx_CLOCK_PIT_BASE_; \
|
| 461 |
|
|
cyg_uint16 _period_, _counter_; \
|
| 462 |
|
|
HAL_READ_UINT16(_base_ + HAL_MCFxxxx_PITx_PMR, _period_); \
|
| 463 |
|
|
HAL_READ_UINT16(_base_ + HAL_MCFxxxx_PITx_PCNTR, _counter_); \
|
| 464 |
|
|
*(_pvalue_) = _period_ - _counter_; \
|
| 465 |
|
|
CYG_MACRO_END
|
| 466 |
|
|
# endif
|
| 467 |
|
|
# endif
|
| 468 |
|
|
# endif
|
| 469 |
|
|
#endif
|
| 470 |
|
|
|
| 471 |
|
|
#ifndef HAL_CLOCK_INITIALIZE
|
| 472 |
|
|
# error Processor or platform HAL should have provided HAL_CLOCK_INITIALIZE() macro
|
| 473 |
|
|
#endif
|
| 474 |
|
|
#ifndef HAL_CLOCK_RESET
|
| 475 |
|
|
# error Processor or platform HAL should have provided HAL_CLOCK_RESET() macro
|
| 476 |
|
|
#endif
|
| 477 |
|
|
#ifndef HAL_CLOCK_READ
|
| 478 |
|
|
# error Processor or platform HAL should have provided HAL_CLOCK_READ() macro
|
| 479 |
|
|
#endif
|
| 480 |
|
|
|
| 481 |
|
|
#ifndef HAL_CLOCK_LATENCY
|
| 482 |
|
|
# define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
|
| 483 |
|
|
#endif
|
| 484 |
|
|
|
| 485 |
|
|
// ----------------------------------------------------------------------------
|
| 486 |
|
|
// Where possible use a 5282-compatible reset controller to generate a
|
| 487 |
|
|
// software reset. The architectural HAL has a fall-back
|
| 488 |
|
|
// implementation which goes through the reset exception vector slot.
|
| 489 |
|
|
#if !defined(HAL_PLATFORM_RESET) && defined(HAL_MCFxxxx_HAS_MCF5282_RST)
|
| 490 |
|
|
# define HAL_PLATFORM_RESET() \
|
| 491 |
|
|
CYG_MACRO_START \
|
| 492 |
|
|
HAL_WRITE_UINT8(HAL_MCFxxxx_RST_BASE + HAL_MCFxxxx_RST_RCR, \
|
| 493 |
|
|
HAL_MCFxxxx_RST_RCR_SOFTRST); \
|
| 494 |
|
|
CYG_MACRO_END
|
| 495 |
|
|
# endif
|
| 496 |
|
|
|
| 497 |
|
|
//---------------------------------------------------------------------------
|
| 498 |
|
|
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
|
