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#ifndef CYGONCE_HAL_VAR_IO_H
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#define CYGONCE_HAL_VAR_IO_H
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//=============================================================================
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//
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// var_io.h
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//
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// Details of mcfxxxx memory-mapped hardware
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2003, 2004, 2006, 2008, 2009 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//####DESCRIPTIONBEGIN####
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//
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// Author(s): bartv
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// Date: 2003-06-04
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//
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//####DESCRIPTIONEND####
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//=============================================================================
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// Most coldfire processors share some/most of their on-chip
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// peripherals with the mcf5282, so that is treated as the base
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// device. The goal is to reduce the effort needed to support each
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// ColdFire processor. The processor HAL still has the ability to
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// override any of the settings to cope with differences between
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// its processor and the 5282, with a small risk that device drivers
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// are tied too closely to the 5282 implementation and need extra
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// effort. The processor HAL also has to supply some information that
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// is inherently too processor-specific, e.g. interrupt assignments
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// and GPIO pin management.
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//
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// This header is #include'd by hal_io.h from the architectural HAL.
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// It then #include's proc_io.h for the first time, giving the processor
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// HAL a chance to define symbols such as:
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//
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// HAL_MCFxxxx_HAS_MCF5282_WD
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// HAL_MCFxxxx_WD_BASE
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// HAL_MCFxxxx_HAS_MCF5282_ETH
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// HAL_MCFxxxx_ETH0_BASE
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//
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// The value of HAS_MCF5282_<module> corresponds to the number of
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// devices. The _BASE symbols correspond to the absolute base
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// addresses, e.g. (IPSBAR+0x0C00). For singleton devices there will
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// be only a single base addresses, otherwise separate base addresses
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// should be supplied for each device instance.
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//
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// Once the processor HAL has defined which mcf5282-compatible devices
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// are present, this header file provides the appropriate I/O
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// definitions. proc_io.h is then #include'd again so that it can undo
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// some of these definitions, e.g. when some h/w functionality
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// available on the 5282 is not present, or to extend the definitions
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// if a device offers more than functionality than the 5282
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// equivalent. Definitions for devices not present on a 5282 can be
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// provided by either the first or second pass of proc_io.h. Finally
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// proc_io.h will include plf_io.h, allowing platform-specific code to
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// override some of the definitions or to provide additional ones for
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// off-chip devices.
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//
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// During the second pass through proc_io.h, if a processor HAL
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// #undef's a var_io.h definition then that can cause problems with
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// device driver portability. There is no perfect way to handle that,
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// if h/w is not 100% compatible then device drivers will struggle.
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// Additional symbols will typically not be used by device drivers so
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// do not cause any portability problems, but eCos will not exploit
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// the extra functionality either.
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//
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// Symbols take the form:
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// HAL_MCFxxxx_<module>_<register>
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// HAL_MCFxxxx_<module>x_<register>
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// HAL_MCFxxxx_<module>_<register>_<field>
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// HAL_MCFxxxx_<module>x_<register>_<field>
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//
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// The x version is used when there may be multiple instances of a
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// given device, e.g. multiple UARTs or multiple interrupt
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// controllers.
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// First read in the processor-specific header so we know which
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// peripherals are common. The header will be read in again at
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// the end to allow the processor HAL to override some of the
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// settings defined here.
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#include <cyg/hal/proc_io.h>
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// ----------------------------------------------------------------------------
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// System registers. Note that these are not memory-mapped, they are
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// accessed via the movec instruction.
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// The cache control register and the access control registers
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// go together.
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#ifdef HAL_MCFxxxx_HAS_MCF5282_CACR_ACR
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# define HAL_MCFxxxx_CACR 0x0002
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# define HAL_MCFxxxx_CACR_CENB (0x01 << 31)
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# define HAL_MCFxxxx_CACR_CPD (0x01 << 28)
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# define HAL_MCFxxxx_CACR_CPDI (0x01 << 28)
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# define HAL_MCFxxxx_CACR_CFRZ (0x01 << 27)
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# define HAL_MCFxxxx_CACR_CINV (0x01 << 24)
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# define HAL_MCFxxxx_CACR_DISI (0x01 << 23)
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# define HAL_MCFxxxx_CACR_DISD (0x01 << 22)
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# define HAL_MCFxxxx_CACR_INVI (0x01 << 21)
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# define HAL_MCFxxxx_CACR_INVD (0x01 << 20)
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# define HAL_MCFxxxx_CACR_CEIB (0x01 << 10)
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# define HAL_MCFxxxx_CACR_DCM (0x01 << 9)
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# define HAL_MCFxxxx_CACR_DBWE (0x01 << 8)
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# define HAL_MCFxxxx_CACR_DWP (0x01 << 5)
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# define HAL_MCFxxxx_CACR_EUSP (0x01 << 4)
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# define HAL_MCFxxxx_CACR_CLNF_MASK (0x03 << 0)
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# define HAL_MCFxxxx_CACR_CLNF_SHIFT 0
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// The two access control registers. These provide some control
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// over external memory accesses.
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# define HAL_MCFxxxx_ACR0 0x0004
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# define HAL_MCFxxxx_ACR1 0x0005
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# define HAL_MCFxxxx_ACRx_AB_MASK (0x00FF << 24)
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# define HAL_MCFxxxx_ACRx_AB_SHIFT 24
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# define HAL_MCFxxxx_ACRx_AM_MASK (0x00FF << 16)
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# define HAL_MCFxxxx_ACRx_AM_SHIFT 16
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# define HAL_MCFxxxx_ACRx_EN (0x01 << 15)
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# define HAL_MCFxxxx_ACRx_SM_MASK (0x03 << 13)
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# define HAL_MCFxxxx_ACRx_SM_SHIFT 13
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# define HAL_MCFxxxx_ACRx_SM_USER_ONLY (0x00 << 13)
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# define HAL_MCFxxxx_ACRx_SM_SUPERVISOR_ONLY (0x01 << 13)
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# define HAL_MCFxxxx_ACRx_SM_ALWAYS (0x02 << 13)
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# define HAL_MCFxxxx_ACRx_CM (0x01 << 6)
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# define HAL_MCFxxxx_ACRx_BUFW (0x01 << 5)
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# define HAL_MCFxxxx_ACRx_BWE (0x01 << 5)
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# define HAL_MCFxxxx_ACRx_WP (0x01 << 2)
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#endif // HAL_MCFxxxx_HAS_MCF5282_CACR_ACR
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#ifdef HAL_MCFxxxx_HAS_MCF5282_RAMBAR
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# define HAL_MCFxxxx_RAMBAR 0x0C05
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# define HAL_MCFxxxx_RAMBAR_BA_MASK (0x00FFFF0000 << 0)
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# define HAL_MCFxxxx_RAMBAR_BA_SHIFT 0
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# define HAL_MCFxxxx_RAMBAR_PRI_MASK (0x03 << 10)
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# define HAL_MCFxxxx_RAMBAR_PRI_SHIFT 10
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# define HAL_MCFxxxx_RAMBAR_PRI_CPU_CPU (0x03 << 10)
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# define HAL_MCFxxxx_RAMBAR_PRI_CPU_DMA (0x02 << 10)
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# define HAL_MCFxxxx_RAMBAR_PRI_DMA_CPU (0x01 << 10)
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# define HAL_MCFxxxx_RAMBAR_PRI_DMA_DMA (0x00 << 10)
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# define HAL_MCFxxxx_RAMBAR_SPV (0x01 << 9)
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# define HAL_MCFxxxx_RAMBAR_WP (0x01 << 8)
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# define HAL_MCFxxxx_RAMBAR_CI (0x01 << 5)
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# define HAL_MCFxxxx_RAMBAR_SC (0x01 << 4)
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# define HAL_MCFxxxx_RAMBAR_SD (0x01 << 3)
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# define HAL_MCFxxxx_RAMBAR_UC (0x01 << 2)
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# define HAL_MCFxxxx_RAMBAR_UD (0x01 << 1)
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# define HAL_MCFxxxx_RAMBAR_V (0x01 << 0)
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#endif
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#ifdef HAL_MCFxxxx_HAS_MCF5282_FLASHBAR
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# define HAL_MCFxxxx_FLASHBAR 0x0C04
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# define HAL_MCFxxxx_FLASHBAR_BA_MASK (0x00FFF80000 << 0)
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# define HAL_MCFxxxx_FLASHBAR_BA_SHIFT 0
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# define HAL_MCFxxxx_FLASHBAR_WP (0x01 << 8)
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# define HAL_MCFxxxx_FLASHBAR_CI (0x01 << 5)
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# define HAL_MCFxxxx_FLASHBAR_SC (0x01 << 4)
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# define HAL_MCFxxxx_FLASHBAR_SD (0x01 << 3)
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# define HAL_MCFxxxx_FLASHBAR_UC (0x01 << 2)
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# define HAL_MCFxxxx_FLASHBAR_UD (0x01 << 1)
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# define HAL_MCFxxxx_FLASHBAR_V (0x01 << 0)
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#endif
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#ifdef HAL_MCFxxxx_HAS_MCF5282_VBR
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# define HAL_MCFxxxx_VBR 0x0801
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#endif
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// ----------------------------------------------------------------------------
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// SCM. For convenience this encapsulates the SCM system control
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// module, the PMM power management module, the CCM chip configuration
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// module, and the CLOCK clock module. These are interrelated in
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// various ways, so are likely to be all present or all absent.
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#ifdef HAL_MCFxxxx_HAS_MCF5282_SCM_PMM_CLOCK_CCM
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// IPSBAR, 32 bits, controls the base address of the on-chip
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// peripherals. This is equivalent to the MBAR register on other
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// processors, but is only accessible via IPSBAR rather than as a
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// control register. This is a bit strange - in theory IPSBAR could be
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// disabled, making it inaccessible without a reset.
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# define HAL_MCFxxxx_SCM_IPSBAR 0x00000000
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// RAMBAR, 32 bits. In practise this should always be a copy of the
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// control register, or rather of the bits that are supported in the SCM.
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# define HAL_MCFxxxx_SCM_RAMBAR 0x00000008
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// Core reset status register, 8 bits.
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# define HAL_MCFxxxx_SCM_CRSR 0x00000010
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// Core watchdog control register, 8 bits.
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# define HAL_MCFxxxx_SCM_CWCR 0x00000011
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// Core watchdog service register, 8 bits
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# define HAL_MCFxxxx_SCM_CWSR 0x00000013
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// Bus master park register, 32 bits
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# define HAL_MCFxxxx_SCM_MPARK 0x0000001C
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// Master privilege register, 8 bits
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# define HAL_MCFxxxx_SCM_MPR 0x00000020
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// The access control registers, 9 * 8 bits.
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# define HAL_MCFxxxx_SCM_PACR0 0x00000024
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# define HAL_MCFxxxx_SCM_PACR1 0x00000025
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# define HAL_MCFxxxx_SCM_PACR2 0x00000026
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# define HAL_MCFxxxx_SCM_PACR3 0x00000027
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# define HAL_MCFxxxx_SCM_PACR4 0x00000028
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# define HAL_MCFxxxx_SCM_PACR5 0x0000002A
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# define HAL_MCFxxxx_SCM_PACR6 0x0000002B
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# define HAL_MCFxxxx_SCM_PACR7 0x0000002C
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# define HAL_MCFxxxx_SCM_PACR8 0x0000002E
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# define HAL_MCFxxxx_SCM_GPACR0 0x00000030
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# define HAL_MCFxxxx_SCM_GPACR1 0x00000031
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# define HAL_MCFxxxx_SCM_IPSBAR_BA_MASK 0xC0000000
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# define HAL_MCFxxxx_SCM_IPSBAR_BA_SHIFT 30
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# define HAL_MCFxxxx_SCM_IPSBAR_V (0x01 << 0)
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# define HAL_MCFxxxx_SCM_RAMBAR_BA_MASK (0x00FFFF << 16)
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# define HAL_MCFxxxx_SCM_RAMBAR_BA_SHIFT 16
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# define HAL_MCFxxxx_SCM_RAMBAR_BDE (0x01 << 9)
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# define HAL_MCFxxxx_SCM_CRSR_EXT (0x01 << 7)
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# define HAL_MCFxxxx_SCM_CRSR_CWDR (0x01 << 5)
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# define HAL_MCFxxxx_SCM_CWCR_CWE (0x01 << 7)
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# define HAL_MCFxxxx_SCM_CWCR_CWRI (0x01 << 6)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_MASK (0x07 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_SHIFT 3
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_9 (0x00 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_11 (0x01 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_13 (0x02 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_15 (0x03 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_19 (0x04 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_23 (0x05 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_27 (0x06 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWT_2_31 (0x07 << 3)
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# define HAL_MCFxxxx_SCM_CWCR_CWTA (0x01 << 2)
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# define HAL_MCFxxxx_SCM_CWCR_CWTAVAL (0x01 << 1)
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# define HAL_MCFxxxx_SCM_CWCR_CWTIF (0x01 << 0)
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// The magic values that should be written to the watchdog service register
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# define HAL_MCFxxxx_SCM_CWSR_MAGIC0 0x0055
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# define HAL_MCFxxxx_SCM_CWSR_MAGIC1 0x00AA
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// Bus master parking. M3 is ethernet, M2 is DMA, M1 is internal,
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// M0 is the ColdFire core.
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# define HAL_MCFxxxx_SCM_MPARK_M2_P_EN (0x01 << 25)
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# define HAL_MCFxxxx_SCM_MPARK_BCR24BIT (0x01 << 24)
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# define HAL_MCFxxxx_SCM_MPARK_M3_PRTY_MASK (0x03 << 22)
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# define HAL_MCFxxxx_SCM_MPARK_M3_PRTY_SHIFT 22
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# define HAL_MCFxxxx_SCM_MPARK_M2_PRTY_MASK (0x03 << 20)
|
| 274 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_M2_PRTY_SHIFT 20
|
| 275 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_M0_PRTY_MASK (0x03 << 18)
|
| 276 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_M0_PRTY_SHIFT 18
|
| 277 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_M1_PRTY_MASK (0x03 << 16)
|
| 278 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_M1_PRTY_SHIFT 16
|
| 279 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_FIXED (0x01 << 14)
|
| 280 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_TIMEOUT (0x01 << 13)
|
| 281 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_PRKLAST (0x01 << 12)
|
| 282 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_LCKOUT_TIME_MASK (0x0F << 8)
|
| 283 |
|
|
# define HAL_MCFxxxx_SCM_MPARK_LCKOUT_TIME_SHIFT 8
|
| 284 |
|
|
|
| 285 |
|
|
# define HAL_MCFxxxx_SCM_MPR_M3 (0x01 << 3)
|
| 286 |
|
|
# define HAL_MCFxxxx_SCM_MPR_M2 (0x01 << 2)
|
| 287 |
|
|
# define HAL_MCFxxxx_SCM_MPR_M1 (0x01 << 1)
|
| 288 |
|
|
# define HAL_MCFxxxx_SCM_MPR_M0 (0x01 << 0)
|
| 289 |
|
|
|
| 290 |
|
|
// Each access control register is split into two nibbles
|
| 291 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_LOCK1 (0x01 << 7)
|
| 292 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL1_MASK (0x07 << 4)
|
| 293 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL1_SHIFT 4
|
| 294 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_LOCK0 (0x01 << 3)
|
| 295 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL0_MASK (0x07 << 0)
|
| 296 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_CTRL0_SHIFT 0
|
| 297 |
|
|
|
| 298 |
|
|
// The access granted. Separated into supervisor and user.
|
| 299 |
|
|
// R for read access, W for write access, N for no-access.
|
| 300 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_RW 0x04
|
| 301 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_R 0x05
|
| 302 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_RW_N 0x00
|
| 303 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_R_R 0x02
|
| 304 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_R_N 0x01
|
| 305 |
|
|
# define HAL_MCFxxxx_SCM_PACRx_ACCESS_N_N 0x07
|
| 306 |
|
|
|
| 307 |
|
|
// Exactly which PACR nibbles control which on-chip peripherals
|
| 308 |
|
|
// is a processor property so defined in proc_io.h
|
| 309 |
|
|
|
| 310 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_LOCK (0x01 << 7)
|
| 311 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_ACCESS_CTRL_MASK (0x0F << 0)
|
| 312 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_ACCESS_CTRL_SHIFT 0
|
| 313 |
|
|
|
| 314 |
|
|
// Read/Write/eXecute/No access in supervisor and user modes
|
| 315 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RW_N 0x00
|
| 316 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_R_N 0x01
|
| 317 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_R_R 0x02
|
| 318 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RW_RW 0x04
|
| 319 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RW_R 0x05
|
| 320 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_N_N 0x07
|
| 321 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RWX_N 0x08
|
| 322 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RX_N 0x09
|
| 323 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RX_RX 0x0A
|
| 324 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_X_N 0x0B
|
| 325 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RWX_RWX 0x0C
|
| 326 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RWX_RX 0x0D
|
| 327 |
|
|
# define HAL_MCFxxxx_SCM_GPACR_RWX_X 0x0F
|
| 328 |
|
|
|
| 329 |
|
|
// Power management. This can get confusing because there is an
|
| 330 |
|
|
// overlap with the chip configuration module, the reset module, and
|
| 331 |
|
|
// the system controller module. There are two registers, one in the
|
| 332 |
|
|
// SCM part of the address space, the other in the reset
|
| 333 |
|
|
// controller/chip configuration. Assume a single device.
|
| 334 |
|
|
|
| 335 |
|
|
// 8-bit interrupt control register
|
| 336 |
|
|
# define HAL_MCFxxxx_PMM_LPICR 0x00000012
|
| 337 |
|
|
// 8-bit control register.
|
| 338 |
|
|
# define HAL_MCFxxxx_PMM_LPCR 0x00110007
|
| 339 |
|
|
|
| 340 |
|
|
# define HAL_MCFxxxx_PMM_LPICR_ENBSTOP (0x01 << 7)
|
| 341 |
|
|
# define HAL_MCFxxxx_PMM_LPICR_XLPM_IPL_MASK (0x07 << 4)
|
| 342 |
|
|
# define HAL_MCFxxxx_PMM_LPICR_XLPM_IPL_SHIFT 4
|
| 343 |
|
|
|
| 344 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_LPMD_MASK (0x03 << 6)
|
| 345 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_LPMD_SHIFT 6
|
| 346 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_LPMD_STOP (0x03 << 6)
|
| 347 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_LPMD_WAIT (0x02 << 6)
|
| 348 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_LPMD_DOZE (0x01 << 6)
|
| 349 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_LPMD_RUN (0x00 << 6)
|
| 350 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_STPMD_MASK (0x03 << 3)
|
| 351 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_STPMD_SHIFT 3
|
| 352 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_STPMD_CLKOUT_PLL_OSC_PMM (0x00 << 3)
|
| 353 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_STPMD_PLL_OSC_PMM (0x01 << 3)
|
| 354 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_STPMD_OSC_PMM (0x02 << 3)
|
| 355 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_STPMD_PMM (0x03 << 3)
|
| 356 |
|
|
# define HAL_MCFxxxx_PMM_LPCR_LVDSE (0x01 << 1)
|
| 357 |
|
|
|
| 358 |
|
|
// The clock module. Assume a single device.
|
| 359 |
|
|
// Synthesizer control register, 16 bits
|
| 360 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR 0x00120000
|
| 361 |
|
|
// Synthesizer status register, 8 bits
|
| 362 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNSR 0x00120002
|
| 363 |
|
|
|
| 364 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_LOLRE (0x01 << 15)
|
| 365 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_MFD_MASK (0x07 << 12)
|
| 366 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_MFD_SHIFT 12
|
| 367 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_LOCRE (0x01 << 11)
|
| 368 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_RFD_MASK (0x07 << 8)
|
| 369 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_RFD_SHIFT 8
|
| 370 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_LOCEN (0x01 << 7)
|
| 371 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_DISCLK (0x01 << 6)
|
| 372 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_FWKUP (0x01 << 5)
|
| 373 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_STPMD_MASK (0x03 << 2)
|
| 374 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNCR_STPMD_SHIFT 2
|
| 375 |
|
|
|
| 376 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNSR_PLLMODE (0x01 << 7)
|
| 377 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNSR_PLLSEL (0x01 << 6)
|
| 378 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNSR_PLLREF (0x01 << 5)
|
| 379 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNSR_LOCKS (0x01 << 4)
|
| 380 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNSR_LOCK (0x01 << 3)
|
| 381 |
|
|
# define HAL_MCFxxxx_CLOCK_SYNSR_LOCS (0x01 << 2)
|
| 382 |
|
|
|
| 383 |
|
|
// Chip configuration module
|
| 384 |
|
|
// Four 16-bit registers: chip configuration, low-power control, reset
|
| 385 |
|
|
// configuration, and chip identification. LPCR is described in the
|
| 386 |
|
|
// power management section.
|
| 387 |
|
|
# define HAL_MCFxxxx_CCM_CCR 0x00110004
|
| 388 |
|
|
# define HAL_MCFxxxx_CCM_RCON 0x00110008
|
| 389 |
|
|
# define HAL_MCFxxxx_CCM_CIR 0x0011000A
|
| 390 |
|
|
|
| 391 |
|
|
# define HAL_MCFxxxx_CCM_CCR_LOAD (0x01 << 15)
|
| 392 |
|
|
# define HAL_MCFxxxx_CCM_CCR_MODE_MASK (0x07 << 8)
|
| 393 |
|
|
# define HAL_MCFxxxx_CCM_CCR_MODE_SHIFT 8
|
| 394 |
|
|
# define HAL_MCFxxxx_CCM_CCR_MODE_SINGLE_CHIP (0x06 << 8)
|
| 395 |
|
|
# define HAL_MCFxxxx_CCM_CCR_MODE_MASTER (0x07 << 8)
|
| 396 |
|
|
# define HAL_MCFxxxx_CCM_CCR_SZEN (0x01 << 6)
|
| 397 |
|
|
# define HAL_MCFxxxx_CCM_CCR_PSTEN (0x01 << 5)
|
| 398 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BME (0x01 << 3)
|
| 399 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_MASK (0x07 << 0)
|
| 400 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_SHIFT 0
|
| 401 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_65536 0x00
|
| 402 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_32768 0x01
|
| 403 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_16384 0x02
|
| 404 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_8192 0x03
|
| 405 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_4096 0x04
|
| 406 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_2048 0x05
|
| 407 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_1024 0x06
|
| 408 |
|
|
# define HAL_MCFxxxx_CCM_CCR_BMT_512 0x07
|
| 409 |
|
|
|
| 410 |
|
|
# define HAL_MCFxxxx_CCM_RCON_RCSC_MASK (0x03 << 8)
|
| 411 |
|
|
# define HAL_MCFxxxx_CCM_RCON_RCSC_SHIFT 8
|
| 412 |
|
|
# define HAL_MCFxxxx_CCM_RCON_RPLLSEL (0x01 << 7)
|
| 413 |
|
|
# define HAL_MCFxxxx_CCM_RCON_RPLLREF (0x01 << 6)
|
| 414 |
|
|
# define HAL_MCFxxxx_CCM_RCON_RLOAD (0x01 << 5)
|
| 415 |
|
|
# define HAL_MCFxxxx_CCM_RCON_BOOTPS_MASK (0x03 << 3)
|
| 416 |
|
|
# define HAL_MCFxxxx_CCM_RCON_BOOTPS_SHIFT 3
|
| 417 |
|
|
# define HAL_MCFxxxx_CCM_RCON_BOOTPS_INTERNAL (0x00 << 3)
|
| 418 |
|
|
# define HAL_MCFxxxx_CCM_RCON_BOOTPS_16 (0x01 << 3)
|
| 419 |
|
|
# define HAL_MCFxxxx_CCM_RCON_BOOTPS_8 (0x02 << 3)
|
| 420 |
|
|
# define HAL_MCFxxxx_CCM_RCON_BOOTPS_32 (0x03 << 3)
|
| 421 |
|
|
# define HAL_MCFxxxx_CCM_RCON_BOOTSEL (0x01 << 2)
|
| 422 |
|
|
# define HAL_MCFxxxx_CCM_RCON_MODE (0x01 << 0)
|
| 423 |
|
|
|
| 424 |
|
|
# define HAL_MCF5282_CCM_CIR_PIN_MASK (0x00FF << 8)
|
| 425 |
|
|
# define HAL_MCF5282_CCM_CIR_PIN_SHIFT 8
|
| 426 |
|
|
# define HAL_MCF5282_CCM_CIR_PRN_MASK (0x00FF << 0)
|
| 427 |
|
|
# define HAL_MCF5282_CCM_CIR_PRN_SHIFT 0
|
| 428 |
|
|
|
| 429 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_SCM_PMM_CLOCK_CCM
|
| 430 |
|
|
|
| 431 |
|
|
// ----------------------------------------------------------------------------
|
| 432 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_RST
|
| 433 |
|
|
// Reset controller
|
| 434 |
|
|
// Two 8-bit registers, reset control and reset status
|
| 435 |
|
|
# define HAL_MCFxxxx_RST_RCR 0x00000000
|
| 436 |
|
|
# define HAL_MCFxxxx_RST_RSR 0x00000001
|
| 437 |
|
|
|
| 438 |
|
|
# define HAL_MCFxxxx_RST_RCR_SOFTRST (0x01 << 7)
|
| 439 |
|
|
# define HAL_MCFxxxx_RST_RCR_FRCRSTOUT (0x01 << 6)
|
| 440 |
|
|
# define HAL_MCFxxxx_RST_RCR_LVDF (0x01 << 4)
|
| 441 |
|
|
# define HAL_MCFxxxx_RST_RCR_LVDIE (0x01 << 3)
|
| 442 |
|
|
# define HAL_MCFxxxx_RST_RCR_LVDRE (0x01 << 2)
|
| 443 |
|
|
# define HAL_MCFxxxx_RST_RCR_LVDE (0x01 << 0)
|
| 444 |
|
|
|
| 445 |
|
|
# define HAL_MCFxxxx_RST_RSR_LVD (0x01 << 6)
|
| 446 |
|
|
# define HAL_MCFxxxx_RST_RSR_SOFT (0x01 << 5)
|
| 447 |
|
|
# define HAL_MCFxxxx_RST_RSR_WDR (0x01 << 4)
|
| 448 |
|
|
# define HAL_MCFxxxx_RST_RSR_POR (0x01 << 3)
|
| 449 |
|
|
# define HAL_MCFxxxx_RST_RSR_EXT (0x01 << 2)
|
| 450 |
|
|
# define HAL_MCFxxxx_RST_RSR_LOC (0x01 << 1)
|
| 451 |
|
|
# define HAL_MCFxxxx_RST_RSR_LOL (0x01 << 0)
|
| 452 |
|
|
#endif
|
| 453 |
|
|
|
| 454 |
|
|
// ----------------------------------------------------------------------------
|
| 455 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_WD
|
| 456 |
|
|
// Watchdog timer. Only a single device.
|
| 457 |
|
|
// Four 16-bit registers: control, modulus, count and service
|
| 458 |
|
|
# define HAL_MCFxxxx_WD_WCR 0x00000000
|
| 459 |
|
|
# define HAL_MCFxxxx_WD_WMR 0x00000002
|
| 460 |
|
|
# define HAL_MCFxxxx_WD_WCNTR 0x00000004
|
| 461 |
|
|
# define HAL_MCFxxxx_WD_WSR 0x00000006
|
| 462 |
|
|
|
| 463 |
|
|
# define HAL_MCFxxxx_WD_WCR_WAIT (0x01 << 3)
|
| 464 |
|
|
# define HAL_MCFxxxx_WD_WCR_DOZE (0x01 << 2)
|
| 465 |
|
|
# define HAL_MCFxxxx_WD_WCR_HALTED (0x01 << 1)
|
| 466 |
|
|
# define HAL_MCFxxxx_WD_WCR_EN (0x01 << 0)
|
| 467 |
|
|
|
| 468 |
|
|
// The modulus and count registers are just 16 bits of counter data
|
| 469 |
|
|
// The magic numbers for the service register
|
| 470 |
|
|
# define HAL_MCF5282_WD_WSR_MAGIC0 0x5555
|
| 471 |
|
|
# define HAL_MCF5282_WD_WSR_MAGIC1 0xAAAA
|
| 472 |
|
|
|
| 473 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_WD
|
| 474 |
|
|
|
| 475 |
|
|
// ----------------------------------------------------------------------------
|
| 476 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_CS
|
| 477 |
|
|
// Chip select module. Assume a single device.
|
| 478 |
|
|
|
| 479 |
|
|
// Seven sets of registers, a 16-bit address register, a 32-bit
|
| 480 |
|
|
// mask register and a 16-bit control register
|
| 481 |
|
|
# define HAL_MCFxxxx_CS_CSAR0 0x00000080
|
| 482 |
|
|
# define HAL_MCFxxxx_CS_CSMR0 0x00000084
|
| 483 |
|
|
# define HAL_MCFxxxx_CS_CSCR0 0x0000008A
|
| 484 |
|
|
# define HAL_MCFxxxx_CS_CSAR1 0x0000008C
|
| 485 |
|
|
# define HAL_MCFxxxx_CS_CSMR1 0x00000090
|
| 486 |
|
|
# define HAL_MCFxxxx_CS_CSCR1 0x00000096
|
| 487 |
|
|
# define HAL_MCFxxxx_CS_CSAR2 0x00000098
|
| 488 |
|
|
# define HAL_MCFxxxx_CS_CSMR2 0x0000009C
|
| 489 |
|
|
# define HAL_MCFxxxx_CS_CSCR2 0x000000A2
|
| 490 |
|
|
# define HAL_MCFxxxx_CS_CSAR3 0x000000A4
|
| 491 |
|
|
# define HAL_MCFxxxx_CS_CSMR3 0x000000A8
|
| 492 |
|
|
# define HAL_MCFxxxx_CS_CSCR3 0x000000AE
|
| 493 |
|
|
# define HAL_MCFxxxx_CS_CSAR4 0x000000B0
|
| 494 |
|
|
# define HAL_MCFxxxx_CS_CSMR4 0x000000B4
|
| 495 |
|
|
# define HAL_MCFxxxx_CS_CSCR4 0x000000BA
|
| 496 |
|
|
# define HAL_MCFxxxx_CS_CSAR5 0x000000BC
|
| 497 |
|
|
# define HAL_MCFxxxx_CS_CSMR5 0x000000C0
|
| 498 |
|
|
# define HAL_MCFxxxx_CS_CSCR5 0x000000C6
|
| 499 |
|
|
# define HAL_MCFxxxx_CS_CSAR6 0x000000C8
|
| 500 |
|
|
# define HAL_MCFxxxx_CS_CSMR6 0x000000CC
|
| 501 |
|
|
# define HAL_MCFxxxx_CS_CSCR6 0x000000D2
|
| 502 |
|
|
|
| 503 |
|
|
// The address register is just the top 16 bits of the address.
|
| 504 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_BAM_MASK (0x00FFFF << 16)
|
| 505 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_BAM_SHIFT 16
|
| 506 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_WP (0x01 << 8)
|
| 507 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_AM (0x01 << 6)
|
| 508 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_CI (0x01 << 5)
|
| 509 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_SC (0x01 << 4)
|
| 510 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_SD (0x01 << 3)
|
| 511 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_UC (0x01 << 2)
|
| 512 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_UD (0x01 << 1)
|
| 513 |
|
|
# define HAL_MCFxxxx_CS_CSMRx_V (0x01 << 0)
|
| 514 |
|
|
|
| 515 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_WS_MASK (0x000F << 10)
|
| 516 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_WS_SHIFT 10
|
| 517 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_AA (0x01 << 8)
|
| 518 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_PS_MASK (0x03 << 6)
|
| 519 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_PS_SHIFT 6
|
| 520 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_PS_32 (0x00 << 6)
|
| 521 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_PS_8 (0x01 << 6)
|
| 522 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_PS_16 (0x02 << 6)
|
| 523 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_BEM (0x01 << 5)
|
| 524 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_BSTR (0x01 << 4)
|
| 525 |
|
|
# define HAL_MCFxxxx_CS_CSCRx_BSTW (0x01 << 3)
|
| 526 |
|
|
|
| 527 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_CS
|
| 528 |
|
|
|
| 529 |
|
|
// ----------------------------------------------------------------------------
|
| 530 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_SDRAMC
|
| 531 |
|
|
// SDRAM controller. Assume a single device.
|
| 532 |
|
|
|
| 533 |
|
|
// A 16-bit overall control register
|
| 534 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR 0x00000040
|
| 535 |
|
|
// Two sets of two 32-bit registers
|
| 536 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACR0 0x00000048
|
| 537 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMR0 0x0000004C
|
| 538 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACR1 0x00000050
|
| 539 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMR1 0x00000054
|
| 540 |
|
|
|
| 541 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR_NAM (0x01 << 13)
|
| 542 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR_COC (0x01 << 12)
|
| 543 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR_IS (0x01 << 11)
|
| 544 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR_RTIM_MASK (0x03 << 9)
|
| 545 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR_RTIM_SHIFT 9
|
| 546 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR_RC_MASK (0x01FF << 0)
|
| 547 |
|
|
# define HAL_MCFxxxx_SDRAMC_DCR_RC_SHIFT 0
|
| 548 |
|
|
|
| 549 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_BA_MASK (0x03FFF << 18)
|
| 550 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_BA_SHIFT 18
|
| 551 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_RE (0x01 << 15)
|
| 552 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CASL_MASK (0x03 << 12)
|
| 553 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CASL_SHIFT 12
|
| 554 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_MASK (0x07 << 8)
|
| 555 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_SHIFT 8
|
| 556 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_17 (0x00 << 8)
|
| 557 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_18 (0x01 << 8)
|
| 558 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_19 (0x02 << 8)
|
| 559 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_20 (0x03 << 8)
|
| 560 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_21 (0x04 << 8)
|
| 561 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_22 (0x05 << 8)
|
| 562 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_23 (0x06 << 8)
|
| 563 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_CBM_24 (0x07 << 8)
|
| 564 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_IMRS (0x01 << 6)
|
| 565 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_PS_MASK (0x03 << 4)
|
| 566 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_PS_SHIFT 4
|
| 567 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_PS_32 (0x00 << 4)
|
| 568 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_PS_8 (0x01 << 4)
|
| 569 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_PS_16 (0x02 << 4)
|
| 570 |
|
|
# define HAL_MCFxxxx_SDRAMC_DACRx_IP (0x01 << 3)
|
| 571 |
|
|
|
| 572 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_BA_MASK (0x03FFF << 18)
|
| 573 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_BA_SHIFT 18
|
| 574 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_WP (0x01 << 8)
|
| 575 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_CI (0x01 << 6)
|
| 576 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_AM (0x01 << 5)
|
| 577 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_SC (0x01 << 4)
|
| 578 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_SD (0x01 << 3)
|
| 579 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_UC (0x01 << 2)
|
| 580 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_UD (0x01 << 1)
|
| 581 |
|
|
# define HAL_MCFxxxx_SDRAMC_DMRx_V (0x01 << 0)
|
| 582 |
|
|
|
| 583 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_SDRAMC
|
| 584 |
|
|
|
| 585 |
|
|
// ----------------------------------------------------------------------------
|
| 586 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_CFM
|
| 587 |
|
|
|
| 588 |
|
|
// The CFM module - on-chip flash. Assume a single device.
|
| 589 |
|
|
// Configuration register, 16 bits.
|
| 590 |
|
|
# define HAL_MCFxxxx_CFM_CR 0x0000
|
| 591 |
|
|
// Clock divider register, 8 bits.
|
| 592 |
|
|
# define HAL_MCFxxxx_CFM_CLKD 0x0002
|
| 593 |
|
|
// Security register, 32 bits
|
| 594 |
|
|
# define HAL_MCFxxxx_CFM_SEC 0x0008
|
| 595 |
|
|
// Protection register, 32 bits
|
| 596 |
|
|
# define HAL_MCFxxxx_CFM_PROT 0x0010
|
| 597 |
|
|
// Supervisor access register, 32 bits
|
| 598 |
|
|
# define HAL_MCFxxxx_CFM_SACC 0x0014
|
| 599 |
|
|
// Data access register, 32 bits
|
| 600 |
|
|
# define HAL_MCFxxxx_CFM_DACC 0x0018
|
| 601 |
|
|
// User status register, 8 bits
|
| 602 |
|
|
# define HAL_MCFxxxx_CFM_USTAT 0x0020
|
| 603 |
|
|
// Command register, 8 bits
|
| 604 |
|
|
# define HAL_MCFxxxx_CFM_CMD 0x0024
|
| 605 |
|
|
|
| 606 |
|
|
# define HAL_MCFxxxx_CFM_CR_LOCK (0x01 << 10)
|
| 607 |
|
|
# define HAL_MCFxxxx_CFM_CR_PVIE (0x01 << 9)
|
| 608 |
|
|
# define HAL_MCFxxxx_CFM_CR_AEIE (0x01 << 8)
|
| 609 |
|
|
# define HAL_MCFxxxx_CFM_CR_CBEIE (0x01 << 7)
|
| 610 |
|
|
# define HAL_MCFxxxx_CFM_CR_CCIE (0x01 << 6)
|
| 611 |
|
|
# define HAL_MCFxxxx_CFM_CR_KEYACC (0x01 << 5)
|
| 612 |
|
|
|
| 613 |
|
|
# define HAL_MCFxxxx_CFM_CLKD_DIVLD (0x01 << 7)
|
| 614 |
|
|
# define HAL_MCFxxxx_CFM_CLKD_PRDIV8 (0x01 << 6)
|
| 615 |
|
|
# define HAL_MCFxxxx_CFM_CLKD_DIV_MASK (0x3F << 0)
|
| 616 |
|
|
# define HAL_MCFxxxx_CFM_CLKD_DIV_SHIFT 0
|
| 617 |
|
|
|
| 618 |
|
|
# define HAL_MCFxxxx_CFM_SEC_KEYEN (0x01 << 31)
|
| 619 |
|
|
# define HAL_MCFxxxx_CFM_SEC_SECSTAT (0x01 << 30)
|
| 620 |
|
|
# define HAL_MCFxxxx_CFM_SEC_SEC_MASK (0x0FFFF << 0)
|
| 621 |
|
|
# define HAL_MCFxxxx_CFM_SEC_SEC_SHIFT 0
|
| 622 |
|
|
# define HAL_MCFxxxx_CFM_SEC_SEC_MAGIC 0x4AC8
|
| 623 |
|
|
|
| 624 |
|
|
// The PROT protection register is just 32 bits, each bit protecting
|
| 625 |
|
|
// one flash sector. 0 means not protected.
|
| 626 |
|
|
|
| 627 |
|
|
// The SACC supervisor access register similarly is 32 bits controlling
|
| 628 |
|
|
// access to the flash. 0 allows access in both user and supervisor modes.
|
| 629 |
|
|
|
| 630 |
|
|
// The DACC data access register is 32 bits determining whether or not
|
| 631 |
|
|
// each sector can contain code. 0 means code is possible.
|
| 632 |
|
|
|
| 633 |
|
|
# define HAL_MCFxxxx_CFM_USTAT_CBEIF (0x01 << 7)
|
| 634 |
|
|
# define HAL_MCFxxxx_CFM_USTAT_CCIF (0x01 << 6)
|
| 635 |
|
|
# define HAL_MCFxxxx_CFM_USTAT_PVIOL (0x01 << 5)
|
| 636 |
|
|
# define HAL_MCFxxxx_CFM_USTAT_ACCERR (0x01 << 4)
|
| 637 |
|
|
# define HAL_MCFxxxx_CFM_USTAT_BLANK (0x01 << 2)
|
| 638 |
|
|
|
| 639 |
|
|
# define HAL_MCFxxxx_CFM_CMD_RDARY1 0x05
|
| 640 |
|
|
# define HAL_MCFxxxx_CFM_CMD_PGERSVER 0x06
|
| 641 |
|
|
# define HAL_MCFxxxx_CFM_CMD_PGM 0x20
|
| 642 |
|
|
# define HAL_MCFxxxx_CFM_CMD_PGERS 0x40
|
| 643 |
|
|
# define HAL_MCFxxxx_CFM_CMD_MASERS 0x41
|
| 644 |
|
|
|
| 645 |
|
|
# if !defined(__ASSEMBLER__) && !defined(__LDI__)
|
| 646 |
|
|
// On reset some of the CFM settings are initialized from a structure
|
| 647 |
|
|
// @ offset 0x00000400 in the flash. When booting from the internal
|
| 648 |
|
|
// flash the FLASHBAR register is initialized to address 0, read-only
|
| 649 |
|
|
// and valid. Presumably it is expected that the first 1K will be
|
| 650 |
|
|
// filled with exception vectors, so the next 24 bytes are used for
|
| 651 |
|
|
// flash settings. Real code can follow afterwards.
|
| 652 |
|
|
typedef struct hal_mcfxxxx_cfm_security_settings {
|
| 653 |
|
|
cyg_uint64 cfm_backdoor_key;
|
| 654 |
|
|
cyg_uint32 cfm_prot;
|
| 655 |
|
|
cyg_uint32 cfm_sacc;
|
| 656 |
|
|
cyg_uint32 cfm_dacc;
|
| 657 |
|
|
cyg_uint32 cfm_sec;
|
| 658 |
|
|
} hal_mcfxxxx_cfm_security_settings;
|
| 659 |
|
|
# endif
|
| 660 |
|
|
|
| 661 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_CFM
|
| 662 |
|
|
|
| 663 |
|
|
// ----------------------------------------------------------------------------
|
| 664 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_INTC
|
| 665 |
|
|
// Support one or more INTC controllers, depending on the number of
|
| 666 |
|
|
// interrup sources.
|
| 667 |
|
|
|
| 668 |
|
|
// Two 32-bit interrupt pending registers
|
| 669 |
|
|
# define HAL_MCFxxxx_INTCx_IPRH 0x0000
|
| 670 |
|
|
# define HAL_MCFxxxx_INTCx_IPRL 0x0004
|
| 671 |
|
|
// Two 32-bit interrupt mask registers
|
| 672 |
|
|
# define HAL_MCFxxxx_INTCx_IMRH 0x0008
|
| 673 |
|
|
# define HAL_MCFxxxx_INTCx_IMRL 0x000C
|
| 674 |
|
|
// Two 32-bit interrupt force registers
|
| 675 |
|
|
# define HAL_MCFxxxx_INTCx_INTFRCH 0x0010
|
| 676 |
|
|
# define HAL_MCFxxxx_INTCx_INTFRCL 0x0014
|
| 677 |
|
|
// 8-bit interrupt request level register
|
| 678 |
|
|
# define HAL_MCFxxxx_INTCx_IRLR 0x0018
|
| 679 |
|
|
// 8-bit interrupt acknowledge level/priority register
|
| 680 |
|
|
# define HAL_MCFxxxx_INTCx_IACKLPR 0x0019
|
| 681 |
|
|
// 64 8-bit interrupt control registers, determining the priorities
|
| 682 |
|
|
// of each interrupt source. ICR00 is actually invalid but useful for
|
| 683 |
|
|
// array indexing.
|
| 684 |
|
|
# define HAL_MCFxxxx_INTCx_ICR00 0x0040
|
| 685 |
|
|
// 8-bit ACK registers. These can be checked in an interrupt handler
|
| 686 |
|
|
// to chain, avoiding the overheads of another interrupt, but at
|
| 687 |
|
|
// the cost of a couple of extra cycles even when no other interrupts
|
| 688 |
|
|
// are pending. Unless the interrupt load is very heavy this is
|
| 689 |
|
|
// likely to be a bad trade off.
|
| 690 |
|
|
# define HAL_MCFxxxx_INTCx_SWIACK 0x00E0
|
| 691 |
|
|
# define HAL_MCFxxxx_INTCx_L1IACK 0x00E4
|
| 692 |
|
|
# define HAL_MCFxxxx_INTCx_L2IACK 0x00E8
|
| 693 |
|
|
# define HAL_MCFxxxx_INTCx_L3IACK 0x00EC
|
| 694 |
|
|
# define HAL_MCFxxxx_INTCx_L4IACK 0x00F0
|
| 695 |
|
|
# define HAL_MCFxxxx_INTCx_L5IACK 0x00F4
|
| 696 |
|
|
# define HAL_MCFxxxx_INTCx_L6IACK 0x00F8
|
| 697 |
|
|
# define HAL_MCFxxxx_INTCx_L7IACK 0x00FC
|
| 698 |
|
|
|
| 699 |
|
|
// Global IACK registers, all 8-bits
|
| 700 |
|
|
# define HAL_MCFxxxx_INTC_GSWACKR 0x0FE0
|
| 701 |
|
|
# define HAL_MCFxxxx_INTC_GL1IACKR 0x0FE4
|
| 702 |
|
|
# define HAL_MCFxxxx_INTC_GL2IACKR 0x0FE8
|
| 703 |
|
|
# define HAL_MCFxxxx_INTC_GL3IACKR 0x0FEC
|
| 704 |
|
|
# define HAL_MCFxxxx_INTC_GL4IACKR 0x0FF0
|
| 705 |
|
|
# define HAL_MCFxxxx_INTC_GL5IACKR 0x0FF4
|
| 706 |
|
|
# define HAL_MCFxxxx_INTC_GL6IACKR 0x0FF8
|
| 707 |
|
|
# define HAL_MCFxxxx_INTC_GL7IACKR 0x0FFC
|
| 708 |
|
|
|
| 709 |
|
|
// The pending, mask and force registers are just 32 bits with one bit
|
| 710 |
|
|
// per interrupt source.
|
| 711 |
|
|
//
|
| 712 |
|
|
// The IRLR registers is just 8 bits with one bit per interrupt
|
| 713 |
|
|
// priority level. Priority level 0 corresponds to no pending
|
| 714 |
|
|
// interrupts, of course.
|
| 715 |
|
|
|
| 716 |
|
|
# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_MASK (0x07 << 4)
|
| 717 |
|
|
# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_SHIFT 4
|
| 718 |
|
|
# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_PRI_MASK (0x0F << 0)
|
| 719 |
|
|
# define HAL_MCFxxxx_INTCx_IACKLPR_LEVEL_PRI_SHIFT 0
|
| 720 |
|
|
|
| 721 |
|
|
# define HAL_MCFxxxx_INTCx_ICRxx_IL_MASK (0x07 << 3)
|
| 722 |
|
|
# define HAL_MCFxxxx_INTCx_ICRxx_IL_SHIFT 3
|
| 723 |
|
|
# define HAL_MCFxxxx_INTCx_ICRxx_IP_MASK (0x07 << 0)
|
| 724 |
|
|
# define HAL_MCFxxxx_INTCx_ICRxx_IP_SHIFT 0
|
| 725 |
|
|
|
| 726 |
|
|
# ifdef HAL_MCFxxxx_HAS_INTC_SIMCIMETC
|
| 727 |
|
|
# undef HAL_MCFxxxx_INTCx_IACKLPR
|
| 728 |
|
|
# define HAL_MCFxxxx_INTCx_ICONFIG 0x0000001A
|
| 729 |
|
|
# define HAL_MCFxxxx_INTCx_SIMR 0x0000001C
|
| 730 |
|
|
# define HAL_MCFxxxx_INTCx_CIMR 0x0000001D
|
| 731 |
|
|
# define HAL_MCFxxxx_INTCx_CLMASK 0x0000001E
|
| 732 |
|
|
# define HAL_MCFxxxx_INTCx_SLMASK 0x0000001F
|
| 733 |
|
|
|
| 734 |
|
|
# define HAL_MCFxxxx_INTCx_ICONFIG_ELVLPRI_MASK (0x7F << 9)
|
| 735 |
|
|
# define HAL_MCFxxxx_INTCx_ICONFIG_ELVLPRI_SHIFT 9
|
| 736 |
|
|
# define HAL_MCFxxxx_INTCx_ICONFIG_EMASK (0x01 << 5)
|
| 737 |
|
|
# endif
|
| 738 |
|
|
|
| 739 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_INTC
|
| 740 |
|
|
|
| 741 |
|
|
// ----------------------------------------------------------------------------
|
| 742 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_EPORT
|
| 743 |
|
|
// Edge port module, pins which can be configured to trigger interrupts.
|
| 744 |
|
|
|
| 745 |
|
|
// Pin assignment register, 16 bits
|
| 746 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR 0x0000
|
| 747 |
|
|
// Data direction register, 8 bits
|
| 748 |
|
|
# define HAL_MCFxxxx_EPORTx_EPDDR 0x0002
|
| 749 |
|
|
// Interrupt enable register, 8 bits
|
| 750 |
|
|
# define HAL_MCFxxxx_EPORTx_EPIER 0x0003
|
| 751 |
|
|
// Data register (output), 8 bits
|
| 752 |
|
|
# define HAL_MCFxxxx_EPORTx_EPDR 0x0004
|
| 753 |
|
|
// Pin data register (input), 8 bits
|
| 754 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPDR 0x0005
|
| 755 |
|
|
// Flag register
|
| 756 |
|
|
# define HAL_MCFxxxx_EPORTx_EPFR 0x0006
|
| 757 |
|
|
|
| 758 |
|
|
// EPPAR is split into 2 bits per pin, the others use 1 bit per pin
|
| 759 |
|
|
// with bit 0 unused.
|
| 760 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA7_MASK (0x03 << 14)
|
| 761 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA7_SHIFT 14
|
| 762 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA6_MASK (0x03 << 12)
|
| 763 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA6_SHIFT 12
|
| 764 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA5_MASK (0x03 << 10)
|
| 765 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA5_SHIFT 10
|
| 766 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA4_MASK (0x03 << 8)
|
| 767 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA4_SHIFT 8
|
| 768 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA3_MASK (0x03 << 6)
|
| 769 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA3_SHIFT 6
|
| 770 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA2_MASK (0x03 << 4)
|
| 771 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA2_SHIFT 4
|
| 772 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA1_MASK (0x03 << 2)
|
| 773 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA1_SHIFT 2
|
| 774 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA0_MASK (0x03 << 0)
|
| 775 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPA0_SHIFT 0
|
| 776 |
|
|
|
| 777 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_LEVEL 0x00
|
| 778 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_RISING 0x01
|
| 779 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_FALLING 0x02
|
| 780 |
|
|
# define HAL_MCFxxxx_EPORTx_EPPAR_EPPAx_BOTH 0x03
|
| 781 |
|
|
|
| 782 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_EPORT
|
| 783 |
|
|
|
| 784 |
|
|
// ----------------------------------------------------------------------------
|
| 785 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_DMA
|
| 786 |
|
|
// DMA. Support an arbitrary number of channels, although
|
| 787 |
|
|
// the DMA_REQC register effectively limits the number to 8.
|
| 788 |
|
|
|
| 789 |
|
|
// DMA request controller, 1 32-bit register. This is assumed relative
|
| 790 |
|
|
// to SCM. It is in addition to the per-channel register definitions.
|
| 791 |
|
|
# define HAL_MCFxxxx_DMA_REQC 0x00000014
|
| 792 |
|
|
|
| 793 |
|
|
#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 7)
|
| 794 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC7_MASK (0x0F << 28)
|
| 795 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC7_SHIFT 28
|
| 796 |
|
|
#endif
|
| 797 |
|
|
#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 6)
|
| 798 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC6_MASK (0x0F << 24)
|
| 799 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC6_SHIFT 24
|
| 800 |
|
|
#endif
|
| 801 |
|
|
#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 5)
|
| 802 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC5_MASK (0x0F << 20)
|
| 803 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC5_SHIFT 20
|
| 804 |
|
|
#endif
|
| 805 |
|
|
#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 4)
|
| 806 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC4_MASK (0x0F << 16)
|
| 807 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC4_SHIFT 16
|
| 808 |
|
|
#endif
|
| 809 |
|
|
#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 3)
|
| 810 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC3_MASK (0x0F << 12)
|
| 811 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC3_SHIFT 12
|
| 812 |
|
|
#endif
|
| 813 |
|
|
#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 2)
|
| 814 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC2_MASK (0x0F << 8)
|
| 815 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC2_SHIFT 8
|
| 816 |
|
|
#endif
|
| 817 |
|
|
#if (HAL_MCFxxxx_HAS_MCF5282_DMA > 1)
|
| 818 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC1_MASK (0x0F << 4)
|
| 819 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC1_SHIFT 4
|
| 820 |
|
|
#endif
|
| 821 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC0_MASK (0x0F << 0)
|
| 822 |
|
|
# define HAL_MCFxxxx_DMA_REQC_DMAC0_SHIFT 0
|
| 823 |
|
|
|
| 824 |
|
|
// Each DMA channel has 32-bit source, destination and control
|
| 825 |
|
|
// registers, a count register (up to 24 bits), and a 1-byte status
|
| 826 |
|
|
// register
|
| 827 |
|
|
# define HAL_MCFxxxx_DMAx_SARx 0x00000000
|
| 828 |
|
|
# define HAL_MCFxxxx_DMAx_DARx 0x00000004
|
| 829 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx 0x00000008
|
| 830 |
|
|
# define HAL_MCFxxxx_DMAx_BCRx 0x0000000C
|
| 831 |
|
|
# define HAL_MCFxxxx_DMAx_DSRx 0x00000010
|
| 832 |
|
|
|
| 833 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_INT (0x01 << 31)
|
| 834 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_EEXT (0x01 << 30)
|
| 835 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_CS (0x01 << 29)
|
| 836 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_AA (0x01 << 28)
|
| 837 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_MASK (0x07 << 25)
|
| 838 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_SHIFT 25
|
| 839 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_PRIORITY (0x00 << 25)
|
| 840 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_512_16384 (0x01 << 25)
|
| 841 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_1024_32768 (0x02 << 25)
|
| 842 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_2048_65536 (0x03 << 25)
|
| 843 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_4096_131072 (0x04 << 25)
|
| 844 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_8192_262144 (0x05 << 25)
|
| 845 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_16384_524288 (0x06 << 25)
|
| 846 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_BWC_32678_1048576 (0x07 << 25)
|
| 847 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_SINC (0x01 << 22)
|
| 848 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_MASK (0x03 << 20)
|
| 849 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_SHIFT 20
|
| 850 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_LONGWORD (0x00 << 20)
|
| 851 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_BYTE (0x01 << 20)
|
| 852 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_WORD (0x02 << 20)
|
| 853 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_SSIZE_LINE (0x03 << 20)
|
| 854 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_DINC (0x01 << 19)
|
| 855 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_MASK (0x03 << 17)
|
| 856 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_SHIFT 17
|
| 857 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_LONGWORD (0x00 << 17)
|
| 858 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_BYTE (0x01 << 17)
|
| 859 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_WORD (0x02 << 17)
|
| 860 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_DSIZE_LINE (0x03 << 17)
|
| 861 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_START (0x01 << 16)
|
| 862 |
|
|
# define HAL_MCFxxxx_DMAx_DCRx_AT (0x01 << 15)
|
| 863 |
|
|
|
| 864 |
|
|
# define HAL_MCFxxxx_DMAx_DSRx_CE (0x01 << 6)
|
| 865 |
|
|
# define HAL_MCFxxxx_DMAx_DSRx_BES (0x01 << 5)
|
| 866 |
|
|
# define HAL_MCFxxxx_DMAx_DSRx_BED (0x01 << 4)
|
| 867 |
|
|
# define HAL_MCFxxxx_DMAx_DSRx_REQ (0x01 << 2)
|
| 868 |
|
|
# define HAL_MCFxxxx_DMAx_DSRx_BSY (0x01 << 1)
|
| 869 |
|
|
# define HAL_MCFxxxx_DMAx_DSRx_DONE (0x01 << 0)
|
| 870 |
|
|
|
| 871 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_DMA
|
| 872 |
|
|
|
| 873 |
|
|
// ----------------------------------------------------------------------------
|
| 874 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_PIT
|
| 875 |
|
|
// Programmable interrupt timer modules
|
| 876 |
|
|
|
| 877 |
|
|
# define HAL_MCFxxxx_PITx_PCSR 0x00000000
|
| 878 |
|
|
# define HAL_MCFxxxx_PITx_PMR 0x00000002
|
| 879 |
|
|
# define HAL_MCFxxxx_PITx_PCNTR 0x00000004
|
| 880 |
|
|
|
| 881 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_MASK (0x0F < 8)
|
| 882 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_SHIFT 8
|
| 883 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_2 (0x00 << 8)
|
| 884 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_4 (0x01 << 8)
|
| 885 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_8 (0x02 << 8)
|
| 886 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_16 (0x03 << 8)
|
| 887 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_32 (0x04 << 8)
|
| 888 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_64 (0x05 << 8)
|
| 889 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_128 (0x06 << 8)
|
| 890 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_256 (0x07 << 8)
|
| 891 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_512 (0x08 << 8)
|
| 892 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_1024 (0x09 << 8)
|
| 893 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_2048 (0x0A << 8)
|
| 894 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_4096 (0x0B << 8)
|
| 895 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_8192 (0x0C << 8)
|
| 896 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_16384 (0x0D << 8)
|
| 897 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_32768 (0x0E << 8)
|
| 898 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PRE_65536 (0x0F << 8)
|
| 899 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_DOZE (0x01 << 6)
|
| 900 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_HALTED (0x01 << 5)
|
| 901 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_DBG HAL_MCFxxxx_PITx_PCSR_HALTED
|
| 902 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_OVW (0x01 << 4)
|
| 903 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PIE (0x01 << 3)
|
| 904 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_PIF (0x01 << 2)
|
| 905 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_RLD (0x01 << 1)
|
| 906 |
|
|
# define HAL_MCFxxxx_PITx_PCSR_EN (0x01 << 0)
|
| 907 |
|
|
|
| 908 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_PIT
|
| 909 |
|
|
|
| 910 |
|
|
// ----------------------------------------------------------------------------
|
| 911 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_GPT
|
| 912 |
|
|
|
| 913 |
|
|
// General purpose timer modules
|
| 914 |
|
|
// 8-bit input capture/output compare register
|
| 915 |
|
|
# define HAL_MCFxxxx_GPTx_IOS 0x0000
|
| 916 |
|
|
// 8-bit compare force register
|
| 917 |
|
|
# define HAL_MCFxxxx_GPTx_CFORC 0x0001
|
| 918 |
|
|
// 8-bit output compare 3 mask register
|
| 919 |
|
|
# define HAL_MCFxxxx_GPTx_OC3M 0x0002
|
| 920 |
|
|
// 8-bit output compare 3 data register
|
| 921 |
|
|
# define HAL_MCFxxxx_GPTx_OC3D 0x0003
|
| 922 |
|
|
// 16-bit counter registers
|
| 923 |
|
|
# define HAL_MCFxxxx_GPTx_CNT 0x0004
|
| 924 |
|
|
// 8-bit system control register 1
|
| 925 |
|
|
# define HAL_MCFxxxx_GPTx_SCR1 0x0006
|
| 926 |
|
|
// 8-bit toggle-on-overflow register
|
| 927 |
|
|
# define HAL_MCFxxxx_GPTx_TOV 0x0008
|
| 928 |
|
|
// 8-bit control register 1
|
| 929 |
|
|
# define HAL_MCFxxxx_GPTx_CTL1 0x0009
|
| 930 |
|
|
// 8-bit control register 2
|
| 931 |
|
|
# define HAL_MCFxxxx_GPTx_CTL2 0x000B
|
| 932 |
|
|
// 8-bit interrupt enable register
|
| 933 |
|
|
# define HAL_MCFxxxx_GPTx_IE 0x000C
|
| 934 |
|
|
// 8-bit system control register 2
|
| 935 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2 0x000D
|
| 936 |
|
|
// 8-bit flag registers
|
| 937 |
|
|
# define HAL_MCFxxxx_GPTx_FLG1 0x000E
|
| 938 |
|
|
# define HAL_MCFxxxx_GPTx_FLG2 0x000F
|
| 939 |
|
|
// 16-bit channel registers
|
| 940 |
|
|
# define HAL_MCFxxxx_GPTx_C0 0x0010
|
| 941 |
|
|
# define HAL_MCFxxxx_GPTx_C1 0x0012
|
| 942 |
|
|
# define HAL_MCFxxxx_GPTx_C2 0x0014
|
| 943 |
|
|
# define HAL_MCFxxxx_GPTx_C3 0x0016
|
| 944 |
|
|
// 8-bit pulse accumulator control register
|
| 945 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL 0x0018
|
| 946 |
|
|
// 8-bit pulse accumulator flag register
|
| 947 |
|
|
# define HAL_MCFxxxx_GPTx_PAFLG 0x0019
|
| 948 |
|
|
// 16-bit pulse accumulator counter register
|
| 949 |
|
|
# define HAL_MCFxxxx_GPTx_PACNT 0x001A
|
| 950 |
|
|
// 8-bit port data registers
|
| 951 |
|
|
# define HAL_MCFxxxx_GPTx_PORT 0x001D
|
| 952 |
|
|
// 8-bit port data direction register
|
| 953 |
|
|
# define HAL_MCFxxxx_GPTx_DDR 0x001E
|
| 954 |
|
|
|
| 955 |
|
|
# define HAL_MCFxxxx_GPTx_SCR1_GPTEN (0x01 << 7)
|
| 956 |
|
|
# define HAL_MCFxxxx_GPTx_SCR1_TFFCA (0x01 << 4)
|
| 957 |
|
|
|
| 958 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_TOI (0x01 << 7)
|
| 959 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PUPT (0x01 << 5)
|
| 960 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_RDPT (0x01 << 4)
|
| 961 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_TCRE (0x01 << 3)
|
| 962 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_MASK (0x07 << 0)
|
| 963 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_SHIFT 0
|
| 964 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV1 0x00
|
| 965 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV2 0x01
|
| 966 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV4 0x02
|
| 967 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV8 0x03
|
| 968 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV16 0x04
|
| 969 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV32 0x05
|
| 970 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV64 0x06
|
| 971 |
|
|
# define HAL_MCFxxxx_GPTx_SCR2_PR_DIV128 0x07
|
| 972 |
|
|
|
| 973 |
|
|
# define HAL_MCFxxxx_GPTx_FLG2_TOF (0x01 << 7)
|
| 974 |
|
|
|
| 975 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_PAE (0x01 << 6)
|
| 976 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_PAMOD (0x01 << 5)
|
| 977 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_PEDGE (0x01 << 4)
|
| 978 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_CLK_MASK (0x03 << 2)
|
| 979 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_CLK_SHIFT 2
|
| 980 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_CLK_PRESCALER (0x00 << 2)
|
| 981 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK (0x01 << 2)
|
| 982 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK_256 (0x02 << 2)
|
| 983 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_CLK_PACLK_65536 (0x03 << 2)
|
| 984 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_PAOVI (0x01 << 1)
|
| 985 |
|
|
# define HAL_MCFxxxx_GPTx_PACTL_PAI (0x01 << 0)
|
| 986 |
|
|
|
| 987 |
|
|
# define HAL_MCFxxxx_GPTx_PAFLG_PAOVF (0x01 << 1)
|
| 988 |
|
|
# define HAL_MCFxxxx_GPTx_PAFLG_PAIF (0x01 << 0)
|
| 989 |
|
|
|
| 990 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_GPT
|
| 991 |
|
|
|
| 992 |
|
|
// ----------------------------------------------------------------------------
|
| 993 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_DTMR
|
| 994 |
|
|
|
| 995 |
|
|
// DMA timers
|
| 996 |
|
|
// 16-bit timer mode registers
|
| 997 |
|
|
# define HAL_MCFxxxx_DTMRx 0x0000
|
| 998 |
|
|
// 8-bit extended mode registers
|
| 999 |
|
|
# define HAL_MCFxxxx_DTXMRx 0x0002
|
| 1000 |
|
|
// 8-bit event registers
|
| 1001 |
|
|
# define HAL_MCFxxxx_DTERx 0x00003
|
| 1002 |
|
|
// 32-bit reference, capture and counter registers
|
| 1003 |
|
|
# define HAL_MCFxxxx_DTRRx 0x0004
|
| 1004 |
|
|
# define HAL_MCFxxxx_DTCRx 0x0008
|
| 1005 |
|
|
# define HAL_MCFxxxx_DTCNx 0x000C
|
| 1006 |
|
|
|
| 1007 |
|
|
# define HAL_MCFxxxx_DTMRx_PS_MASK (0x0FF << 8)
|
| 1008 |
|
|
# define HAL_MCFxxxx_DTMRx_PS_SHIFT 8
|
| 1009 |
|
|
# define HAL_MCFxxxx_DTMRx_CE_MASK (0x03 << 6)
|
| 1010 |
|
|
# define HAL_MCFxxxx_DTMRx_CE_SHIFT 6
|
| 1011 |
|
|
# define HAL_MCFxxxx_DTMRx_CE_DISABLE (0x00 << 6)
|
| 1012 |
|
|
# define HAL_MCFxxxx_DTMRx_CE_RISING (0x01 << 6)
|
| 1013 |
|
|
# define HAL_MCFxxxx_DTMRx_CE_FALLING (0x02 << 6)
|
| 1014 |
|
|
# define HAL_MCFxxxx_DTMRx_CE_ANY (0x03 << 6)
|
| 1015 |
|
|
# define HAL_MCFxxxx_DTMRx_OM (0x01 << 5)
|
| 1016 |
|
|
# define HAL_MCFxxxx_DTMRx_ORRI (0x01 << 4)
|
| 1017 |
|
|
# define HAL_MCFxxxx_DTMRx_FRR (0x01 << 3)
|
| 1018 |
|
|
# define HAL_MCFxxxx_DTMRx_CLK_MASK (0x03 << 1)
|
| 1019 |
|
|
# define HAL_MCFxxxx_DTMRx_CLK_SHIFT 1
|
| 1020 |
|
|
# define HAL_MCFxxxx_DTMRx_CLK_STOP (0x00 << 1)
|
| 1021 |
|
|
# define HAL_MCFxxxx_DTMRx_CLK_DIV_1 (0x01 << 1)
|
| 1022 |
|
|
# define HAL_MCFxxxx_DTMRx_CLK_DIV_16 (0x02 << 1)
|
| 1023 |
|
|
# define HAL_MCFxxxx_DTMRx_CLK_DTINn (0x03 << 1)
|
| 1024 |
|
|
# define HAL_MCFxxxx_DTMRx_RST (0x01 << 0)
|
| 1025 |
|
|
|
| 1026 |
|
|
# define HAL_MCFxxxx_DTXMRx_DMAEN (0x01 << 7)
|
| 1027 |
|
|
# define HAL_MCFxxxx_DTXMRx_MODE16 (0x01 << 1)
|
| 1028 |
|
|
|
| 1029 |
|
|
# define HAL_MCFxxxx_DTERx_REF (0x01 << 1)
|
| 1030 |
|
|
# define HAL_MCFxxxx_DTERx_CAP (0x01 << 0)
|
| 1031 |
|
|
|
| 1032 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_DTMR
|
| 1033 |
|
|
|
| 1034 |
|
|
// ----------------------------------------------------------------------------
|
| 1035 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_ETH
|
| 1036 |
|
|
// Ethernet. Allow for multiple devices.
|
| 1037 |
|
|
|
| 1038 |
|
|
# define HAL_MCFxxxx_ETHx_EIR 0x0004
|
| 1039 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR 0x0008
|
| 1040 |
|
|
# define HAL_MCFxxxx_ETHx_RDAR 0x0010
|
| 1041 |
|
|
# define HAL_MCFxxxx_ETHx_TDAR 0x0014
|
| 1042 |
|
|
# define HAL_MCFxxxx_ETHx_ECR 0x0024
|
| 1043 |
|
|
# define HAL_MCFxxxx_ETHx_MDATA 0x0040
|
| 1044 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR 0x0040
|
| 1045 |
|
|
# define HAL_MCFxxxx_ETHx_MSCR 0x0044
|
| 1046 |
|
|
# define HAL_MCFxxxx_ETHx_MIBC 0x0064
|
| 1047 |
|
|
# define HAL_MCFxxxx_ETHx_RCR 0x0084
|
| 1048 |
|
|
# define HAL_MCFxxxx_ETHx_TCR 0x00C4
|
| 1049 |
|
|
# define HAL_MCFxxxx_ETHx_PALR 0x00E4
|
| 1050 |
|
|
# define HAL_MCFxxxx_ETHx_PAUR 0x00E8
|
| 1051 |
|
|
# define HAL_MCFxxxx_ETHx_OPD 0x00EC
|
| 1052 |
|
|
# define HAL_MCFxxxx_ETHx_IAUR 0x0118
|
| 1053 |
|
|
# define HAL_MCFxxxx_ETHx_IALR 0x011C
|
| 1054 |
|
|
# define HAL_MCFxxxx_ETHx_GAUR 0x0120
|
| 1055 |
|
|
# define HAL_MCFxxxx_ETHx_GALR 0x0124
|
| 1056 |
|
|
# define HAL_MCFxxxx_ETHx_TFWR 0x0144
|
| 1057 |
|
|
# define HAL_MCFxxxx_ETHx_FRBR 0x014C
|
| 1058 |
|
|
# define HAL_MCFxxxx_ETHx_FRSR 0x0150
|
| 1059 |
|
|
# define HAL_MCFxxxx_ETHx_ERDSR 0x0180
|
| 1060 |
|
|
# define HAL_MCFxxxx_ETHx_ETDSR 0x0184
|
| 1061 |
|
|
# define HAL_MCFxxxx_ETHx_EMRBR 0x0188
|
| 1062 |
|
|
|
| 1063 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_DROP 0x0200
|
| 1064 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_PACKETS 0x0204
|
| 1065 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_BC_PKT 0x0208
|
| 1066 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_MC_PKT 0x020C
|
| 1067 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_CRC_ALIGN 0x0210
|
| 1068 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_UNDERSIZE 0x0214
|
| 1069 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_OVERSIZE 0x0218
|
| 1070 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_FRAG 0x021C
|
| 1071 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_JAB 0x0220
|
| 1072 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_COL 0x0224
|
| 1073 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_P64 0x0228
|
| 1074 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_P65TO127 0x022C
|
| 1075 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_P128TO255 0x0230
|
| 1076 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_P256TO511 0x0234
|
| 1077 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_P512TO1023 0x0238
|
| 1078 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_P1024TO2047 0x023C
|
| 1079 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_PGTE2048 0x0240
|
| 1080 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_T_OCTETS 0x0244
|
| 1081 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_DROP 0x0248
|
| 1082 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_FRAME_OK 0x024C
|
| 1083 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_1COL 0x0250
|
| 1084 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_MCOL 0x0254
|
| 1085 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_DEF 0x0258
|
| 1086 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_LCOL 0x025C
|
| 1087 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_EXCOL 0x0260
|
| 1088 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_MACERR 0x0264
|
| 1089 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_CSERR 0x0268
|
| 1090 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_SQE 0x026C
|
| 1091 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_FDXFC 0x0270
|
| 1092 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_T_OCTETS_OK 0x0274
|
| 1093 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_PACKETS 0x0284
|
| 1094 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_BC_PKT 0x0288
|
| 1095 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_MC_PKT 0x028C
|
| 1096 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_CRC_ALIGN 0x0290
|
| 1097 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_UNDERSIZE 0x0294
|
| 1098 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_OVERSIZE 0x0298
|
| 1099 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_FRAG 0x029C
|
| 1100 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_JAB 0x02A0
|
| 1101 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_RESVD_0 0x02A4
|
| 1102 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_P64 0x02A8
|
| 1103 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_P65TO127 0x02AC
|
| 1104 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_P128TO255 0x02B0
|
| 1105 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_P256TO511 0x02B4
|
| 1106 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_P512TO1023 0x02B8
|
| 1107 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_P1024TO2047 0x02BC
|
| 1108 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_GTE2048 0x02C0
|
| 1109 |
|
|
# define HAL_MCFxxxx_ETHx_RMON_R_OCTETS 0x02C4
|
| 1110 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_R_DROP 0x02C8
|
| 1111 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_R_FRAME_OK 0x02CC
|
| 1112 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_R_CRC 0x02D0
|
| 1113 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_R_ALIGN 0x02D4
|
| 1114 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_R_MACERR 0x02D8
|
| 1115 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_R_FDXFC 0x02DC
|
| 1116 |
|
|
# define HAL_MCFxxxx_ETHx_IEEE_R_OCTETS_OK 0x02E0
|
| 1117 |
|
|
|
| 1118 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_HBERR (0x01 << 31)
|
| 1119 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_BABR (0x01 << 30)
|
| 1120 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_BABT (0x01 << 29)
|
| 1121 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_GRA (0x01 << 28)
|
| 1122 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_TXF (0x01 << 27)
|
| 1123 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_TXB (0x01 << 26)
|
| 1124 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_RXF (0x01 << 25)
|
| 1125 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_RXB (0x01 << 24)
|
| 1126 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_MII (0x01 << 23)
|
| 1127 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_EBERR (0x01 << 22)
|
| 1128 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_LC (0x01 << 21)
|
| 1129 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_RL (0x01 << 20)
|
| 1130 |
|
|
# define HAL_MCFxxxx_ETHx_EIR_UN (0x01 << 19)
|
| 1131 |
|
|
|
| 1132 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_HBERR HAL_MCFxxxx_ETHx_EIR_HBERR
|
| 1133 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_BABR HAL_MCFxxxx_ETHx_EIR_BABR
|
| 1134 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_BABT HAL_MCFxxxx_ETHx_EIR_BABT
|
| 1135 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_GRA HAL_MCFxxxx_ETHx_EIR_GRA
|
| 1136 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_TXF HAL_MCFxxxx_ETHx_EIR_TXF
|
| 1137 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_TXB HAL_MCFxxxx_ETHx_EIR_TXB
|
| 1138 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_RXF HAL_MCFxxxx_ETHx_EIR_RXF
|
| 1139 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_RXB HAL_MCFxxxx_ETHx_EIR_RXB
|
| 1140 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_MII HAL_MCFxxxx_ETHx_EIR_MII
|
| 1141 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_EBERR HAL_MCFxxxx_ETHx_EIR_EBERR
|
| 1142 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_LC HAL_MCFxxxx_ETHx_EIR_LC
|
| 1143 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_RL HAL_MCFxxxx_ETHx_EIR_RL
|
| 1144 |
|
|
# define HAL_MCFxxxx_ETHx_EIMR_UN HAL_MCFxxxx_ETHx_EIR_UN
|
| 1145 |
|
|
|
| 1146 |
|
|
# define HAL_MCFxxxx_ETHx_RDAR_R_DES_ACTIVE (0x01 << 24)
|
| 1147 |
|
|
# define HAL_MCFxxxx_ETHx_TDAR_X_DES_ACTIVE (0x01 << 24)
|
| 1148 |
|
|
|
| 1149 |
|
|
# define HAL_MCFxxxx_ETHx_ECR_ETHER_EN (0x01 << 1)
|
| 1150 |
|
|
# define HAL_MCFxxxx_ETHx_ECR_RESET (0x01 << 0)
|
| 1151 |
|
|
|
| 1152 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_ST_MASK (0x03 << 30)
|
| 1153 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_ST_SHIFT 30
|
| 1154 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_ST_VALUE (0x01 << 30)
|
| 1155 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_OP_MASK (0x03 << 28)
|
| 1156 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_OP_READ (0x02 << 28)
|
| 1157 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_OP_WRITE (0x01 << 28)
|
| 1158 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_PA_MASK (0x1F << 23)
|
| 1159 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_PA_SHIFT 23
|
| 1160 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_RA_MASK (0x1F << 18)
|
| 1161 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_RA_SHIFT 18
|
| 1162 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_TA_MASK (0x03 << 16)
|
| 1163 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_TA_SHIFT 16
|
| 1164 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_TA_VALUE (0x02 << 16)
|
| 1165 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_DATA_MASK (0x0FFFF << 0)
|
| 1166 |
|
|
# define HAL_MCFxxxx_ETHx_MMFR_DATA_SHIFT 0
|
| 1167 |
|
|
|
| 1168 |
|
|
# define HAL_MCFxxxx_ETHx_MSCR_DIS_PREAMBLE (0x01 << 7)
|
| 1169 |
|
|
# define HAL_MCFxxxx_ETHx_MSCR_MII_SPEED_MASK (0x3F << 1)
|
| 1170 |
|
|
# define HAL_MCFxxxx_ETHx_MSCR_MII_SPEED_SHIFT 1
|
| 1171 |
|
|
|
| 1172 |
|
|
# define HAL_MCFxxxx_ETHx_MIBC_MIB_DISABLE (0x01 << 31)
|
| 1173 |
|
|
# define HAL_MCFxxxx_ETHx_MIBC_MIB_IDLE (0x01 << 30)
|
| 1174 |
|
|
|
| 1175 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_MASK (0x03FFF << 16)
|
| 1176 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_SHIFT 16
|
| 1177 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_MAX_FL_VALUE (1518 << 16)
|
| 1178 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_FCE (0x01 << 5)
|
| 1179 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_BC_REJ (0x01 << 4)
|
| 1180 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_PROM (0x01 << 3)
|
| 1181 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_MII_MODE (0x01 << 2)
|
| 1182 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_DRT (0x01 << 1)
|
| 1183 |
|
|
# define HAL_MCFxxxx_ETHx_RCR_LOOP (0x01 << 0)
|
| 1184 |
|
|
|
| 1185 |
|
|
# define HAL_MCFxxxx_ETHx_TCR_RFC_PAUSE (0x01 << 4)
|
| 1186 |
|
|
# define HAL_MCFxxxx_ETHx_TCR_TFC_PAUSE (0x01 << 3)
|
| 1187 |
|
|
# define HAL_MCFxxxx_ETHx_TCR_FDEN (0x01 << 2)
|
| 1188 |
|
|
# define HAL_MCFxxxx_ETHx_TCR_HBC (0x01 << 1)
|
| 1189 |
|
|
# define HAL_MCFxxxx_ETHx_TCR_GTS (0x01 << 0)
|
| 1190 |
|
|
|
| 1191 |
|
|
# define HAL_MCFxxxx_ETHx_OPD_OPCODE_MASK (0x0FFFF << 16)
|
| 1192 |
|
|
# define HAL_MCFxxxx_ETHx_OPD_OPCODE_SHIFT 16
|
| 1193 |
|
|
# define HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_MASK (0x0FFFF << 0)
|
| 1194 |
|
|
# define HAL_MCFxxxx_ETHx_OPD_PAUSE_DUR_SHIFT 0
|
| 1195 |
|
|
|
| 1196 |
|
|
# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_MASK (0x03 << 0)
|
| 1197 |
|
|
# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_SHIFT 0
|
| 1198 |
|
|
# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_64 (0x00 << 0)
|
| 1199 |
|
|
# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_128 (0x02 << 0)
|
| 1200 |
|
|
# define HAL_MCFxxxx_ETHx_TFWR_X_WMRK_192 (0x03 << 0)
|
| 1201 |
|
|
|
| 1202 |
|
|
// This is the data structure for a buffer descriptor.
|
| 1203 |
|
|
# if !defined( __ASSEMBLER__) && !defined(__LDI__)
|
| 1204 |
|
|
typedef struct hal_mcfxxxx_eth_buffer_descriptor {
|
| 1205 |
|
|
cyg_uint16 ethbd_flags;
|
| 1206 |
|
|
cyg_uint16 ethbd_length;
|
| 1207 |
|
|
cyg_uint8* ethbd_buffer;
|
| 1208 |
|
|
} hal_mcfxxxx_eth_buffer_descriptor;
|
| 1209 |
|
|
# endif
|
| 1210 |
|
|
|
| 1211 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_E (0x01 << 15)
|
| 1212 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_RO1 (0x01 << 14)
|
| 1213 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_W (0x01 << 13)
|
| 1214 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_RO2 (0x01 << 12)
|
| 1215 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_L (0x01 << 11)
|
| 1216 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_M (0x01 << 8)
|
| 1217 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_BC (0x01 << 7)
|
| 1218 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_MC (0x01 << 6)
|
| 1219 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_LG (0x01 << 5)
|
| 1220 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_NO (0x01 << 4)
|
| 1221 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_CR (0x01 << 2)
|
| 1222 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_OV (0x01 << 1)
|
| 1223 |
|
|
# define HAL_MCFxxxx_ETHx_RXBD_TR (0x01 << 0)
|
| 1224 |
|
|
|
| 1225 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_R (0x01 << 15)
|
| 1226 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_TO1 (0x01 << 14)
|
| 1227 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_W (0x01 << 13)
|
| 1228 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_TO2 (0x01 << 12)
|
| 1229 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_L (0x01 << 11)
|
| 1230 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_TC (0x01 << 10)
|
| 1231 |
|
|
# define HAL_MCFxxxx_ETHx_TXBD_ABC (0x01 << 9)
|
| 1232 |
|
|
|
| 1233 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_ETH
|
| 1234 |
|
|
|
| 1235 |
|
|
// ----------------------------------------------------------------------------
|
| 1236 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_QSPI
|
| 1237 |
|
|
|
| 1238 |
|
|
// QSPI
|
| 1239 |
|
|
// Six 16-bit registers: mode, delay, wrap, interrupt, address and data
|
| 1240 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR 0x0000
|
| 1241 |
|
|
# define HAL_MCFxxxx_QSPIx_QDLYR 0x0004
|
| 1242 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR 0x0008
|
| 1243 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR 0x000C
|
| 1244 |
|
|
# define HAL_MCFxxxx_QSPIx_QAR 0x0010
|
| 1245 |
|
|
# define HAL_MCFxxxx_QSPIx_QDR 0x0014
|
| 1246 |
|
|
|
| 1247 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_MSTR (0x01 << 15)
|
| 1248 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_DOHIE (0x01 << 14)
|
| 1249 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_MASK (0x0F << 10)
|
| 1250 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_SHIFT 10
|
| 1251 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_16 (0x00 << 10)
|
| 1252 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_8 (0x08 << 10)
|
| 1253 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_9 (0x09 << 10)
|
| 1254 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_10 (0x0A << 10)
|
| 1255 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_11 (0x0B << 10)
|
| 1256 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_12 (0x0C << 10)
|
| 1257 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_13 (0x0D << 10)
|
| 1258 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_14 (0x0E << 10)
|
| 1259 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BITS_15 (0x0F << 10)
|
| 1260 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_CPOL (0x01 << 9)
|
| 1261 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_CPHA (0x01 << 8)
|
| 1262 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BAUD_MASK (0x0FF << 0)
|
| 1263 |
|
|
# define HAL_MCFxxxx_QSPIx_QMR_BAUD_SHIFT 0
|
| 1264 |
|
|
|
| 1265 |
|
|
# define HAL_MCFxxxx_QSPIx_QDLYR_SPE (0x01 << 15)
|
| 1266 |
|
|
# define HAL_MCFxxxx_QSPIx_QDLYR_QCD_MASK (0x07F << 8)
|
| 1267 |
|
|
# define HAL_MCFxxxx_QSPIx_QDLYR_QCD_SHIFT 8
|
| 1268 |
|
|
# define HAL_MCFxxxx_QSPIx_QDLYR_DTL_MASK (0x0FF << 0)
|
| 1269 |
|
|
# define HAL_MCFxxxx_QSPIx_QDLYR_DTL_SHIFT 0
|
| 1270 |
|
|
|
| 1271 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_HALT (0x01 << 15)
|
| 1272 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_WREN (0x01 << 14)
|
| 1273 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_WRTO (0x01 << 13)
|
| 1274 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_CSIV (0x01 << 12)
|
| 1275 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_ENDQP_MASK (0x0F << 8)
|
| 1276 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_ENDQP_SHIFT 8
|
| 1277 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_CPTQP_MASK (0x0F << 4)
|
| 1278 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_CPTQP_SHIFT 4
|
| 1279 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_NEWQP_MASK (0x0F << 0)
|
| 1280 |
|
|
# define HAL_MCFxxxx_QSPIx_QWR_NEWQP_SHIFT 0
|
| 1281 |
|
|
|
| 1282 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_WCEFB (0x01 << 15)
|
| 1283 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_ABRTB (0x01 << 14)
|
| 1284 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_ABRTL (0x01 << 12)
|
| 1285 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_WCEFE (0x01 << 11)
|
| 1286 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_ABRTE (0x01 << 10)
|
| 1287 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_SPIFE (0x01 << 8)
|
| 1288 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_WCEF (0x01 << 3)
|
| 1289 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_ABRT (0x01 << 2)
|
| 1290 |
|
|
# define HAL_MCFxxxx_QSPIx_QIR_SPIF (0x01 << 0)
|
| 1291 |
|
|
|
| 1292 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_CONT (0x01 << 15)
|
| 1293 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_BITSE (0x01 << 14)
|
| 1294 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_DT (0x01 << 13)
|
| 1295 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_DSCK (0x01 << 12)
|
| 1296 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_MASK (0x0F << 8)
|
| 1297 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_SHIFT 8
|
| 1298 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS0 (0x01 << 8)
|
| 1299 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS1 (0x02 << 8)
|
| 1300 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS2 (0x04 << 8)
|
| 1301 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CS3 (0x08 << 8)
|
| 1302 |
|
|
# define HAL_MCFxxxx_QSPI_QCRn_QSPI_CS_CSn(__n) ((__n) << 8)
|
| 1303 |
|
|
# define HAL_MCFxxxx_QSPIx_QCRn_QSPI_CS_CSn(__n) ((__n) << 8)
|
| 1304 |
|
|
|
| 1305 |
|
|
# define HAL_MCFxxxx_QSPIx_QAR_TX_BASE 0x0000
|
| 1306 |
|
|
# define HAL_MCFxxxx_QSPIx_QAR_RX_BASE 0x0010
|
| 1307 |
|
|
# define HAL_MCFxxxx_QSPIx_QAR_COMMAND_BASE 0x0020
|
| 1308 |
|
|
|
| 1309 |
|
|
# define HAL_MCFxxxx_QSPIx_DEV_TO_BAUD(_dev_setting_arg_, _baud_) \
|
| 1310 |
|
|
CYG_MACRO_START \
|
| 1311 |
|
|
cyg_uint32 _dev_setting_ = (cyg_uint32) (_dev_setting_arg_); \
|
| 1312 |
|
|
cyg_uint32 _result_; \
|
| 1313 |
|
|
if (0 == _dev_setting_) { \
|
| 1314 |
|
|
_result_ = 0; \
|
| 1315 |
|
|
} else { \
|
| 1316 |
|
|
_result_ = CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _dev_setting_); \
|
| 1317 |
|
|
} \
|
| 1318 |
|
|
_baud_ = _result_; \
|
| 1319 |
|
|
CYG_MACRO_END
|
| 1320 |
|
|
|
| 1321 |
|
|
// When calculating a device setting, if the baud rate cannot be supported exactly
|
| 1322 |
|
|
// then switch to the next slowest setting.
|
| 1323 |
|
|
# define HAL_MCFxxxx_QSPIx_BAUD_TO_DEV(_baud_arg_, _dev_setting_) \
|
| 1324 |
|
|
CYG_MACRO_START \
|
| 1325 |
|
|
cyg_uint32 _baud_ = (cyg_uint32) (_baud_arg_); \
|
| 1326 |
|
|
cyg_uint32 _result_; \
|
| 1327 |
|
|
if (0 == _baud_) { \
|
| 1328 |
|
|
_result_ = 0; \
|
| 1329 |
|
|
} else { \
|
| 1330 |
|
|
_result_ = CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _baud_); \
|
| 1331 |
|
|
if (_baud_ != (CYGHWR_HAL_SYSTEM_CLOCK_HZ / (2 * _result_))) { \
|
| 1332 |
|
|
_result_++; \
|
| 1333 |
|
|
} \
|
| 1334 |
|
|
if (_result_ < 2) { \
|
| 1335 |
|
|
_result_ = 2; \
|
| 1336 |
|
|
} else if (_result_ > 255) { \
|
| 1337 |
|
|
_result_ = 255; \
|
| 1338 |
|
|
} \
|
| 1339 |
|
|
} \
|
| 1340 |
|
|
_dev_setting_ = _result_; \
|
| 1341 |
|
|
CYG_MACRO_END
|
| 1342 |
|
|
|
| 1343 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_QSPI
|
| 1344 |
|
|
|
| 1345 |
|
|
// ----------------------------------------------------------------------------
|
| 1346 |
|
|
|
| 1347 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_UART
|
| 1348 |
|
|
// All registers are a single byte.
|
| 1349 |
|
|
# define HAL_MCFxxxx_UARTx_UMR 0x00
|
| 1350 |
|
|
# define HAL_MCFxxxx_UARTx_USR 0x04
|
| 1351 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR 0x04
|
| 1352 |
|
|
# define HAL_MCFxxxx_UARTx_UCR 0x08
|
| 1353 |
|
|
# define HAL_MCFxxxx_UARTx_URB 0x0C
|
| 1354 |
|
|
# define HAL_MCFxxxx_UARTx_UTB 0x0C
|
| 1355 |
|
|
# define HAL_MCFxxxx_UARTx_UIPCR 0x10
|
| 1356 |
|
|
# define HAL_MCFxxxx_UARTx_UACR 0x10
|
| 1357 |
|
|
# define HAL_MCFxxxx_UARTx_UISR 0x14
|
| 1358 |
|
|
# define HAL_MCFxxxx_UARTx_UIMR 0x14
|
| 1359 |
|
|
# define HAL_MCFxxxx_UARTx_UBG1 0x18
|
| 1360 |
|
|
# define HAL_MCFxxxx_UARTx_UBG2 0x1C
|
| 1361 |
|
|
|
| 1362 |
|
|
# define HAL_MCFxxxx_UARTx_UIP 0x34
|
| 1363 |
|
|
# define HAL_MCFxxxx_UARTx_UOP1 0x38
|
| 1364 |
|
|
# define HAL_MCFxxxx_UARTx_UOP0 0x3C
|
| 1365 |
|
|
|
| 1366 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_RXRTS (0x01 << 7)
|
| 1367 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_FFULL (0x01 << 6)
|
| 1368 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_ERR (0x01 << 5)
|
| 1369 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_PM_MASK (0x03 << 3)
|
| 1370 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_PM_SHIFT 3
|
| 1371 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_PM_WITH (0x00 << 3)
|
| 1372 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_PM_FORCE (0x01 << 3)
|
| 1373 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_PM_NO (0x02 << 3)
|
| 1374 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_PM_MULTIDROP (0x03 << 3)
|
| 1375 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_PT (0x01 << 2)
|
| 1376 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_BC_MASK (0x03 << 0)
|
| 1377 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_BC_SHIFT 0
|
| 1378 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_BC_5 (0x00 << 0)
|
| 1379 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_BC_6 (0x01 << 0)
|
| 1380 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_BC_7 (0x02 << 0)
|
| 1381 |
|
|
# define HAL_MCFxxxx_UARTx_UMR1_BC_8 (0x03 << 0)
|
| 1382 |
|
|
|
| 1383 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_CM_MASK (0x03 << 6)
|
| 1384 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_CM_SHIFT 6
|
| 1385 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_CM_NORMAL (0x00 << 6)
|
| 1386 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_CM_AUTO (0x01 << 6)
|
| 1387 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_CM_LOCAL (0x02 << 6)
|
| 1388 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_CM_REMOTE (0x03 << 6)
|
| 1389 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_TXRTS (0x01 << 5)
|
| 1390 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_TXCTS (0x01 << 4)
|
| 1391 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_SB_MASK (0x0f << 0)
|
| 1392 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_SB_SHIFT 0
|
| 1393 |
|
|
// These two constants are only valid for 6-8 bits. 5 bit needs
|
| 1394 |
|
|
// to be treated specially.
|
| 1395 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_SB_1 (0x07 << 0)
|
| 1396 |
|
|
# define HAL_MCFxxxx_UARTx_UMR2_SB_2 (0x0f << 0)
|
| 1397 |
|
|
|
| 1398 |
|
|
# define HAL_MCFxxxx_UARTx_USR_RB (0x01 << 7)
|
| 1399 |
|
|
# define HAL_MCFxxxx_UARTx_USR_FE (0x01 << 6)
|
| 1400 |
|
|
# define HAL_MCFxxxx_UARTx_USR_PE (0x01 << 5)
|
| 1401 |
|
|
# define HAL_MCFxxxx_UARTx_USR_OE (0x01 << 4)
|
| 1402 |
|
|
# define HAL_MCFxxxx_UARTx_USR_TXEMP (0x01 << 3)
|
| 1403 |
|
|
# define HAL_MCFxxxx_UARTx_USR_TXRDY (0x01 << 2)
|
| 1404 |
|
|
# define HAL_MCFxxxx_UARTx_USR_FFULL (0x01 << 1)
|
| 1405 |
|
|
# define HAL_MCFxxxx_UARTx_USR_RXRDY (0x01 << 0)
|
| 1406 |
|
|
|
| 1407 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_RCS_MASK (0x0f << 4)
|
| 1408 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_RCS_SHIFT 4
|
| 1409 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_RCS_CLKIN (0x0D << 4)
|
| 1410 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_RCS_DTINDIV16 (0x0E << 4)
|
| 1411 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_RCS_DTIN (0x0F << 4)
|
| 1412 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_TCS_MASK (0x0f << 0)
|
| 1413 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_TCS_SHIFT (0x0f << 0)
|
| 1414 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_TCS_CLKIN (0x0D << 0)
|
| 1415 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_TCS_DTINDIV16 (0x0E << 0)
|
| 1416 |
|
|
# define HAL_MCFxxxx_UARTx_UCSR_TCS_DTIN (0x0F << 0)
|
| 1417 |
|
|
|
| 1418 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_MASK (0x07 << 4)
|
| 1419 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_SHIFT 4
|
| 1420 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_NOP (0x00 << 4)
|
| 1421 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_RMRP (0x01 << 4)
|
| 1422 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_RR (0x02 << 4)
|
| 1423 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_RT (0x03 << 4)
|
| 1424 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_RES (0x04 << 4)
|
| 1425 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_RBCI (0x05 << 4)
|
| 1426 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_STARTB (0x06 << 4)
|
| 1427 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_MISC_STOPB (0x07 << 4)
|
| 1428 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_TC_MASK (0x03 << 2)
|
| 1429 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_TC_SHIFT 2
|
| 1430 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_TC_NOP (0x00 << 2)
|
| 1431 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_TC_TE (0x01 << 2)
|
| 1432 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_TC_TD (0x02 << 2)
|
| 1433 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_RC_MASK (0x03 << 0)
|
| 1434 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_RC_SHIFT 0
|
| 1435 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_RC_NOP (0x00 << 0)
|
| 1436 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_RC_RE (0x01 << 0)
|
| 1437 |
|
|
# define HAL_MCFxxxx_UARTx_UCR_RC_RD (0x02 << 0)
|
| 1438 |
|
|
|
| 1439 |
|
|
# define HAL_MCFxxxx_UARTx_UIPCR_COS (0x01 << 4)
|
| 1440 |
|
|
# define HAL_MCFxxxx_UARTx_UIPCR_CTS (0x01 << 0)
|
| 1441 |
|
|
|
| 1442 |
|
|
# define HAL_MCFxxxx_UARTx_UACR_IEC (0x01 << 0)
|
| 1443 |
|
|
|
| 1444 |
|
|
// ABC, RXFIFO, TXFIFO and RXFTO are not always available
|
| 1445 |
|
|
# define HAL_MCFxxxx_UARTx_UISR_COS (0x01 << 7)
|
| 1446 |
|
|
# define HAL_MCFxxxx_UARTx_UISR_DB (0x01 << 2)
|
| 1447 |
|
|
# define HAL_MCFxxxx_UARTx_UISR_FFUL (0x01 << 1)
|
| 1448 |
|
|
# define HAL_MCFxxxx_UARTx_UISR_RXRDY (0x01 << 1)
|
| 1449 |
|
|
# define HAL_MCFxxxx_UARTx_UISR_TXRDY (0x01 << 0)
|
| 1450 |
|
|
|
| 1451 |
|
|
# define HAL_MCFxxxx_UARTx_UIMR_COS (0x01 << 7)
|
| 1452 |
|
|
# define HAL_MCFxxxx_UARTx_UIMR_DB (0x01 << 2)
|
| 1453 |
|
|
# define HAL_MCFxxxx_UARTx_UIMR_FFUL (0x01 << 1)
|
| 1454 |
|
|
# define HAL_MCFxxxx_UARTx_UIMR_RXRDY (0x01 << 1)
|
| 1455 |
|
|
# define HAL_MCFxxxx_UARTx_UIMR_TXRDY (0x01 << 0)
|
| 1456 |
|
|
|
| 1457 |
|
|
# define HAL_MCFxxxx_UARTx_UIP_CTS (0x01 << 0)
|
| 1458 |
|
|
# define HAL_MCFxxxx_UARTx_UOP_RTS (0x01 << 0)
|
| 1459 |
|
|
|
| 1460 |
|
|
// The baud rate depends on the system clock. There is no fractional
|
| 1461 |
|
|
// precision register.
|
| 1462 |
|
|
# define HAL_MCFxxxx_UARTx_SET_BAUD(_base_, _baud_) \
|
| 1463 |
|
|
CYG_MACRO_START \
|
| 1464 |
|
|
cyg_uint8 _udu_ = ((cyg_uint8) (((CYGHWR_HAL_SYSTEM_CLOCK_MHZ * 1000000) / (32 * (_baud_))) >> 8)); \
|
| 1465 |
|
|
cyg_uint8 _udl_ = ((cyg_uint8) (((CYGHWR_HAL_SYSTEM_CLOCK_MHZ * 1000000) / (32 * (_baud_))) & 0x00FF)); \
|
| 1466 |
|
|
HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG1, _udu_); \
|
| 1467 |
|
|
HAL_WRITE_UINT8((_base_) + HAL_MCFxxxx_UARTx_UBG2, _udl_); \
|
| 1468 |
|
|
CYG_MACRO_END
|
| 1469 |
|
|
|
| 1470 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_UART
|
| 1471 |
|
|
|
| 1472 |
|
|
// ----------------------------------------------------------------------------
|
| 1473 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_I2C
|
| 1474 |
|
|
// I2C
|
| 1475 |
|
|
// Five 8-bit registers: address, frequency divider, control, status, data
|
| 1476 |
|
|
# define HAL_MCFxxxx_I2Cx_ADR 0x0000
|
| 1477 |
|
|
# define HAL_MCFxxxx_I2Cx_FDR 0x0004
|
| 1478 |
|
|
# define HAL_MCFxxxx_I2Cx_CR 0x0008
|
| 1479 |
|
|
# define HAL_MCFxxxx_I2Cx_SR 0x000C
|
| 1480 |
|
|
# define HAL_MCFxxxx_I2Cx_DR 0x0010
|
| 1481 |
|
|
|
| 1482 |
|
|
# define HAL_MCFxxxx_I2Cx_CR_IEN (0x01 << 7)
|
| 1483 |
|
|
# define HAL_MCFxxxx_I2Cx_CR_IIEN (0x01 << 6)
|
| 1484 |
|
|
# define HAL_MCFxxxx_I2Cx_CR_MSTA (0x01 << 5)
|
| 1485 |
|
|
# define HAL_MCFxxxx_I2Cx_CR_MTX (0x01 << 4)
|
| 1486 |
|
|
# define HAL_MCFxxxx_I2Cx_CR_TXAK (0x01 << 3)
|
| 1487 |
|
|
# define HAL_MCFxxxx_I2Cx_CR_RSTA (0x01 << 2)
|
| 1488 |
|
|
|
| 1489 |
|
|
# define HAL_MCFxxxx_I2Cx_SR_ICF (0x01 << 7)
|
| 1490 |
|
|
# define HAL_MCFxxxx_I2Cx_SR_IAAS (0x01 << 6)
|
| 1491 |
|
|
# define HAL_MCFxxxx_I2Cx_SR_IBB (0x01 << 5)
|
| 1492 |
|
|
# define HAL_MCFxxxx_I2Cx_SR_IAL (0x01 << 4)
|
| 1493 |
|
|
# define HAL_MCFxxxx_I2Cx_SR_SRW (0x01 << 2)
|
| 1494 |
|
|
# define HAL_MCFxxxx_I2Cx_SR_IIF (0x01 << 1)
|
| 1495 |
|
|
# define HAL_MCFxxxx_I2Cx_SR_RXAK (0x01 << 0)
|
| 1496 |
|
|
|
| 1497 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_I2C
|
| 1498 |
|
|
|
| 1499 |
|
|
// ----------------------------------------------------------------------------
|
| 1500 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_CAN
|
| 1501 |
|
|
// FLEXCAN
|
| 1502 |
|
|
// 16-bit module configuration register
|
| 1503 |
|
|
# define HAL_MCFxxxx_CANx_MCR 0x0000
|
| 1504 |
|
|
// Three 8-bit control registers and an 8-bit prescaler
|
| 1505 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0 0x0006
|
| 1506 |
|
|
# define HAL_MCFxxxx_CANx_CTRL1 0x0007
|
| 1507 |
|
|
# define HAL_MCFxxxx_CANx_PRESDIV 0x0008
|
| 1508 |
|
|
# define HAL_MCFxxxx_CANx_CTRL2 0x0009
|
| 1509 |
|
|
// 16-bit free runxxng timer
|
| 1510 |
|
|
# define HAL_MCFxxxx_CANx_TIMER 0x000A
|
| 1511 |
|
|
// 32-bit global and buffer mask registers
|
| 1512 |
|
|
# define HAL_MCFxxxx_CANx_RXGMASK 0x0010
|
| 1513 |
|
|
# define HAL_MCFxxxx_CANx_RX14MASK 0x0014
|
| 1514 |
|
|
# define HAL_MCFxxxx_CANx_RX15MASK 0x0018
|
| 1515 |
|
|
// 16-bit error and status
|
| 1516 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT 0x0020
|
| 1517 |
|
|
// 16-bit interrup mask and flags
|
| 1518 |
|
|
# define HAL_MCFxxxx_CANx_IMASK 0x0022
|
| 1519 |
|
|
# define HAL_MCFxxxx_CANx_IFLAG 0x0024
|
| 1520 |
|
|
// Two 8-bit error counters
|
| 1521 |
|
|
# define HAL_MCFxxxx_CANx_RXECTR 0x0026
|
| 1522 |
|
|
# define HAL_MCFxxxx_CANx_TXECTR 0x0027
|
| 1523 |
|
|
// 16 32-bit message buffers start here
|
| 1524 |
|
|
# define HAL_MCFxxxx_CANx_BUF 0x0080
|
| 1525 |
|
|
|
| 1526 |
|
|
# define HAL_MCFxxxx_CANx_MCR_STOP (0x01 << 15)
|
| 1527 |
|
|
# define HAL_MCFxxxx_CANx_MCR_FRZ (0x01 << 14)
|
| 1528 |
|
|
# define HAL_MCFxxxx_CANx_MCR_HALT (0x01 << 12)
|
| 1529 |
|
|
# define HAL_MCFxxxx_CANx_MCR_NOTRDY (0x01 << 11)
|
| 1530 |
|
|
# define HAL_MCFxxxx_CANx_MCR_WAKEMSK (0x01 << 10)
|
| 1531 |
|
|
# define HAL_MCFxxxx_CANx_MCR_SOFTRST (0x01 << 9)
|
| 1532 |
|
|
# define HAL_MCFxxxx_CANx_MCR_FRZACK (0x01 << 8)
|
| 1533 |
|
|
# define HAL_MCFxxxx_CANx_MCR_SUPV (0x01 << 7)
|
| 1534 |
|
|
# define HAL_MCFxxxx_CANx_MCR_SELFWAKE (0x01 << 6)
|
| 1535 |
|
|
# define HAL_MCFxxxx_CANx_MCR_APS (0x01 << 5)
|
| 1536 |
|
|
# define HAL_MCFxxxx_CANx_MCR_STOPACK (0x01 << 4)
|
| 1537 |
|
|
|
| 1538 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_BOFFMSK (0x01 << 7)
|
| 1539 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_ERRMASK (0x01 << 6)
|
| 1540 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_RXMODE (0x01 << 2)
|
| 1541 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_RXMODE_0_DOMINANT (0x00 << 2)
|
| 1542 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_RXMODE_1_DOMINANT (0x01 << 2)
|
| 1543 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_MASK (0x03 << 0)
|
| 1544 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_SHIFT 0
|
| 1545 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_FULL_0_DOMINANT (0x00 << 0)
|
| 1546 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_FULL_1_DOMINANT (0x01 << 0)
|
| 1547 |
|
|
# define HAL_MCFxxxx_CANx_CTRL0_TXMODE_OPEN_0_DOMINANT (0x02 << 0)
|
| 1548 |
|
|
|
| 1549 |
|
|
# define HAL_MCFxxxx_CANx_CTRL1_SAMP (0x01 << 7)
|
| 1550 |
|
|
# define HAL_MCFxxxx_CANx_CTRL1_TSYNC (0x01 << 5)
|
| 1551 |
|
|
# define HAL_MCFxxxx_CANx_CTRL1_LBUF (0x01 << 4)
|
| 1552 |
|
|
# define HAL_MCFxxxx_CANx_CTRL1_LOM (0x01 << 3)
|
| 1553 |
|
|
# define HAL_MCFxxxx_CANx_CTRL1_PROPSEG_MASK (0x07 << 0)
|
| 1554 |
|
|
# define HAL_MCFxxxx_CANx_CTRL1_PROPSEG_SHIFT 0
|
| 1555 |
|
|
|
| 1556 |
|
|
# define HAL_MCFxxxx_CANx_CTRL2_RJW_MASK (0x03 << 6)
|
| 1557 |
|
|
# define HAL_MCFxxxx_CANx_CTRL2_RJW_SHIFT 6
|
| 1558 |
|
|
# define HAL_MCFxxxx_CANx_CTRL2_PSEG1_MASK (0x07 << 3)
|
| 1559 |
|
|
# define HAL_MCFxxxx_CANx_CTRL2_PSEG1_SHIFT 3
|
| 1560 |
|
|
# define HAL_MCFxxxx_CANx_CTRL2_PSEG2_MASK (0x07 << 0)
|
| 1561 |
|
|
# define HAL_MCFxxxx_CANx_CTRL2_PSEG2_SHIFT 0
|
| 1562 |
|
|
|
| 1563 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_BITERR_MASK (0x03 << 14)
|
| 1564 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_BITERR_SHIFT 14
|
| 1565 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_BITERR_NONE (0x00 << 14)
|
| 1566 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_BITERR_DOMINANT_RECESSIVE (0x01 << 14)
|
| 1567 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_BITERR_RECESSIVE_DOMINANT (0x02 << 14)
|
| 1568 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_ACKERR (0x01 << 13)
|
| 1569 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_CRCERR (0x01 << 12)
|
| 1570 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_FORMERR (0x01 << 11)
|
| 1571 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_STUFFERR (0x01 << 10)
|
| 1572 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_TXWARN (0x01 << 9)
|
| 1573 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_RXWARN (0x01 << 8)
|
| 1574 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_IDLE (0x01 << 7)
|
| 1575 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_TX_RX (0x01 << 6)
|
| 1576 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_FCS_MASK (0x03 << 4)
|
| 1577 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_FCS_SHIFT 4
|
| 1578 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_FCS_ERROR_ACTIVE (0x00 << 4)
|
| 1579 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_FCS_ERROR_PASSIVE (0x01 << 4)
|
| 1580 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_BOFFINT (0x01 << 2)
|
| 1581 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_ERRINT (0x01 << 1)
|
| 1582 |
|
|
# define HAL_MCFxxxx_CANx_ESTAT_WAKEINT (0x01 << 0)
|
| 1583 |
|
|
|
| 1584 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_CAN
|
| 1585 |
|
|
|
| 1586 |
|
|
// Some ColdFire processors have a variation of the CAN device where all
|
| 1587 |
|
|
// the registers are 32-bit.
|
| 1588 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCFxxxx_CAN_32BIT_REGS
|
| 1589 |
|
|
# define HAL_MCFxxxx_CANx_MCR 0x0000
|
| 1590 |
|
|
# define HAL_MCFxxxx_CANx_CTRL 0x0004
|
| 1591 |
|
|
# define HAL_MCFxxxx_CANx_TIMER 0x0008
|
| 1592 |
|
|
# define HAL_MCFxxxx_CANx_RXGMASK 0x0010
|
| 1593 |
|
|
# define HAL_MCFxxxx_CANx_RX14MASK 0x0014
|
| 1594 |
|
|
# define HAL_MCFxxxx_CANx_RX15MASK 0x0018
|
| 1595 |
|
|
# define HAL_MCFxxxx_CANx_ERRCNT 0x001C
|
| 1596 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT 0x0020
|
| 1597 |
|
|
# define HAL_MCFxxxx_CANx_IMASK 0x0028
|
| 1598 |
|
|
# define HAL_MCFxxxx_CANx_IFLAG 0x0030
|
| 1599 |
|
|
# define HAL_MCFxxxx_CANx_BUF 0x0080
|
| 1600 |
|
|
|
| 1601 |
|
|
# define HAL_MCFxxxx_CANx_MCR_MDIS (0x01 << 31)
|
| 1602 |
|
|
# define HAL_MCFxxxx_CANx_MCR_FRZ (0x01 << 30)
|
| 1603 |
|
|
# define HAL_MCFxxxx_CANx_MCR_HALT (0x01 << 28)
|
| 1604 |
|
|
# define HAL_MCFxxxx_CANx_MCR_NOTRDY (0x01 << 27)
|
| 1605 |
|
|
# define HAL_MCFxxxx_CANx_MCR_SOFTRST (0x01 << 25)
|
| 1606 |
|
|
# define HAL_MCFxxxx_CANx_MCR_FRZACK (0x01 << 24)
|
| 1607 |
|
|
# define HAL_MCFxxxx_CANx_MCR_SUPV (0x01 << 23)
|
| 1608 |
|
|
# define HAL_MCFxxxx_CANx_MCR_LPMACK (0x01 << 20)
|
| 1609 |
|
|
# define HAL_MCFxxxx_CANx_MCR_MAXMB_MASK (0x0F << 0)
|
| 1610 |
|
|
# define HAL_MCFxxxx_CANx_MCR_MAXMB_SHIFT 0
|
| 1611 |
|
|
|
| 1612 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PRESDIV_MASK (0x00FF << 24)
|
| 1613 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PRESDIV_SHIFT 24
|
| 1614 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_RJW_MASK (0x03 << 22)
|
| 1615 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_RJW_SHIFT 22
|
| 1616 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PSEG1_MASK (0x07 << 19)
|
| 1617 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PSEG1_SHIFT 19
|
| 1618 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PSEG2_MASK (0x07 << 16)
|
| 1619 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PSEG2_SHIFT 16
|
| 1620 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_BOFFMSK (0x01 << 15)
|
| 1621 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_ERRMSK (0x01 << 14)
|
| 1622 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_CLKSRC (0x01 << 13)
|
| 1623 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_LPB (0x01 << 12)
|
| 1624 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_SMP (0x01 << 7)
|
| 1625 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_BOFFREC (0x01 << 6)
|
| 1626 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_TSYN (0x01 << 5)
|
| 1627 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_LBUF (0x01 << 4)
|
| 1628 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_LOM (0x01 << 3)
|
| 1629 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PROPSEG_MASK (0x07 << 0)
|
| 1630 |
|
|
# define HAL_MCFxxxx_CANx_CTRL_PROPSEG_SHIFT 0
|
| 1631 |
|
|
|
| 1632 |
|
|
# define HAL_MCFxxxx_CANx_ERRCNT_RXECTR_MASK (0x00FF << 8)
|
| 1633 |
|
|
# define HAL_MCFxxxx_CANx_ERRCNT_RXECTR_SHIFT 8
|
| 1634 |
|
|
# define HAL_MCFxxxx_CANx_ERRCNT_TXECTR_MASK (0x00FF << 0)
|
| 1635 |
|
|
# define HAL_MCFxxxx_CANx_ERRCNT_TXECTR_SHIFT 0
|
| 1636 |
|
|
|
| 1637 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_BIT1ERR (0x01 << 15)
|
| 1638 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_BIT0ERR (0x01 << 14)
|
| 1639 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_ACKERR (0x01 << 13)
|
| 1640 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_CRCERR (0x01 << 12)
|
| 1641 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_FRMERR (0x01 << 11)
|
| 1642 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_STFERR (0x01 << 10)
|
| 1643 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_TXWRN (0x01 << 9)
|
| 1644 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_RXWRN (0x01 << 8)
|
| 1645 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_IDLE (0x01 << 7)
|
| 1646 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_TXRX (0x01 << 6)
|
| 1647 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_FLTCONF_MASK (0x03 << 4)
|
| 1648 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_FLTCONF_SHIFT 4
|
| 1649 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_BOFFINT (0x01 << 2)
|
| 1650 |
|
|
# define HAL_MCFxxxx_CANx_ERRSTAT_ERRINT (0x01 << 1)
|
| 1651 |
|
|
#endif
|
| 1652 |
|
|
|
| 1653 |
|
|
// ----------------------------------------------------------------------------
|
| 1654 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCF5282_QADC
|
| 1655 |
|
|
// Queued analog-to-digital converter
|
| 1656 |
|
|
|
| 1657 |
|
|
// Configuration register, 16 bits
|
| 1658 |
|
|
# define HAL_MCFxxxx_QADC_QADCMCR 0x0000
|
| 1659 |
|
|
// Test register, 16 bits. This is only usable in factory test mode
|
| 1660 |
|
|
# define HAL_MCFxxxx_QADC_QADCTEST 0x0002
|
| 1661 |
|
|
// Two port data registers, 8 bits each
|
| 1662 |
|
|
# define HAL_MCFxxxx_QADC_PORTQA 0x0006
|
| 1663 |
|
|
# define HAL_MCFxxxx_QADC_PORTQB 0x0007
|
| 1664 |
|
|
// Two port direction registers, 8 bits each
|
| 1665 |
|
|
# define HAL_MCFxxxx_QADC_DDRQA 0x0008
|
| 1666 |
|
|
# define HAL_MCFxxxx_QADC_DDRQB 0x0009
|
| 1667 |
|
|
// Three control registers, 16 bits each
|
| 1668 |
|
|
# define HAL_MCFxxxx_QADC_QACR0 0x000A
|
| 1669 |
|
|
# define HAL_MCFxxxx_QADC_QACR1 0x000C
|
| 1670 |
|
|
# define HAL_MCFxxxx_QADC_QACR2 0x000E
|
| 1671 |
|
|
// Two status registers, 16 bits each
|
| 1672 |
|
|
# define HAL_MCFxxxx_QADC_QASR0 0x0010
|
| 1673 |
|
|
# define HAL_MCFxxxx_QADC_QASR1 0x0012
|
| 1674 |
|
|
// Command word table, 64 entries * 16 bits each
|
| 1675 |
|
|
# define HAL_MCFxxxx_QADC_CCW 0x0200
|
| 1676 |
|
|
// Right-justified unsigned results, 64 entries * 16 bits
|
| 1677 |
|
|
# define HAL_MCFxxxx_QADC_RJURR 0x0280
|
| 1678 |
|
|
// Left-justified signed results, 64 entries * 16 bits
|
| 1679 |
|
|
# define HAL_MCFxxxx_QADC_LJSRR 0x0300
|
| 1680 |
|
|
// Left-justified unsigned results, 64 entries * 16 bits
|
| 1681 |
|
|
# define HAL_MCFxxxx_QADC_LJURR 0x0380
|
| 1682 |
|
|
|
| 1683 |
|
|
# define HAL_MCFxxxx_QADC_QADCMCR_QSTOP (0x01 << 15)
|
| 1684 |
|
|
# define HAL_MCFxxxx_QADC_QADCMCR_QDBG (0x01 << 14)
|
| 1685 |
|
|
# define HAL_MCFxxxx_QADC_QADCMCR_QSUPV (0x01 << 7)
|
| 1686 |
|
|
|
| 1687 |
|
|
// The port data and direction registers just provide control
|
| 1688 |
|
|
// over four signals apiece.
|
| 1689 |
|
|
|
| 1690 |
|
|
# define HAL_MCFxxxx_QADC_QACR0_MUX (0x01 << 15)
|
| 1691 |
|
|
# define HAL_MCFxxxx_QADC_QACR0_TRG (0x01 << 14)
|
| 1692 |
|
|
# define HAL_MCFxxxx_QADC_QACR0_QPR_MASK (0x7F << 0)
|
| 1693 |
|
|
# define HAL_MCFxxxx_QADC_QACR0_QPR_SHIFT 0
|
| 1694 |
|
|
// The actual prescaler is (2 * (QPR+1)), except for a QPR value
|
| 1695 |
|
|
// of 0 which gives a prescaler of 4.
|
| 1696 |
|
|
|
| 1697 |
|
|
// QACR1 and QACR2 control queues 1 and 2 respectively
|
| 1698 |
|
|
# define HAL_MCFxxxx_QADC_QACRn_CIE (0x01 << 15)
|
| 1699 |
|
|
# define HAL_MCFxxxx_QADC_QACRn_PIE (0x01 << 14)
|
| 1700 |
|
|
# define HAL_MCFxxxx_QADC_QACRn_SSE (0x01 << 13)
|
| 1701 |
|
|
# define HAL_MCFxxxx_QADC_QACRn_MQ_MASK (0x1F << 8)
|
| 1702 |
|
|
# define HAL_MCFxxxx_QADC_QACRn_MQ_SHIFT 8
|
| 1703 |
|
|
// There are 32 different modes, see the manual for details.
|
| 1704 |
|
|
|
| 1705 |
|
|
// QACR2 has some additional bits to support resume operations
|
| 1706 |
|
|
# define HAL_MCFxxxx_QADC_QACR2_RESUME (0x01 << 7)
|
| 1707 |
|
|
# define HAL_MCFxxxx_QADC_QACR2_BQ_MASK (0x7F << 0)
|
| 1708 |
|
|
# define HAL_MCFxxxx_QADC_QACR2_BQ_SHIFT 0
|
| 1709 |
|
|
|
| 1710 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_CF1 (0x01 << 15)
|
| 1711 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_PF1 (0x01 << 14)
|
| 1712 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_CF2 (0x01 << 13)
|
| 1713 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_PF2 (0x01 << 12)
|
| 1714 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_TOR1 (0x01 << 11)
|
| 1715 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_TOR2 (0x01 << 10)
|
| 1716 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_MASK (0x0F << 6)
|
| 1717 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_SHIFT 6
|
| 1718 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_IDLE (0x00 << 6)
|
| 1719 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_PAUSED (0x01 << 6)
|
| 1720 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_ACTIVE (0x02 << 6)
|
| 1721 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_IDLE_PENDING (0x03 << 6)
|
| 1722 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_IDLE (0x04 << 6)
|
| 1723 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_PAUSED (0x05 << 6)
|
| 1724 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_ACTIVE (0x06 << 6)
|
| 1725 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_PAUSED_PENDING (0x07 << 6)
|
| 1726 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_IDLE (0x08 << 6)
|
| 1727 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_PAUSED (0x09 << 6)
|
| 1728 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_SUSPENDED (0x0A << 6)
|
| 1729 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_QS_ACTIVE_PENDING (0x0B << 6)
|
| 1730 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_CWP_MASK (0x3F << 0)
|
| 1731 |
|
|
# define HAL_MCFxxxx_QADC_QASR0_CWP_SHIFT 0
|
| 1732 |
|
|
|
| 1733 |
|
|
# define HAL_MCFxxxx_QADC_QASR1_CWPQ1_MASK (0x3F << 8)
|
| 1734 |
|
|
# define HAL_MCFxxxx_QADC_QASR1_CWPQ1_SHIFT 8
|
| 1735 |
|
|
# define HAL_MCFxxxx_QADC_QASR1_CWPQ_MASK (0x3F << 0)
|
| 1736 |
|
|
# define HAL_MCFxxxx_QADC_QASR1_CWPQ_SHIFT 0
|
| 1737 |
|
|
|
| 1738 |
|
|
# define HAL_MCFxxxx_QADC_CCW_PAUSE (0x01 << 9)
|
| 1739 |
|
|
# define HAL_MCFxxxx_QADC_CCW_BYP (0x01 << 8)
|
| 1740 |
|
|
# define HAL_MCFxxxx_QADC_CCW_IST_MASK (0x03 << 6)
|
| 1741 |
|
|
# define HAL_MCFxxxx_QADC_CCW_IST_SHIFT 6
|
| 1742 |
|
|
# define HAL_MCFxxxx_QADC_CCW_IST_2 (0x00 << 6)
|
| 1743 |
|
|
# define HAL_MCFxxxx_QADC_CCW_IST_4 (0x01 << 6)
|
| 1744 |
|
|
# define HAL_MCFxxxx_QADC_CCW_IST_8 (0x02 << 6)
|
| 1745 |
|
|
# define HAL_MCFxxxx_QADC_CCW_IST_16 (0x03 << 6)
|
| 1746 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_MASK (0x3F << 0)
|
| 1747 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_SHIFT 0
|
| 1748 |
|
|
|
| 1749 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN0 0
|
| 1750 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN1 1
|
| 1751 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN2 2
|
| 1752 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN3 3
|
| 1753 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN52 52
|
| 1754 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN53 53
|
| 1755 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN55 55
|
| 1756 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_AN56 56
|
| 1757 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_ETRIG1 55
|
| 1758 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_ETRIG2 56
|
| 1759 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_LOWREF 60
|
| 1760 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_HIGHREF 61
|
| 1761 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_MIDREF 62
|
| 1762 |
|
|
# define HAL_MCFxxxx_QADC_CCW_CHAN_EOQ 63
|
| 1763 |
|
|
|
| 1764 |
|
|
#endif // HAL_MCFxxxx_HAS_MCF5282_QADC
|
| 1765 |
|
|
|
| 1766 |
|
|
// ----------------------------------------------------------------------------
|
| 1767 |
|
|
// Pulse width modulation unit.
|
| 1768 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCFxxxx_PWM
|
| 1769 |
|
|
# define HAL_MCFxxxx_PWMx_PWME 0x0000
|
| 1770 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPOL 0x0001
|
| 1771 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCLK 0x0002
|
| 1772 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPRCLK 0x0003
|
| 1773 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCAE 0x0004
|
| 1774 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCTL 0x0005
|
| 1775 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSCLA 0x0008
|
| 1776 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSCLB 0x0009
|
| 1777 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT0 0x000C
|
| 1778 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT1 0x000D
|
| 1779 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT2 0x000E
|
| 1780 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT3 0x000F
|
| 1781 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT4 0x0010
|
| 1782 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT5 0x0011
|
| 1783 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT6 0x0012
|
| 1784 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCNT7 0x0013
|
| 1785 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER0 0x0014
|
| 1786 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER1 0x0015
|
| 1787 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER2 0x0016
|
| 1788 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER3 0x0017
|
| 1789 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER4 0x0018
|
| 1790 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER5 0x0019
|
| 1791 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER6 0x001A
|
| 1792 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPER7 0x001B
|
| 1793 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY0 0x001C
|
| 1794 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY1 0x001D
|
| 1795 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY2 0x001E
|
| 1796 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY3 0x001F
|
| 1797 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY4 0x0020
|
| 1798 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY5 0x0021
|
| 1799 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY6 0x0022
|
| 1800 |
|
|
# define HAL_MCFxxxx_PWMx_PWMDTY7 0x0023
|
| 1801 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN 0x0024
|
| 1802 |
|
|
|
| 1803 |
|
|
# define HAL_MCFxxxx_PWMx_PWME_PWME7 (0x01 << 7)
|
| 1804 |
|
|
# define HAL_MCFxxxx_PWMx_PWME_PWME5 (0x01 << 5)
|
| 1805 |
|
|
# define HAL_MCFxxxx_PWMx_PWME_PWME3 (0x01 << 3)
|
| 1806 |
|
|
# define HAL_MCFxxxx_PWMx_PWME_PWME1 (0x01 << 1)
|
| 1807 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL7 (0x01 << 7)
|
| 1808 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL5 (0x01 << 5)
|
| 1809 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL3 (0x01 << 3)
|
| 1810 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPOL_PPOL1 (0x01 << 1)
|
| 1811 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK7 (0x01 << 7)
|
| 1812 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK5 (0x01 << 5)
|
| 1813 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK3 (0x01 << 3)
|
| 1814 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCLK_PCLK1 (0x01 << 1)
|
| 1815 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKB_MASK (0x07 << 4)
|
| 1816 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKB_SHIFT 4
|
| 1817 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKA_MASK (0x07 << 0)
|
| 1818 |
|
|
# define HAL_MCFxxxx_PWMx_PWMPRCLK_PCKA_SHIFT 0
|
| 1819 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCAE_CAE7 (0x01 << 7)
|
| 1820 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCAE_CAE5 (0x01 << 5)
|
| 1821 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCAE_CAE3 (0x01 << 3)
|
| 1822 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCAE_CAE1 (0x01 << 1)
|
| 1823 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCTL_CON67 (0x01 << 7)
|
| 1824 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCTL_CON45 (0x01 << 6)
|
| 1825 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCTL_CON23 (0x01 << 5)
|
| 1826 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCTL_CON01 (0x01 << 4)
|
| 1827 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCTL_PSWAI (0x01 << 3)
|
| 1828 |
|
|
# define HAL_MCFxxxx_PWMx_PWMCTL_PFRZ (0x01 << 2)
|
| 1829 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN_IF (0x01 << 7)
|
| 1830 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN_IE (0x01 << 6)
|
| 1831 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN_RESTART (0x01 << 5)
|
| 1832 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN_LVL (0x01 << 4)
|
| 1833 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN_PWM7IN (0x01 << 2)
|
| 1834 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN_PWM7IL (0x01 << 1)
|
| 1835 |
|
|
# define HAL_MCFxxxx_PWMx_PWMSDN_SDNEN (0x01 << 0)
|
| 1836 |
|
|
#endif // HAS_MCFxxxx_PWM
|
| 1837 |
|
|
|
| 1838 |
|
|
// ----------------------------------------------------------------------------
|
| 1839 |
|
|
// Real-time clock.
|
| 1840 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCFxxxx_RTC
|
| 1841 |
|
|
# define HAL_MCFxxxx_RTC_HOURMIN 0x00
|
| 1842 |
|
|
# define HAL_MCFxxxx_RTC_SECONDS 0x04
|
| 1843 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_HM 0x08
|
| 1844 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_SEC 0x0C
|
| 1845 |
|
|
# define HAL_MCFxxxx_RTC_CR 0x10
|
| 1846 |
|
|
# define HAL_MCFxxxx_RTC_ISR 0x14
|
| 1847 |
|
|
# define HAL_MCFxxxx_RTC_IER 0x18
|
| 1848 |
|
|
# define HAL_MCFxxxx_RTC_STPWCH 0x1C
|
| 1849 |
|
|
# define HAL_MCFxxxx_RTC_DAYS 0x20
|
| 1850 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_DAY 0x24
|
| 1851 |
|
|
|
| 1852 |
|
|
# define HAL_MCFxxxx_RTC_HOURMIN_HOURS_MASK (0x1F << 8)
|
| 1853 |
|
|
# define HAL_MCFxxxx_RTC_HOURMIN_HOURS_SHIFT 8
|
| 1854 |
|
|
# define HAL_MCFxxxx_RTC_HOURMIN_MINUTES_MASK (0x3F << 0)
|
| 1855 |
|
|
# define HAL_MCFxxxx_RTC_HOURMIN_MINUTES_SHIFT 0
|
| 1856 |
|
|
# define HAL_MCFxxxx_RTC_SECONDS_SECONDS_MASK (0x3F << 0)
|
| 1857 |
|
|
# define HAL_MCFxxxx_RTC_SECONDS_SECONDS_SHIFT 0
|
| 1858 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_HM_HOURS_MASK (0x1F << 8)
|
| 1859 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_HM_HOURS_SHIFT 8
|
| 1860 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_HM_MINUTES_MASK (0x3F << 0)
|
| 1861 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_HM_MINUTES_SHIFT 0
|
| 1862 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_SEC_SECONDS_MASK (0x3F << 0)
|
| 1863 |
|
|
# define HAL_MCFxxxx_RTC_ALARM_SEC_SECONDS_SHIFT 0
|
| 1864 |
|
|
# define HAL_MCFxxxx_RTC_CR_EN (0x01 << 7)
|
| 1865 |
|
|
# define HAL_MCFxxxx_RTC_CR_XTL_MASK (0x03 << 5)
|
| 1866 |
|
|
# define HAL_MCFxxxx_RTC_CR_XTL_SHIFT 5
|
| 1867 |
|
|
# define HAL_MCFxxxx_RTC_CR_XTL_32768 (0x00 << 5)
|
| 1868 |
|
|
# define HAL_MCFxxxx_RTC_CR_XTL_32000 (0x01 << 5)
|
| 1869 |
|
|
# define HAL_MCFxxxx_RTC_CR_XTL_38400 (0x02 << 5)
|
| 1870 |
|
|
# define HAL_MCFxxxx_RTC_CR_SWR (0x01 << 0)
|
| 1871 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM7 (0x01 << 15)
|
| 1872 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM6 (0x01 << 14)
|
| 1873 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM5 (0x01 << 13)
|
| 1874 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM4 (0x01 << 12)
|
| 1875 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM3 (0x01 << 11)
|
| 1876 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM2 (0x01 << 10)
|
| 1877 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM1 (0x01 << 9)
|
| 1878 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SAM0 (0x01 << 8)
|
| 1879 |
|
|
# define HAL_MCFxxxx_RTC_ISR_2HZ (0x01 << 7)
|
| 1880 |
|
|
# define HAL_MCFxxxx_RTC_ISR_HR (0x01 << 5)
|
| 1881 |
|
|
# define HAL_MCFxxxx_RTC_ISR_1HZ (0x01 << 4)
|
| 1882 |
|
|
# define HAL_MCFxxxx_RTC_ISR_DAY (0x01 << 3)
|
| 1883 |
|
|
# define HAL_MCFxxxx_RTC_ISR_ALM (0x01 << 2)
|
| 1884 |
|
|
# define HAL_MCFxxxx_RTC_ISR_MIN (0x01 << 1)
|
| 1885 |
|
|
# define HAL_MCFxxxx_RTC_ISR_SW (0x01 << 0)
|
| 1886 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM7 (0x01 << 15)
|
| 1887 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM6 (0x01 << 14)
|
| 1888 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM5 (0x01 << 13)
|
| 1889 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM4 (0x01 << 12)
|
| 1890 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM3 (0x01 << 11)
|
| 1891 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM2 (0x01 << 10)
|
| 1892 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM1 (0x01 << 9)
|
| 1893 |
|
|
# define HAL_MCFxxxx_RTC_IER_SAM0 (0x01 << 8)
|
| 1894 |
|
|
# define HAL_MCFxxxx_RTC_IER_2HZ (0x01 << 7)
|
| 1895 |
|
|
# define HAL_MCFxxxx_RTC_IER_HR (0x01 << 5)
|
| 1896 |
|
|
# define HAL_MCFxxxx_RTC_IER_1HZ (0x01 << 4)
|
| 1897 |
|
|
# define HAL_MCFxxxx_RTC_IER_DAY (0x01 << 3)
|
| 1898 |
|
|
# define HAL_MCFxxxx_RTC_IER_ALM (0x01 << 2)
|
| 1899 |
|
|
# define HAL_MCFxxxx_RTC_IER_MIN (0x01 << 1)
|
| 1900 |
|
|
# define HAL_MCFxxxx_RTC_IER_SW (0x01 << 0)
|
| 1901 |
|
|
# define HAL_MCFxxxx_RTC_STPWCH_CNT_MASK (0x3F << 0)
|
| 1902 |
|
|
# define HAL_MCFxxxx_RTC_STPWCH_CNT_SHIFT 0
|
| 1903 |
|
|
# define HAL_MCFxxxx_RTC_DAYS_DAYS_MASK (0x00FFFF << 0)
|
| 1904 |
|
|
# define HAL_MCFxxxx_RTC_DAYS_DAYS_SHIFT 0
|
| 1905 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_DAY_DAYS_MASK (0x00FFFF << 0)
|
| 1906 |
|
|
# define HAL_MCFxxxx_RTC_ALRM_DAY_DAYS_SHIFT 0
|
| 1907 |
|
|
#endif // HAS_MCFxxxx_RTC
|
| 1908 |
|
|
|
| 1909 |
|
|
// ----------------------------------------------------------------------------
|
| 1910 |
|
|
// Message digest hardware
|
| 1911 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCFxxxx_MDHA
|
| 1912 |
|
|
# define HAL_MCFxxxx_MDHA_MR 0x0000
|
| 1913 |
|
|
# define HAL_MCFxxxx_MDHA_CR 0x0004
|
| 1914 |
|
|
# define HAL_MCFxxxx_MDHA_CMR 0x0008
|
| 1915 |
|
|
# define HAL_MCFxxxx_MDHA_SR 0x000C
|
| 1916 |
|
|
# define HAL_MCFxxxx_MDHA_ISR 0x0010
|
| 1917 |
|
|
# define HAL_MCFxxxx_MDHA_IMR 0x0014
|
| 1918 |
|
|
# define HAL_MCFxxxx_MDHA_DSR 0x001C
|
| 1919 |
|
|
# define HAL_MCFxxxx_MDHA_MIN 0x0020
|
| 1920 |
|
|
# define HAL_MCFxxxx_MDHA_A0 0x0030
|
| 1921 |
|
|
# define HAL_MCFxxxx_MDHA_B0 0x0034
|
| 1922 |
|
|
# define HAL_MCFxxxx_MDHA_C0 0x0038
|
| 1923 |
|
|
# define HAL_MCFxxxx_MDHA_D0 0x003C
|
| 1924 |
|
|
# define HAL_MCFxxxx_MDHA_E0 0x0040
|
| 1925 |
|
|
# define HAL_MCFxxxx_MDHA_MDS 0x0044
|
| 1926 |
|
|
# define HAL_MCFxxxx_MDHA_A1 0x0070
|
| 1927 |
|
|
# define HAL_MCFxxxx_MDHA_B1 0x0074
|
| 1928 |
|
|
# define HAL_MCFxxxx_MDHA_C1 0x0078
|
| 1929 |
|
|
# define HAL_MCFxxxx_MDHA_D1 0x007C
|
| 1930 |
|
|
# define HAL_MCFxxxx_MDHA_E1 0x0080
|
| 1931 |
|
|
|
| 1932 |
|
|
# define HAL_MCFxxxx_MDHA_MR_SSL (0x01 << 10)
|
| 1933 |
|
|
# define HAL_MCFxxxx_MDHA_MR_MACFULL (0x01 << 9)
|
| 1934 |
|
|
# define HAL_MCFxxxx_MDHA_MR_SWAP (0x01 << 8)
|
| 1935 |
|
|
# define HAL_MCFxxxx_MDHA_MR_OPAD (0x01 << 7)
|
| 1936 |
|
|
# define HAL_MCFxxxx_MDHA_MR_IPAD (0x01 << 6)
|
| 1937 |
|
|
# define HAL_MCFxxxx_MDHA_MR_INIT (0x01 << 5)
|
| 1938 |
|
|
# define HAL_MCFxxxx_MDHA_MR_MAC_MASK (0x03 << 3)
|
| 1939 |
|
|
# define HAL_MCFxxxx_MDHA_MR_MAC_SHIFT 3
|
| 1940 |
|
|
# define HAL_MCFxxxx_MDHA_MR_MAC_NONE (0x00 << 3)
|
| 1941 |
|
|
# define HAL_MCFxxxx_MDHA_MR_MAC_HMAC (0x01 << 3)
|
| 1942 |
|
|
# define HAL_MCFxxxx_MDHA_MR_MAC_EHMAC (0x02 << 3)
|
| 1943 |
|
|
# define HAL_MCFxxxx_MDHA_MR_PDATA (0x01 << 2)
|
| 1944 |
|
|
# define HAL_MCFxxxx_MDHA_MR_ALG (0x01 << 0)
|
| 1945 |
|
|
# define HAL_MCFxxxx_MDHA_CR_DMAL_MASK (0x1F << 16)
|
| 1946 |
|
|
# define HAL_MCFxxxx_MDHA_CR_DMAL_SHIFT 16
|
| 1947 |
|
|
# define HAL_MCFxxxx_MDHA_CR_END (0x01 << 2)
|
| 1948 |
|
|
# define HAL_MCFxxxx_MDHA_CR_DMA (0x01 << 2)
|
| 1949 |
|
|
# define HAL_MCFxxxx_MDHA_CR_IE (0x01 << 2)
|
| 1950 |
|
|
# define HAL_MCFxxxx_MDHA_CMR_GO (0x01 << 3)
|
| 1951 |
|
|
# define HAL_MCFxxxx_MDHA_CMR_CI (0x01 << 2)
|
| 1952 |
|
|
# define HAL_MCFxxxx_MDHA_CMR_RI (0x01 << 1)
|
| 1953 |
|
|
# define HAL_MCFxxxx_MDHA_CMR_SWR (0x01 << 0)
|
| 1954 |
|
|
# define HAL_MCFxxxx_MDHA_SR_IFL_MASK (0x00FF << 16)
|
| 1955 |
|
|
# define HAL_MCFxxxx_MDHA_SR_IFL_SHIFT 16
|
| 1956 |
|
|
# define HAL_MCFxxxx_MDHA_SR_APD_MASK (0x07 << 13)
|
| 1957 |
|
|
# define HAL_MCFxxxx_MDHA_SR_APD_SHIFT 13
|
| 1958 |
|
|
# define HAL_MCFxxxx_MDHA_SR_APD_STANDARD (0x00 << 13)
|
| 1959 |
|
|
# define HAL_MCFxxxx_MDHA_SR_APD_PAD_LAST_WORD (0x01 << 13)
|
| 1960 |
|
|
# define HAL_MCFxxxx_MDHA_SR_APD_ADD_A_WORD (0x02 << 13)
|
| 1961 |
|
|
# define HAL_MCFxxxx_MDHA_SR_APD_LAST_HASH (0x03 << 13)
|
| 1962 |
|
|
# define HAL_MCFxxxx_MDHA_SR_APD_STALL_STATE (0x04 << 13)
|
| 1963 |
|
|
# define HAL_MCFxxxx_MDHA_SR_FS_MASK (0x07 << 8)
|
| 1964 |
|
|
# define HAL_MCFxxxx_MDHA_SR_FS_SHIFT 8
|
| 1965 |
|
|
# define HAL_MCFxxxx_MDHA_SR_GNW (0x01 << 7)
|
| 1966 |
|
|
# define HAL_MCFxxxx_MDHA_SR_HSH (0x01 << 6)
|
| 1967 |
|
|
# define HAL_MCFxxxx_MDHA_SR_BUSY (0x01 << 4)
|
| 1968 |
|
|
# define HAL_MCFxxxx_MDHA_SR_RD (0x01 << 3)
|
| 1969 |
|
|
# define HAL_MCFxxxx_MDHA_SR_ERR (0x01 << 2)
|
| 1970 |
|
|
# define HAL_MCFxxxx_MDHA_SR_DONE (0x01 << 1)
|
| 1971 |
|
|
# define HAL_MCFxxxx_MDHA_SR_INT (0x01 << 0)
|
| 1972 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_DRL (0x01 << 10)
|
| 1973 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_GTDS (0x01 << 9)
|
| 1974 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_ERE (0x01 << 8)
|
| 1975 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_RMDP (0x01 << 7)
|
| 1976 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_DSE (0x01 << 5)
|
| 1977 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_IME (0x01 << 4)
|
| 1978 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_NEIF (0x01 << 2)
|
| 1979 |
|
|
# define HAL_MCFxxxx_MDHA_ISR_IFO (0x01 << 0)
|
| 1980 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_DRL (0x01 << 10)
|
| 1981 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_GTDS (0x01 << 9)
|
| 1982 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_ERE (0x01 << 8)
|
| 1983 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_RMDP (0x01 << 7)
|
| 1984 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_DSE (0x01 << 5)
|
| 1985 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_IME (0x01 << 4)
|
| 1986 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_NEIF (0x01 << 2)
|
| 1987 |
|
|
# define HAL_MCFxxxx_MDHA_IMR_IFO (0x01 << 0)
|
| 1988 |
|
|
#endif // HAS_MCFxxxx_MDHA
|
| 1989 |
|
|
|
| 1990 |
|
|
// ----------------------------------------------------------------------------
|
| 1991 |
|
|
// Random number generation
|
| 1992 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCFxxxx_RNG
|
| 1993 |
|
|
# define HAL_MCFxxxx_RNG_CR 0x00000000
|
| 1994 |
|
|
# define HAL_MCFxxxx_RNG_SR 0x00000004
|
| 1995 |
|
|
# define HAL_MCFxxxx_RNG_ER 0x00000008
|
| 1996 |
|
|
# define HAL_MCFxxxx_RNG_OUT 0x0000000C
|
| 1997 |
|
|
|
| 1998 |
|
|
# define HAL_MCFxxxx_RNG_CR_CI (0x01 << 3)
|
| 1999 |
|
|
# define HAL_MCFxxxx_RNG_CR_IM (0x01 << 2)
|
| 2000 |
|
|
# define HAL_MCFxxxx_RNG_CR_HA (0x01 << 1)
|
| 2001 |
|
|
# define HAL_MCFxxxx_RNG_CR_GO (0x01 << 0)
|
| 2002 |
|
|
# define HAL_MCFxxxx_RNG_SR_OFS_MASK (0x00FF << 16)
|
| 2003 |
|
|
# define HAL_MCFxxxx_RNG_SR_OFS_SHIFT 16
|
| 2004 |
|
|
# define HAL_MCFxxxx_RNG_SR_OFL_MASK (0x00FF << 8)
|
| 2005 |
|
|
# define HAL_MCFxxxx_RNG_SR_OFL_SHIFT 8
|
| 2006 |
|
|
# define HAL_MCFxxxx_RNG_SR_EI (0x01 << 3)
|
| 2007 |
|
|
# define HAL_MCFxxxx_RNG_SR_FUF (0x01 << 2)
|
| 2008 |
|
|
# define HAL_MCFxxxx_RNG_SR_LRS (0x01 << 1)
|
| 2009 |
|
|
# define HAL_MCFxxxx_RNG_SR_SR (0x01 << 0)
|
| 2010 |
|
|
#endif // HAS_MCFxxxx_RNG
|
| 2011 |
|
|
|
| 2012 |
|
|
// ----------------------------------------------------------------------------
|
| 2013 |
|
|
// Symmetric key hardware
|
| 2014 |
|
|
#ifdef HAL_MCFxxxx_HAS_MCFxxxx_SKHA
|
| 2015 |
|
|
|
| 2016 |
|
|
# define HAL_MCFxxxx_SKHA_MR 0x00000000
|
| 2017 |
|
|
# define HAL_MCFxxxx_SKHA_CR 0x00000004
|
| 2018 |
|
|
# define HAL_MCFxxxx_SKHA_CMR 0x00000008
|
| 2019 |
|
|
# define HAL_MCFxxxx_SKHA_SR 0x0000000C
|
| 2020 |
|
|
# define HAL_MCFxxxx_SKHA_ESR 0x00000010
|
| 2021 |
|
|
# define HAL_MCFxxxx_SKHA_EMR 0x00000014
|
| 2022 |
|
|
# define HAL_MCFxxxx_SKHA_KSR 0x00000018
|
| 2023 |
|
|
# define HAL_MCFxxxx_SKHA_DSR 0x0000001C
|
| 2024 |
|
|
# define HAL_MCFxxxx_SKHA_IN 0x00000020
|
| 2025 |
|
|
# define HAL_MCFxxxx_SKHA_OUT 0x00000024
|
| 2026 |
|
|
# define HAL_MCFxxxx_SKHA_KDR1 0x00000030
|
| 2027 |
|
|
# define HAL_MCFxxxx_SKHA_KDR2 0x00000034
|
| 2028 |
|
|
# define HAL_MCFxxxx_SKHA_KDR3 0x00000038
|
| 2029 |
|
|
# define HAL_MCFxxxx_SKHA_KDR4 0x0000003C
|
| 2030 |
|
|
# define HAL_MCFxxxx_SKHA_KDR5 0x00000040
|
| 2031 |
|
|
# define HAL_MCFxxxx_SKHA_KDR6 0x00000044
|
| 2032 |
|
|
# define HAL_MCFxxxx_SKHA_C1 0x00000070
|
| 2033 |
|
|
# define HAL_MCFxxxx_SKHA_C2 0x00000074
|
| 2034 |
|
|
# define HAL_MCFxxxx_SKHA_C3 0x00000078
|
| 2035 |
|
|
# define HAL_MCFxxxx_SKHA_C4 0x0000007C
|
| 2036 |
|
|
# define HAL_MCFxxxx_SKHA_C5 0x00000080
|
| 2037 |
|
|
# define HAL_MCFxxxx_SKHA_C6 0x00000084
|
| 2038 |
|
|
# define HAL_MCFxxxx_SKHA_C7 0x00000088
|
| 2039 |
|
|
# define HAL_MCFxxxx_SKHA_C8 0x0000008C
|
| 2040 |
|
|
# define HAL_MCFxxxx_SKHA_C9 0x00000090
|
| 2041 |
|
|
# define HAL_MCFxxxx_SKHA_C10 0x00000094
|
| 2042 |
|
|
# define HAL_MCFxxxx_SKHA_C11 0x00000098
|
| 2043 |
|
|
|
| 2044 |
|
|
# define HAL_MCFxxxx_SKHA_MR_CTRM_MASK (0x0F << 9)
|
| 2045 |
|
|
# define HAL_MCFxxxx_SKHA_MR_CTRM_SHIFT 9
|
| 2046 |
|
|
# define HAL_MCFxxxx_SKHA_MR_DKP (0x01 << 8)
|
| 2047 |
|
|
# define HAL_MCFxxxx_SKHA_MR_CM_MASK (0x03 << 3)
|
| 2048 |
|
|
# define HAL_MCFxxxx_SKHA_MR_CM_SHIFT 3
|
| 2049 |
|
|
# define HAL_MCFxxxx_SKHA_MR_CM_ECB (0x00 << 3)
|
| 2050 |
|
|
# define HAL_MCFxxxx_SKHA_MR_CM_CBC (0x01 << 3)
|
| 2051 |
|
|
# define HAL_MCFxxxx_SKHA_MR_CM_CTR (0x03 << 3)
|
| 2052 |
|
|
# define HAL_MCFxxxx_SKHA_MR_DIR (0x01 << 2)
|
| 2053 |
|
|
# define HAL_MCFxxxx_SKHA_MR_ALG_MASK (0x03 << 0)
|
| 2054 |
|
|
# define HAL_MCFxxxx_SKHA_MR_ALG_SHIFT 0
|
| 2055 |
|
|
# define HAL_MCFxxxx_SKHA_MR_ALG_AES (0x00 << 0)
|
| 2056 |
|
|
# define HAL_MCFxxxx_SKHA_MR_ALG_DES (0x01 << 0)
|
| 2057 |
|
|
# define HAL_MCFxxxx_SKHA_MR_ALG_3DES (0x02 << 0)
|
| 2058 |
|
|
# define HAL_MCFxxxx_SKHA_CR_ODMAL_MASK (0x3F << 24)
|
| 2059 |
|
|
# define HAL_MCFxxxx_SKHA_CR_ODMAL_SHIFT 24
|
| 2060 |
|
|
# define HAL_MCFxxxx_SKHA_CR_IDMAL_MASK (0x3F << 16)
|
| 2061 |
|
|
# define HAL_MCFxxxx_SKHA_CR_IDMAL_SHIFT 16
|
| 2062 |
|
|
# define HAL_MCFxxxx_SKHA_CR_END (0x01 << 3)
|
| 2063 |
|
|
# define HAL_MCFxxxx_SKHA_CR_ODMA (0x01 << 2)
|
| 2064 |
|
|
# define HAL_MCFxxxx_SKHA_CR_IDMA (0x01 << 1)
|
| 2065 |
|
|
# define HAL_MCFxxxx_SKHA_CR_IE (0x01 << 0)
|
| 2066 |
|
|
# define HAL_MCFxxxx_SKHA_CMR_GO (0x01 << 3)
|
| 2067 |
|
|
# define HAL_MCFxxxx_SKHA_CMR_CI (0x01 << 2)
|
| 2068 |
|
|
# define HAL_MCFxxxx_SKHA_CMR_RI (0x01 << 1)
|
| 2069 |
|
|
# define HAL_MCFxxxx_SKHA_CMR_SWR (0x01 << 0)
|
| 2070 |
|
|
# define HAL_MCFxxxx_SKHA_SR_OFL_MASK (0x00FF << 24)
|
| 2071 |
|
|
# define HAL_MCFxxxx_SKHA_SR_OFL_SHIFT 24
|
| 2072 |
|
|
# define HAL_MCFxxxx_SKHA_SR_IFL_MASK (0x00FF << 16)
|
| 2073 |
|
|
# define HAL_MCFxxxx_SKHA_SR_IFL_SHIFT 16
|
| 2074 |
|
|
# define HAL_MCFxxxx_SKHA_SR_BUSY (0x01 << 4)
|
| 2075 |
|
|
# define HAL_MCFxxxx_SKHA_SR_RD (0x01 << 3)
|
| 2076 |
|
|
# define HAL_MCFxxxx_SKHA_SR_ERR (0x01 << 2)
|
| 2077 |
|
|
# define HAL_MCFxxxx_SKHA_SR_DONE (0x01 << 1)
|
| 2078 |
|
|
# define HAL_MCFxxxx_SKHA_SR_INT (0x01 << 0)
|
| 2079 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_DRL (0x01 << 11)
|
| 2080 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_KRE (0x01 << 10)
|
| 2081 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_KPE (0x01 << 9)
|
| 2082 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_ERE (0x01 << 8)
|
| 2083 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_RMDP (0x01 << 7)
|
| 2084 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_KSE (0x01 << 6)
|
| 2085 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_DSE (0x01 << 5)
|
| 2086 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_IME (0x01 << 4)
|
| 2087 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_NEOF (0x01 << 3)
|
| 2088 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_NEIF (0x01 << 2)
|
| 2089 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_OFU (0x01 << 1)
|
| 2090 |
|
|
# define HAL_MCFxxxx_SKHA_ESR_IFO (0x01 << 0)
|
| 2091 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_DRL (0x01 << 11)
|
| 2092 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_KRE (0x01 << 10)
|
| 2093 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_KPE (0x01 << 9)
|
| 2094 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_ERE (0x01 << 8)
|
| 2095 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_RMDP (0x01 << 7)
|
| 2096 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_KSE (0x01 << 6)
|
| 2097 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_DSE (0x01 << 5)
|
| 2098 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_IME (0x01 << 4)
|
| 2099 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_NEOF (0x01 << 3)
|
| 2100 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_NEIF (0x01 << 2)
|
| 2101 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_OFU (0x01 << 1)
|
| 2102 |
|
|
# define HAL_MCFxxxx_SKHA_EMR_IFO (0x01 << 0)
|
| 2103 |
|
|
#endif // HAS_MCFxxxx_SKHA
|
| 2104 |
|
|
|
| 2105 |
|
|
// ----------------------------------------------------------------------------
|
| 2106 |
|
|
// Allow the processor-specific header to override some of the above, if
|
| 2107 |
|
|
// necessary, or to extend the definitions.
|
| 2108 |
|
|
#include <cyg/hal/proc_io.h>
|
| 2109 |
|
|
|
| 2110 |
|
|
//-----------------------------------------------------------------------------
|
| 2111 |
|
|
#endif // CYGONCE_HAL_VAR_IO_H
|
