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skrzyp |
#ifndef CYGONCE_HAL_CACHE_H
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#define CYGONCE_HAL_CACHE_H
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//=============================================================================
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//
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// hal_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg
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// Date: 1998-02-17
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/var_cache.h>
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// Use this macro to allow the assembler to accept "cache" instructions,
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// which are MIPS ISA 3. This is useful if someone is compiling
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// with -mips2, but the architecture is really MIPS ISA 3.
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#define _hal_asm_mips_cpp_stringize( _x_ ) #_x_
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#define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( \
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".set mips" _hal_asm_mips_cpp_stringize(_isal_) )
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//=============================================================================
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// Default Implementation. This uses the standard MIPS CP0 registers and
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// cache instructions. Note that not all variants will have all of the
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// functionality defined here.
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//-----------------------------------------------------------------------------
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// Cache dimensions.
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// These really should be defined in var_cache.h. If they are not, then provide
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// a set of numbers that are typical of many variants.
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#ifndef HAL_DCACHE_SIZE
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// Data cache
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#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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#define HAL_DCACHE_WAYS 2 // Associativity of the cache
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// Instruction cache
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#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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#define HAL_ICACHE_WAYS 2 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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#endif
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// Defines for various R4000+ MIPS cache operations
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// this is a 5 bit field with bits 4-2 defining the operation
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// and bits 1-0 defining which cache is being operated on
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#define HAL_MIPS_CACHE_INDEX_INVALIDATE_I 0x00 /* 0 0 */
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#define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D 0x01 /* 0 1 */
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#define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_S 0x03 /* 0 3 */
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#define HAL_MIPS_CACHE_INDEX_LOAD_TAG_I 0x04 /* 1 0 */
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#define HAL_MIPS_CACHE_INDEX_LOAD_TAG_D 0x05 /* 1 1 */
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#define HAL_MIPS_CACHE_INDEX_LOAD_TAG_S 0x07 /* 1 3 */
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#define HAL_MIPS_CACHE_INDEX_STORE_TAG_I 0x08 /* 2 0 */
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#define HAL_MIPS_CACHE_INDEX_STORE_TAG_D 0x09 /* 2 1 */
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#define HAL_MIPS_CACHE_INDEX_STORE_TAG_S 0x0b /* 2 3 */
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#define HAL_MIPS_CACHE_HIT_INVALIDATE_I 0x10 /* 4 0 */
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#define HAL_MIPS_CACHE_HIT_INVALIDATE_D 0x11 /* 4 1 */
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#define HAL_MIPS_CACHE_HIT_INVALIDATE_S 0x13 /* 4 3 */
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#define HAL_MIPS_CACHE_FILL_I 0x14 /* 5 0 */
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#define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D 0x15 /* 5 1 */
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#define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_S 0x17 /* 5 3 */
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// there seems to be different uses for operation
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// code 6 depending on CPU
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#define HAL_MIPS_CACHE_HIT_WRITEBACK_D 0x19 /* 6 1 */
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#define HAL_MIPS_CACHE_INDEX_LOAD_DATA_I 0x18 /* 6 0 */
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#define HAL_MIPS_CACHE_INDEX_LOAD_DATA_D 0x19 /* 6 1 */
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#define HAL_MIPS_CACHE_INDEX_LOAD_DATA_S 0x1b /* 6 3 */
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// there seems to be different uses for operation
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// code 7 depending on CPU
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#define HAL_MIPS_CACHE_FETCH_AND_LOCK_I 0x1c /* 7 0 */
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#define HAL_MIPS_CACHE_FETCH_AND_LOCK_D 0x1d /* 7 1 */
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#define HAL_MIPS_CACHE_INDEX_STORE_DATA_I 0x1c /* 7 0 */
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#define HAL_MIPS_CACHE_INDEX_STORE_DATA_D 0x1d /* 7 1 */
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#define HAL_MIPS_CACHE_INDEX_STORE_DATA_S 0x1f /* 7 3 */
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//-----------------------------------------------------------------------------
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// Cache instruction uses LSBs or MSBs (depending on the
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// implementation) of the virtual address to specify which WAY to
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// affect. The _ALL_WAYS macro defines the necessary cache instructions
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// to affect all ways.
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#ifdef HAL_MIPS_CACHE_INSN_USES_LSB
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# define _IWAY(_n_) (_n_)
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# define _DWAY(_n_) (_n_)
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#else
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# define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS)
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# define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS)
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#endif
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#if (HAL_DCACHE_WAYS == 1)
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#define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
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asm volatile ("cache %0,0(%1);" \
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: : "I" ((_cmd_) | 1), "r"(_addr_) )
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#elif (HAL_DCACHE_WAYS == 2)
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#define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
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asm volatile ("cache %0,0(%1);" \
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"cache %0,%2(%1);" \
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: : "I" ((_cmd_) | 1), "r"(_addr_), \
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"I" (_DWAY(1)))
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#elif (HAL_DCACHE_WAYS == 4)
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#define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
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asm volatile ("cache %0,0(%1);" \
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"cache %0,%2(%1);" \
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"cache %0,%3(%1);" \
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"cache %0,%4(%1);" \
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: : "I" ((_cmd_) | 1), "r"(_addr_), \
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"I" (_DWAY(1)), \
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"I" (_DWAY(2)), \
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"I" (_DWAY(3)))
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#else
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# error "Unsupported number of ways"
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#endif
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#if (HAL_ICACHE_WAYS == 1)
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#define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
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asm volatile ("cache %0,0(%1);" \
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: : "I" (_cmd_), "r"(_addr_) )
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#elif (HAL_ICACHE_WAYS == 2)
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#define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
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asm volatile ("cache %0,0(%1);" \
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"cache %0,%2(%1);" \
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: : "I" (_cmd_), "r"(_addr_), \
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"I" (_IWAY(1)))
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#elif (HAL_ICACHE_WAYS == 4)
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#define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
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asm volatile ("cache %0,0(%1);" \
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"cache %0,%2(%1);" \
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"cache %0,%3(%1);" \
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"cache %0,%4(%1);" \
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: : "I" (_cmd_), "r"(_addr_), \
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"I" (_IWAY(1)), \
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"I" (_IWAY(2)), \
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"I" (_IWAY(3)))
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#else
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# error "Unsupported number of ways"
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#endif
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//-----------------------------------------------------------------------------
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// Address adjustment.
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// Given an address and a size, these macros return the first
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// cacheline containing the requested range and a terminating address.
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#define HAL_DCACHE_START_ADDRESS(_addr_) \
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(((CYG_ADDRESS)(_addr_)) & ~(HAL_DCACHE_LINE_SIZE-1))
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#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \
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((CYG_ADDRESS)((_addr_) + (_asize_)))
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#define HAL_ICACHE_START_ADDRESS(_addr_) \
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(((CYG_ADDRESS)(_addr_)) & ~(HAL_ICACHE_LINE_SIZE-1))
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#define HAL_ICACHE_END_ADDRESS(_addr_, _asize_) \
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((CYG_ADDRESS)((_addr_) + (_asize_)))
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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// There is no default mechanism for enabling or disabling the caches.
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#ifndef HAL_DCACHE_ENABLE_DEFINED
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#define HAL_DCACHE_ENABLE()
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#endif
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// Disable the data cache
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#ifndef HAL_DCACHE_DISABLE_DEFINED
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#define HAL_DCACHE_DISABLE()
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#endif
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#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
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#define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
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#endif
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// Invalidate the entire cache
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// We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
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// is not quite what we want, but there is no index-invalidate operation
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// available.
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#ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
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#define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
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#endif
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// Synchronize the contents of the cache with memory.
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// This uses the index-writeback-invalidate operation.
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#ifndef HAL_DCACHE_SYNC_DEFINED
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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register CYG_ADDRESS _baddr_ = 0x80000000; \
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register CYG_ADDRESS _addr_ = 0x80000000; \
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register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
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_HAL_ASM_SET_MIPS_ISA(3); \
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for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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{ _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D, _addr_); } \
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_HAL_ASM_SET_MIPS_ISA(0); \
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CYG_MACRO_END
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#endif
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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//#define HAL_DCACHE_WRITETHRU_MODE 0
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//#define HAL_DCACHE_WRITEBACK_MODE 1
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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// This uses the fetch-and-lock cache operation.
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#ifndef HAL_DCACHE_LOCK_DEFINED
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#define HAL_DCACHE_LOCK(_base_, _asize_) \
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CYG_MACRO_START \
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register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
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register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
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register CYG_WORD _state_; \
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HAL_DCACHE_IS_ENABLED( _state_ ); \
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if( _state_ ) { \
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_HAL_ASM_SET_MIPS_ISA(3); \
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for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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{ _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_D, _addr_); } \
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_HAL_ASM_SET_MIPS_ISA(0); \
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} \
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CYG_MACRO_END
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#endif
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// Undo a previous lock operation.
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// Do this by flushing the cache, which is defined to clear the lock bit.
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#ifndef HAL_DCACHE_UNLOCK_DEFINED
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#define HAL_DCACHE_UNLOCK(_base_, _size_) \
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HAL_DCACHE_FLUSH( _base_, _size_ )
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#endif
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// Unlock entire cache
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#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
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#define HAL_DCACHE_UNLOCK_ALL() \
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HAL_DCACHE_INVALIDATE_ALL()
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#endif
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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// This uses the hit-writeback-invalidate cache operation.
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#ifndef HAL_DCACHE_FLUSH_DEFINED
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#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
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CYG_MACRO_START \
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register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
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register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
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register CYG_WORD _state_; \
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HAL_DCACHE_IS_ENABLED( _state_ ); \
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if( _state_ ) { \
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_HAL_ASM_SET_MIPS_ISA(3); \
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for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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{ _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D, _addr_); } \
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_HAL_ASM_SET_MIPS_ISA(0); \
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} \
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CYG_MACRO_END
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#endif
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// Invalidate cache lines in the given range without writing to memory.
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// This uses the hit-invalidate cache operation.
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#ifndef HAL_DCACHE_INVALIDATE_DEFINED
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#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
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CYG_MACRO_START \
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register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
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register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
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_HAL_ASM_SET_MIPS_ISA(3); \
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for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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{ _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_D, _addr_); } \
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_HAL_ASM_SET_MIPS_ISA(0); \
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CYG_MACRO_END
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#endif
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// Write dirty cache lines to memory for the given address range.
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// This uses the hit-writeback cache operation.
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#ifndef HAL_DCACHE_STORE_DEFINED
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#define HAL_DCACHE_STORE( _base_ , _asize_ ) \
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CYG_MACRO_START \
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register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
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register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
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register CYG_WORD _state_; \
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HAL_DCACHE_IS_ENABLED( _state_ ); \
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if( _state_ ) { \
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_HAL_ASM_SET_MIPS_ISA(3); \
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for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
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{ _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_D, _addr_); } \
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_HAL_ASM_SET_MIPS_ISA(0); \
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} \
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CYG_MACRO_END
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#endif
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// Preread the given range into the cache with the intention of reading
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// from it later.
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//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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// Preread the given range into the cache with the intention of writing
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// to it later.
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//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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// Allocate and zero the cache lines associated with the given range.
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//#define HAL_DCACHE_ZERO( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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// Enable the instruction cache
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// There is no default mechanism for enabling or disabling the caches.
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#ifndef HAL_ICACHE_ENABLE_DEFINED
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#define HAL_ICACHE_ENABLE()
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#endif
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// Disable the instruction cache
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#ifndef HAL_ICACHE_DISABLE_DEFINED
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#define HAL_ICACHE_DISABLE()
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#endif
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#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
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#define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
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#endif
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// Invalidate the entire cache
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// This uses the index-invalidate cache operation.
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#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
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#define HAL_ICACHE_INVALIDATE_ALL() \
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| 390 |
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CYG_MACRO_START \
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| 391 |
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register CYG_ADDRESS _baddr_ = 0x80000000; \
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| 392 |
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register CYG_ADDRESS _addr_ = 0x80000000; \
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_HAL_ASM_SET_MIPS_ISA(3); \
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| 394 |
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for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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| 395 |
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{ _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_INVALIDATE_I, _addr_); } \
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_HAL_ASM_SET_MIPS_ISA(0); \
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| 397 |
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CYG_MACRO_END
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| 398 |
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#endif
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| 399 |
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| 400 |
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// Synchronize the contents of the cache with memory.
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| 401 |
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// Simply force the cache to reload.
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| 402 |
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#ifndef HAL_ICACHE_SYNC_DEFINED
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| 403 |
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#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
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| 404 |
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#endif
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| 405 |
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| 406 |
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// Set the instruction cache refill burst size
|
| 407 |
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//#define HAL_ICACHE_BURST_SIZE(_size_)
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| 408 |
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|
| 409 |
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// Load the contents of the given address range into the instruction cache
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| 410 |
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// and then lock the cache so that it stays there.
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| 411 |
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// This uses the fetch-and-lock cache operation.
|
| 412 |
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#ifndef HAL_ICACHE_LOCK_DEFINED
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| 413 |
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#define HAL_ICACHE_LOCK(_base_, _asize_) \
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| 414 |
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CYG_MACRO_START \
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| 415 |
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register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
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| 416 |
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register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
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| 417 |
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register CYG_WORD _state_; \
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| 418 |
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HAL_ICACHE_IS_ENABLED( _state_ ); \
|
| 419 |
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if( _state_ ) { \
|
| 420 |
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_HAL_ASM_SET_MIPS_ISA(3); \
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| 421 |
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for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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| 422 |
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{ _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_I, _addr_); } \
|
| 423 |
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_HAL_ASM_SET_MIPS_ISA(0); \
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| 424 |
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} \
|
| 425 |
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CYG_MACRO_END
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| 426 |
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#endif
|
| 427 |
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|
|
| 428 |
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// Undo a previous lock operation.
|
| 429 |
|
|
// Do this by invalidating the cache, which is defined to clear the lock bit.
|
| 430 |
|
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#ifndef HAL_ICACHE_UNLOCK_DEFINED
|
| 431 |
|
|
#define HAL_ICACHE_UNLOCK(_base_, _size_) \
|
| 432 |
|
|
HAL_ICACHE_INVALIDATE( _base_, _size_ )
|
| 433 |
|
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#endif
|
| 434 |
|
|
|
| 435 |
|
|
// Unlock entire cache
|
| 436 |
|
|
//#define HAL_ICACHE_UNLOCK_ALL()
|
| 437 |
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|
| 438 |
|
|
//-----------------------------------------------------------------------------
|
| 439 |
|
|
// Instruction cache line control
|
| 440 |
|
|
|
| 441 |
|
|
// Invalidate cache lines in the given range without writing to memory.
|
| 442 |
|
|
// This uses the hit-invalidate cache operation.
|
| 443 |
|
|
#ifndef HAL_ICACHE_INVALIDATE_DEFINED
|
| 444 |
|
|
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
|
| 445 |
|
|
CYG_MACRO_START \
|
| 446 |
|
|
register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
|
| 447 |
|
|
register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
|
| 448 |
|
|
_HAL_ASM_SET_MIPS_ISA(3); \
|
| 449 |
|
|
for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
|
| 450 |
|
|
{ _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_I, _addr_); } \
|
| 451 |
|
|
_HAL_ASM_SET_MIPS_ISA(0); \
|
| 452 |
|
|
CYG_MACRO_END
|
| 453 |
|
|
#endif
|
| 454 |
|
|
|
| 455 |
|
|
//-----------------------------------------------------------------------------
|
| 456 |
|
|
// Check that a supported configuration has actually defined some macros.
|
| 457 |
|
|
|
| 458 |
|
|
#ifndef HAL_DCACHE_ENABLE
|
| 459 |
|
|
|
| 460 |
|
|
#error Unsupported MIPS configuration
|
| 461 |
|
|
|
| 462 |
|
|
#endif
|
| 463 |
|
|
|
| 464 |
|
|
//-----------------------------------------------------------------------------
|
| 465 |
|
|
#endif // ifndef CYGONCE_HAL_CACHE_H
|
| 466 |
|
|
// End of hal_cache.h
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