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skrzyp |
#ifndef CYGONCE_HAL_HAL_INTR_H
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#define CYGONCE_HAL_HAL_INTR_H
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//==========================================================================
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//
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// hal_intr.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jskov,
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// gthomas, jlarmour
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// Date: 1999-02-16
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock.
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//
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// Usage:
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// #include <cyg/hal/hal_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/var_intr.h>
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//--------------------------------------------------------------------------
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// MIPS vectors.
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// These are the exception codes presented in the Cause register and
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// correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET
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// External interrupt
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#define CYGNUM_HAL_VECTOR_INTERRUPT 0
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// TLB modification exception
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#define CYGNUM_HAL_VECTOR_TLB_MOD 1
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// TLB miss (Load or IFetch)
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#define CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL 2
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// TLB miss (Store)
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#define CYGNUM_HAL_VECTOR_TLB_STORE_REFILL 3
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// Address error (Load or Ifetch)
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#define CYGNUM_HAL_VECTOR_LOAD_ADDRESS 4
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// Address error (store)
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#define CYGNUM_HAL_VECTOR_STORE_ADDRESS 5
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// Bus error (Ifetch)
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#define CYGNUM_HAL_VECTOR_IBE 6
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// Bus error (data load or store)
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#define CYGNUM_HAL_VECTOR_DBE 7
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// System call
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#define CYGNUM_HAL_VECTOR_SYSTEM_CALL 8
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// Break point
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#define CYGNUM_HAL_VECTOR_BREAKPOINT 9
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// Reserved instruction
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#define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 10
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// Coprocessor unusable
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#define CYGNUM_HAL_VECTOR_COPROCESSOR 11
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// Arithmetic overflow
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#define CYGNUM_HAL_VECTOR_OVERFLOW 12
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// Reserved
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#define CYGNUM_HAL_VECTOR_RESERVED_13 13
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// Division-by-zero [reserved vector]
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// This is caused by 'trap 0x7' which GCC puts in the code to check
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// for division by zero. The break_vsr_springboard in vectors.S is the
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// only caller of this vector.
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#define CYGNUM_HAL_VECTOR_DIV_BY_ZERO 14
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// Floating point exception
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#ifdef CYGHWR_HAL_MIPS_FPU
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#define CYGNUM_HAL_VECTOR_FPE 15
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#endif
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#define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_INTERRUPT
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#ifdef CYGNUM_HAL_VECTOR_FPE
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#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_FPE
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#else
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#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_DIV_BY_ZERO
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#endif
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#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX-CYGNUM_HAL_VSR_MIN+1)
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// Exception vectors. These are the values used when passed out to an
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// external exception handler using cyg_hal_deliver_exception()
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#define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_TLB_MOD
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#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \
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CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL
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#define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_WRITE \
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CYGNUM_HAL_VECTOR_TLB_STORE_REFILL
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#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \
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CYGNUM_HAL_VECTOR_LOAD_ADDRESS
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#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_WRITE \
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CYGNUM_HAL_VECTOR_STORE_ADDRESS
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#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_IBE
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#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DBE
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#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
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#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_BREAKPOINT
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#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
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CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION
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#define CYGNUM_HAL_EXCEPTION_COPROCESSOR CYGNUM_HAL_VECTOR_COPROCESSOR
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#define CYGNUM_HAL_EXCEPTION_OVERFLOW CYGNUM_HAL_VECTOR_OVERFLOW
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#define CYGNUM_HAL_EXCEPTION_DIV_BY_ZERO CYGNUM_HAL_VECTOR_DIV_BY_ZERO
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#ifdef CYGHWR_HAL_MIPS_FPU
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#define CYGNUM_HAL_EXCEPTION_FPU CYGNUM_HAL_VECTOR_FPE
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#endif
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#define CYGNUM_HAL_EXCEPTION_INTERRUPT CYGNUM_HAL_VECTOR_BREAKPOINT
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#ifdef CYGHWR_HAL_MIPS_FPU
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// decoded exception vectors
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#define CYGNUM_HAL_EXCEPTION_FPU_INEXACT (-1)
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#define CYGNUM_HAL_EXCEPTION_FPU_DIV_BY_ZERO (-2)
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#define CYGNUM_HAL_EXCEPTION_FPU_OVERFLOW (-3)
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#define CYGNUM_HAL_EXCEPTION_FPU_UNDERFLOW (-4)
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#define CYGNUM_HAL_EXCEPTION_FPU_INVALID (-5)
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#endif
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// Min/Max exception numbers and how many there are
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#ifdef CYGNUM_HAL_EXCEPTION_FPU_INVALID
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_FPU_INVALID
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#else
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN
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#endif
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#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
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#define CYGNUM_HAL_EXCEPTION_COUNT \
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( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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// the default for all MIPS variants is to use the 6 bits
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// in the cause register.
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#define CYGNUM_HAL_INTERRUPT_0 0
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#define CYGNUM_HAL_INTERRUPT_1 1
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#define CYGNUM_HAL_INTERRUPT_2 2
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#define CYGNUM_HAL_INTERRUPT_3 3
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#define CYGNUM_HAL_INTERRUPT_4 4
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#define CYGNUM_HAL_INTERRUPT_5 5
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 5
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#define CYGNUM_HAL_ISR_COUNT 6
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// The vector used by the Real time clock. The default here is to use
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// interrupt 5, which is connected to the counter/comparator registers
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// in many MIPS variants.
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#ifndef CYGNUM_HAL_INTERRUPT_RTC
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_5
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#endif
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Static data used by HAL
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// ISR tables
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externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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// VSR table
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externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1];
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//--------------------------------------------------------------------------
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// Default ISR
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// The #define is used to test whether this routine exists, and to allow
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// us to call it.
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externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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#define HAL_DEFAULT_ISR hal_default_isr
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//--------------------------------------------------------------------------
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// Interrupt state storage
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typedef cyg_uint32 CYG_INTERRUPT_STATE;
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//--------------------------------------------------------------------------
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// Interrupt control macros
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// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
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// that might otherwise cause following code to run in the wrong state or
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// cause a resource conflict.
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#ifndef CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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{ \
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asm volatile ( \
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"mfc0 $8,$12; nop;" \
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"move %0,$8;" \
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"and $8,$8,0XFFFFFFFE;" \
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"mtc0 $8,$12;" \
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"nop; nop; nop;" \
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"and %0,%0,0X1;" \
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: "=r"(_old_) \
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: \
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: "$8" \
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); \
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}
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#define HAL_ENABLE_INTERRUPTS() \
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{ \
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asm volatile ( \
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"mfc0 $8,$12; nop;" \
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"or $8,$8,1;" \
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"mtc0 $8,$12;" \
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"nop; nop; nop;" \
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: \
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: \
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: "$8" \
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); \
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}
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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{ \
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asm volatile ( \
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"mfc0 $8,$12; nop;" \
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"and %0,%0,0x1;" \
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"or $8,$8,%0;" \
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"mtc0 $8,$12;" \
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"nop; nop; nop;" \
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: \
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: "r"(_old_) \
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: "$8" \
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); \
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}
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#define HAL_QUERY_INTERRUPTS( _state_ ) \
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{ \
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asm volatile ( \
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"mfc0 %0,$12; nop;" \
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"and %0,%0,0x1;" \
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: "=r"(_state_) \
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: \
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: "$8" \
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); \
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}
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#endif // CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
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//--------------------------------------------------------------------------
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// Routine to execute DSRs using separate interrupt stack
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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externC void hal_interrupt_stack_call_pending_DSRs(void);
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#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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hal_interrupt_stack_call_pending_DSRs()
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// these are offered solely for stack usage testing
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// if they are not defined, then there is no interrupt stack.
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#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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// use them to declare these extern however you want:
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// extern char HAL_INTERRUPT_STACK_BASE[];
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// extern char HAL_INTERRUPT_STACK_TOP[];
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// is recommended
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#endif
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//--------------------------------------------------------------------------
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// Vector translation.
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// For chained interrupts we only have a single vector though which all
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// are passed. For unchained interrupts we have a vector per interrupt.
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#ifndef HAL_TRANSLATE_VECTOR
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#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
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#else
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
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#endif
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#endif
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//--------------------------------------------------------------------------
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// Interrupt and VSR attachment macros
|
| 324 |
|
|
|
| 325 |
|
|
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
|
| 326 |
|
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CYG_MACRO_START \
|
| 327 |
|
|
cyg_uint32 _index_; \
|
| 328 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 329 |
|
|
\
|
| 330 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
|
| 331 |
|
|
(_state_) = 0; \
|
| 332 |
|
|
else \
|
| 333 |
|
|
(_state_) = 1; \
|
| 334 |
|
|
CYG_MACRO_END
|
| 335 |
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|
| 336 |
|
|
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
|
| 337 |
|
|
{ \
|
| 338 |
|
|
cyg_uint32 _index_; \
|
| 339 |
|
|
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
|
| 340 |
|
|
\
|
| 341 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
|
| 342 |
|
|
{ \
|
| 343 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
|
| 344 |
|
|
hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
|
| 345 |
|
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hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
|
| 346 |
|
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} \
|
| 347 |
|
|
}
|
| 348 |
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|
| 349 |
|
|
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
|
| 350 |
|
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{ \
|
| 351 |
|
|
cyg_uint32 _index_; \
|
| 352 |
|
|
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
|
| 353 |
|
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\
|
| 354 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
|
| 355 |
|
|
{ \
|
| 356 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
|
| 357 |
|
|
hal_interrupt_data[_index_] = 0; \
|
| 358 |
|
|
hal_interrupt_objects[_index_] = 0; \
|
| 359 |
|
|
} \
|
| 360 |
|
|
}
|
| 361 |
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|
| 362 |
|
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
|
| 363 |
|
|
*(_pvsr_) = (void (*)())hal_vsr_table[_vector_];
|
| 364 |
|
|
|
| 365 |
|
|
|
| 366 |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \
|
| 367 |
|
|
if( (void*)_poldvsr_ != NULL) \
|
| 368 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \
|
| 369 |
|
|
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
|
| 370 |
|
|
CYG_MACRO_END
|
| 371 |
|
|
|
| 372 |
|
|
// This is an ugly name, but what it means is: grab the VSR back to eCos
|
| 373 |
|
|
// internal handling, or if you like, the default handler. But if
|
| 374 |
|
|
// cooperating with GDB and CygMon, the default behaviour is to pass most
|
| 375 |
|
|
// exceptions to CygMon. This macro undoes that so that eCos handles the
|
| 376 |
|
|
// exception. So use it with care.
|
| 377 |
|
|
|
| 378 |
|
|
externC void __default_exception_vsr(void);
|
| 379 |
|
|
externC void __default_interrupt_vsr(void);
|
| 380 |
|
|
externC void __break_vsr_springboard(void);
|
| 381 |
|
|
|
| 382 |
|
|
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \
|
| 383 |
|
|
HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \
|
| 384 |
|
|
? (CYG_ADDRESS)__default_interrupt_vsr \
|
| 385 |
|
|
: _vector_ == CYGNUM_HAL_VECTOR_BREAKPOINT \
|
| 386 |
|
|
? (CYG_ADDRESS)__break_vsr_springboard \
|
| 387 |
|
|
: (CYG_ADDRESS)__default_exception_vsr, \
|
| 388 |
|
|
_poldvsr_ ); \
|
| 389 |
|
|
CYG_MACRO_END
|
| 390 |
|
|
|
| 391 |
|
|
//--------------------------------------------------------------------------
|
| 392 |
|
|
// Interrupt controller access
|
| 393 |
|
|
// The default code here simply uses the fields present in the CP0 status
|
| 394 |
|
|
// and cause registers to implement this functionality.
|
| 395 |
|
|
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
|
| 396 |
|
|
// that might otherwise cause following code to run in the wrong state or
|
| 397 |
|
|
// cause a resource conflict.
|
| 398 |
|
|
|
| 399 |
|
|
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 400 |
|
|
|
| 401 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ ) \
|
| 402 |
|
|
CYG_MACRO_START \
|
| 403 |
|
|
asm volatile ( \
|
| 404 |
|
|
"mfc0 $3,$12\n" \
|
| 405 |
|
|
"la $2,0x00000400\n" \
|
| 406 |
|
|
"sllv $2,$2,%0\n" \
|
| 407 |
|
|
"nor $2,$2,$0\n" \
|
| 408 |
|
|
"and $3,$3,$2\n" \
|
| 409 |
|
|
"mtc0 $3,$12\n" \
|
| 410 |
|
|
"nop; nop; nop\n" \
|
| 411 |
|
|
: \
|
| 412 |
|
|
: "r"(_vector_) \
|
| 413 |
|
|
: "$2", "$3" \
|
| 414 |
|
|
); \
|
| 415 |
|
|
CYG_MACRO_END
|
| 416 |
|
|
|
| 417 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
|
| 418 |
|
|
CYG_MACRO_START \
|
| 419 |
|
|
asm volatile ( \
|
| 420 |
|
|
"mfc0 $3,$12\n" \
|
| 421 |
|
|
"la $2,0x00000400\n" \
|
| 422 |
|
|
"sllv $2,$2,%0\n" \
|
| 423 |
|
|
"or $3,$3,$2\n" \
|
| 424 |
|
|
"mtc0 $3,$12\n" \
|
| 425 |
|
|
"nop; nop; nop\n" \
|
| 426 |
|
|
: \
|
| 427 |
|
|
: "r"(_vector_) \
|
| 428 |
|
|
: "$2", "$3" \
|
| 429 |
|
|
); \
|
| 430 |
|
|
CYG_MACRO_END
|
| 431 |
|
|
|
| 432 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 433 |
|
|
CYG_MACRO_START \
|
| 434 |
|
|
asm volatile ( \
|
| 435 |
|
|
"mfc0 $3,$13\n" \
|
| 436 |
|
|
"la $2,0x00000400\n" \
|
| 437 |
|
|
"sllv $2,$2,%0\n" \
|
| 438 |
|
|
"nor $2,$2,$0\n" \
|
| 439 |
|
|
"and $3,$3,$2\n" \
|
| 440 |
|
|
"mtc0 $3,$13\n" \
|
| 441 |
|
|
"nop; nop; nop\n" \
|
| 442 |
|
|
: \
|
| 443 |
|
|
: "r"(_vector_) \
|
| 444 |
|
|
: "$2", "$3" \
|
| 445 |
|
|
); \
|
| 446 |
|
|
CYG_MACRO_END
|
| 447 |
|
|
|
| 448 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
|
| 449 |
|
|
|
| 450 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
|
| 451 |
|
|
|
| 452 |
|
|
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 453 |
|
|
|
| 454 |
|
|
#endif
|
| 455 |
|
|
|
| 456 |
|
|
//--------------------------------------------------------------------------
|
| 457 |
|
|
// Clock control.
|
| 458 |
|
|
// This code uses the count and compare registers that are present in many
|
| 459 |
|
|
// MIPS variants.
|
| 460 |
|
|
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
|
| 461 |
|
|
// that might otherwise cause following code to run in the wrong state or
|
| 462 |
|
|
// cause a resource conflict.
|
| 463 |
|
|
|
| 464 |
|
|
#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED
|
| 465 |
|
|
|
| 466 |
|
|
externC CYG_WORD32 cyg_hal_clock_period;
|
| 467 |
|
|
#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED
|
| 468 |
|
|
|
| 469 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
| 470 |
|
|
CYG_MACRO_START \
|
| 471 |
|
|
asm volatile ( \
|
| 472 |
|
|
"mtc0 $0,$9\n" \
|
| 473 |
|
|
"nop; nop; nop\n" \
|
| 474 |
|
|
"mtc0 %0,$11\n" \
|
| 475 |
|
|
"nop; nop; nop\n" \
|
| 476 |
|
|
: \
|
| 477 |
|
|
: "r"(_period_) \
|
| 478 |
|
|
); \
|
| 479 |
|
|
cyg_hal_clock_period = _period_; \
|
| 480 |
|
|
CYG_MACRO_END
|
| 481 |
|
|
|
| 482 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
|
| 483 |
|
|
CYG_MACRO_START \
|
| 484 |
|
|
asm volatile ( \
|
| 485 |
|
|
"mtc0 $0,$9\n" \
|
| 486 |
|
|
"nop; nop; nop\n" \
|
| 487 |
|
|
"mtc0 %0,$11\n" \
|
| 488 |
|
|
"nop; nop; nop\n" \
|
| 489 |
|
|
: \
|
| 490 |
|
|
: "r"(_period_) \
|
| 491 |
|
|
); \
|
| 492 |
|
|
CYG_MACRO_END
|
| 493 |
|
|
|
| 494 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
| 495 |
|
|
CYG_MACRO_START \
|
| 496 |
|
|
register CYG_WORD32 result; \
|
| 497 |
|
|
asm volatile ( \
|
| 498 |
|
|
"mfc0 %0,$9\n" \
|
| 499 |
|
|
: "=r"(result) \
|
| 500 |
|
|
); \
|
| 501 |
|
|
*(_pvalue_) = result; \
|
| 502 |
|
|
CYG_MACRO_END
|
| 503 |
|
|
|
| 504 |
|
|
#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED
|
| 505 |
|
|
|
| 506 |
|
|
#endif
|
| 507 |
|
|
|
| 508 |
|
|
#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
|
| 509 |
|
|
!defined(HAL_CLOCK_LATENCY)
|
| 510 |
|
|
#define HAL_CLOCK_LATENCY( _pvalue_ ) \
|
| 511 |
|
|
CYG_MACRO_START \
|
| 512 |
|
|
register CYG_WORD32 _cval_; \
|
| 513 |
|
|
HAL_CLOCK_READ(&_cval_); \
|
| 514 |
|
|
*(_pvalue_) = _cval_ - cyg_hal_clock_period; \
|
| 515 |
|
|
CYG_MACRO_END
|
| 516 |
|
|
#endif
|
| 517 |
|
|
|
| 518 |
|
|
|
| 519 |
|
|
//--------------------------------------------------------------------------
|
| 520 |
|
|
// Microsecond delay function provided in hal_misc.c
|
| 521 |
|
|
externC void hal_delay_us(int us);
|
| 522 |
|
|
|
| 523 |
|
|
#define HAL_DELAY_US(n) hal_delay_us(n)
|
| 524 |
|
|
|
| 525 |
|
|
//--------------------------------------------------------------------------
|
| 526 |
|
|
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
|
| 527 |
|
|
// End of hal_intr.h
|
