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skrzyp |
#ifndef CYGONCE_HAL_MIPS_REGS_H
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#define CYGONCE_HAL_MIPS_REGS_H
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//========================================================================
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//
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// mips-regs.h
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//
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// Register defines for MIPS processors
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//
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//========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Red Hat, nickg
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// Contributors: Red Hat, nickg, dmoseley
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// Date: 1998-06-08
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// Purpose:
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// Description: Register defines for MIPS processors
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// Usage:
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================
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#include <pkgconf/hal.h>
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#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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/* This value must agree with NUMREGS in mips-stub.h. */
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#if defined(CYGPKG_HAL_MIPS_GDB_REPORT_CP0)
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#define NUM_REGS 107
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#else
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#define NUM_REGS 90
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#endif
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#ifdef __mips64
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#define REG_SIZE 8
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#else
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#define REG_SIZE 4
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#endif
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/* General register names for assembly code. */
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#define zero $0
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#define at $1 /* assembler temporary */
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#define atmp $1 /* assembler temporary */
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#define v0 $2 /* value holders */
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#define v1 $3
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#define a0 $4 /* arguments */
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#define a1 $5
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#define a2 $6
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#define a3 $7
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#define t0 $8 /* temporaries */
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define s0 $16 /* saved registers */
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#define s1 $17
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#define s2 $18
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#define s3 $19
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#define s4 $20
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#define s5 $21
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#define s6 $22
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#define s7 $23
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#define t8 $24 /* temporaries */
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#define t9 $25
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#define k0 $26 /* kernel registers */
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#define k1 $27
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#define gp $28 /* global pointer */
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#define sp $29 /* stack pointer */
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#define s8 $30 /* saved register */
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#define fp $30 /* frame pointer (obsolete usage) */
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#define ra $31 /* return address */
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/* MIPS registers, numbered in the order in which gdb expects to see them. */
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#define ZERO 0
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#define AT 1
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#define ATMP 1
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#define V0 2
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#define V1 3
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#define A0 4
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#define A1 5
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#define A2 6
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#define A3 7
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#define T4 12
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#define T5 13
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#define T6 14
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#define T7 15
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#define S0 16
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#define S1 17
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#define S2 18
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#define S3 19
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#define S4 20
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#define S5 21
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#define S6 22
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#define S7 23
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#define T8 24
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#define T9 25
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#define K0 26
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#define K1 27
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#define GP 28
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#define SP 29
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#define S8 30
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#define RA 31
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#define SR 32
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#define LO 33
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#define HI 34
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#define BAD_VA 35
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#define CAUSE 36
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#define PC 37
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#define F0 38
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#define F1 39
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#define F2 40
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#define F3 41
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#define F4 42
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#define F5 43
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#define F6 44
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#define F7 45
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#define F8 46
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#define F9 47
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#define F10 48
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#define F11 49
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#define F12 50
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#define F13 51
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#define F14 52
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#define F15 53
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#define F16 54
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#define F17 55
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#define F18 56
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#define F19 57
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#define F20 58
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#define F21 59
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#define F22 60
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#define F23 61
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#define F24 62
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#define F25 63
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#define F26 64
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#define F27 65
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#define F28 66
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#define F29 67
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#define F30 68
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#define F31 69
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#define FCR31 70
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/* System Control Coprocessor (CP0) exception processing registers */
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#define C0_CONTEXT $4 /* Context */
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#define C0_BADVADDR $8 /* Bad Virtual Address */
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#define C0_COUNT $9 /* Count */
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#define C0_COMPARE $11 /* Compare */
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#define C0_STATUS $12 /* Processor Status */
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#define C0_CAUSE $13 /* Exception Cause */
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#define C0_EPC $14 /* Exception PC */
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#define C0_WATCHLO $18 /* Watchpoint LO */
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#define C0_WATCHHI $19 /* Watchpoint HI */
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#define C0_XCONTEXT $20 /* XContext */
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#define C0_ECC $26 /* ECC */
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#define C0_CACHEERR $27 /* CacheErr */
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#define C0_ERROREPC $30 /* ErrorEPC */
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/* Status register fields */
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#define SR_CUMASK 0xf0000000 /* Coprocessor usable bits */
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#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
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#define SR_CU2 0x40000000 /* coprocessor 2 usable */
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#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
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#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
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#define SR_FR 0x04000000 /* Enable 32 floating-point registers */
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#define SR_RE 0x02000000 /* Reverse Endian in user mode */
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#define SR_BEV 0x00400000 /* Bootstrap Exception Vector */
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#define SR_TS 0x00200000 /* TLB shutdown (reserved on R4600) */
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#define SR_SR 0x00100000 /* Soft Reset */
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#define SR_CH 0x00040000 /* Cache Hit */
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#define SR_CE 0x00020000 /* ECC register modifies check bits */
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#define SR_DE 0x00010000 /* Disable cache errors */
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#define SR_IMASK 0x0000ff00 /* Interrupt Mask */
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#define SR_IMASK8 0x00000000 /* Interrupt Mask level=8 */
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#define SR_IMASK7 0x00008000 /* Interrupt Mask level=7 */
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#define SR_IMASK6 0x0000c000 /* Interrupt Mask level=6 */
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#define SR_IMASK5 0x0000e000 /* Interrupt Mask level=5 */
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#define SR_IMASK4 0x0000f000 /* Interrupt Mask level=4 */
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#define SR_IMASK3 0x0000f800 /* Interrupt Mask level=3 */
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#define SR_IMASK2 0x0000fc00 /* Interrupt Mask level=2 */
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#define SR_IMASK1 0x0000fe00 /* Interrupt Mask level=1 */
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#define SR_IMASK0 0x0000ff00 /* Interrupt Mask level=0 */
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#define SR_IBIT8 0x00008000 /* (Intr5) */
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#define SR_IBIT7 0x00004000 /* (Intr4) */
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#define SR_IBIT6 0x00002000 /* (Intr3) */
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#define SR_IBIT5 0x00001000 /* (Intr2) */
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#define SR_IBIT4 0x00000800 /* (Intr1) */
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#define SR_IBIT3 0x00000400 /* (Intr0) */
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#define SR_IBIT2 0x00000200 /* (Software Interrupt 1) */
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#define SR_IBIT1 0x00000100 /* (Software Interrupt 0) */
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#define SR_KX 0x00000080 /* xtlb in kernel mode */
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#define SR_SX 0x00000040 /* mips3 & xtlb in supervisor mode */
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#define SR_UX 0x00000020 /* mips3 & xtlb in user mode */
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#define SR_KSU_MASK 0x00000018 /* ksu mode mask */
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#define SR_KSU_USER 0x00000010 /* user mode */
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#define SR_KSU_SUPV 0x00000008 /* supervisor mode */
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#define SR_KSU_KERN 0x00000000 /* kernel mode */
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#define SR_ERL 0x00000004 /* error level */
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#define SR_EXL 0x00000002 /* exception level */
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#define SR_IE 0x00000001 /* interrupt enable */
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/* Floating-point unit control/status register (FCR31) */
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#define FCR31_FS 0x01000000 /* Flush denormalized to zero */
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#define FCR31_C 0x00800000 /* FP compare result */
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#define FCR31_CAUSE_E 0x00020000 /* Cause - unimplemented operation */
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#define FCR31_CAUSE_V 0x00010000 /* Cause - invalid operation */
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#define FCR31_CAUSE_Z 0x00008000 /* Cause - division by zero */
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#define FCR31_CAUSE_O 0x00004000 /* Cause - overflow */
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#define FCR31_CAUSE_U 0x00002000 /* Cause - underflow */
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#define FCR31_CAUSE_I 0x00001000 /* Cause - inexact operation */
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#define FCR31_ENABLES_V 0x00000800 /* Enables - invalid operation */
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#define FCR31_ENABLES_Z 0x00000400 /* Enables - division by zero */
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#define FCR31_ENABLES_O 0x00000200 /* Enables - overflow */
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#define FCR31_ENABLES_U 0x00000100 /* Enables - underflow */
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#define FCR31_ENABLES_I 0x00000080 /* Enables - inexact operation */
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#define FCR31_FLAGS_V 0x00000040 /* Flags - invalid operation */
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#define FCR31_FLAGS_Z 0x00000020 /* Flags - division by zero */
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#define FCR31_FLAGS_O 0x00000010 /* Flags - overflow */
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#define FCR31_FLAGS_U 0x00000008 /* Flags - underflow */
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#define FCR31_FLAGS_I 0x00000004 /* Flags - inexact operation */
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#define FCR31_RMMASK 0x00000002 /* Rounding mode mask */
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#define FCR31_RM_RN 0 /* Round to nearest */
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#define FCR31_RM_RZ 1 /* Round to zero */
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#define FCR31_RM_RP 2 /* Round to +infinity */
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#define FCR31_RM_RM 3 /* Round to -infinity */
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/* Cause register fields */
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#define CAUSE_BD 0x80000000 /* Branch Delay */
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#define CAUSE_CEMASK 0x30000000 /* Coprocessor Error */
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#define CAUSE_CESHIFT 28 /* Right justify CE */
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#define CAUSE_IPMASK 0x0000ff00 /* Interrupt Pending */
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#define CAUSE_IPSHIFT 8 /* Right justify IP */
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#define CAUSE_IP8 0x00008000 /* (Intr5) */
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#define CAUSE_IP7 0x00004000 /* (Intr4) */
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#define CAUSE_IP6 0x00002000 /* (Intr3) */
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#define CAUSE_IP5 0x00001000 /* (Intr2) */
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#define CAUSE_IP4 0x00000800 /* (Intr1) */
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#define CAUSE_IP3 0x00000400 /* (Intr0) */
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#define CAUSE_SW2 0x00000200 /* (Software Interrupt 1) */
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#define CAUSE_SW1 0x00000100 /* (Software Interrupt 0) */
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#define CAUSE_EXCMASK 0x0000007c /* Exception Code */
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#define CAUSE_EXCSHIFT 2 /* Right justify EXC */
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/* Exception Codes */
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#define EXC_INT 0 /* External interrupt */
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#define EXC_MOD 1 /* TLB modification exception */
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#define EXC_TLBL 2 /* TLB miss (Load or Ifetch) */
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#define EXC_TLBS 3 /* TLB miss (Store) */
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#define EXC_ADEL 4 /* Address error (Load or Ifetch) */
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#define EXC_ADES 5 /* Address error (Store) */
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#define EXC_IBE 6 /* Bus error (Ifetch) */
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#define EXC_DBE 7 /* Bus error (data load or store) */
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#define EXC_SYS 8 /* System call */
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#define EXC_BP 9 /* Break point */
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#define EXC_RI 10 /* Reserved instruction */
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#define EXC_CPU 11 /* Coprocessor unusable */
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#define EXC_OVF 12 /* Arithmetic overflow */
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#define EXC_TRAP 13 /* Trap exception */
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#define EXC_FPE 15 /* Floating Point Exception */
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#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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#endif // ifndef CYGONCE_HAL_MIPS_REGS_H
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