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skrzyp |
##=============================================================================
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##
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## vectors.S
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##
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## MIPS exception vectors
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): nickg
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## Contributors: nickg, dmoseley
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## Date: 1998-02-04
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## Purpose: MIPS exception vectors
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## Description: This file defines the code placed into the exception
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## vectors. It also contains the first level default VSRs
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## that save and restore state for both exceptions and
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## interrupts.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#ifdef CYGPKG_KERNEL
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# include
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#endif
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#include
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#include
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#ifdef at
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#undef at
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#endif
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.extern cyg_instrument
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##-----------------------------------------------------------------------------
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## Hardware supplied vectors
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.set noreorder
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.section ".reset_vector","ax"
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# Reset vector at 0xBFC00000
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FUNC_START(reset_vector)
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#ifndef CYG_HAL_STARTUP_RAM
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# if defined(CYGPKG_HAL_RESET_VECTOR_FIRST_CODE)
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hal_reset_vector_first_code
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# endif
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# if defined(CYGPKG_HAL_EARLY_INIT)
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hal_early_init
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# endif
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# Decide whether this is an NMI, cold or warm boot.
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mfc0 k0,status # get status reg
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lui k1,0x0008 # isolate NMI bit
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and k1,k1,k0
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beqz k1,1f # skip if zero
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nop
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lar k1,__nmi_entry # jump to ROM nmi code
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jalr k1
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nop
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1:
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lui k1,0x0010 # isolate soft reset bit
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and k1,k1,k0
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beqz k1,2f # skip if zero
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nop
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lar k1,__warm_start # jump to ROM warm_start code
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jr k1
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nop
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2:
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la k0,INITIAL_CONFIG0 # Set up config0 register
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mtc0 k0,config0 # to disable cache
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#endif
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lar v0,_start # jump to start
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#ifdef CYGARC_START_FUNC_UNCACHED
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CYGARC_ADDRESS_REG_UNCACHED(v0)
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#endif
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jr v0
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nop # (delay slot)
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FUNC_END(reset_vector)
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.section ".debug_vector","ax"
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# Debug vector at 0xBFC00200
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FUNC_START(debug_vector)
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la k0,32*4
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la k1,hal_vsr_table # Get VSR table
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lw k1,32*4(k1) # load debug vector
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jr k1 # go there
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nop # (delay slot)
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FUNC_END(debug_vector)
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.section ".other_vector","ax"
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# Common vector at 0x80000080 or 0xBFC00180
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FUNC_START(other_vector)
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mfc0 k0,cause # K0 = exception cause
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nop
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andi k0,k0,0x7F # isolate exception code
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la k1,hal_vsr_table # address of VSR table
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add k1,k1,k0 # offset of VSR entry
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lw k1,0(k1) # k1 = pointer to VSR
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jr k1 # go there
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nop # (delay slot)
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FUNC_END(other_vector)
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.section ".utlb_vector","ax"
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FUNC_START(utlb_vector)
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mfc0 k0,cause # K0 = exception cause
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nop
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andi k0,k0,0x7F # isolate exception code
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la k1,hal_vsr_table # address of VSR table
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add k1,k1,k0 # offset of VSR entry
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lw k1,0(k1) # k1 = pointer to VSR
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jr k1 # go there
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nop # (delay slot)
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FUNC_END(utlb_vector)
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##-----------------------------------------------------------------------------
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## Startup code
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.text
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FUNC_START(_start)
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# Initialize hardware
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hal_cpu_init
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hal_diag_init
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hal_mmu_init
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hal_fpu_init
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hal_memc_init
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hal_intc_init
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hal_cache_init
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hal_timer_init
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#ifdef CYGARC_START_FUNC_UNCACHED
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# switch to cached execution address if necessary
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# assumption is that hal_cache_init makes this safe
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lar v0,1f
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jr v0
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nop
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1:
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#endif
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# Load Global Pointer register.
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la gp,_gp
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# load initial stack pointer
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la a0,__interrupt_stack
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move sp,a0
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hal_mon_init
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#ifdef CYG_HAL_STARTUP_ROM
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# Copy data from ROM to RAM
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.extern hal_copy_data
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jal hal_copy_data
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nop
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#endif
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# Zero BSS
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.extern hal_zero_bss
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jal hal_zero_bss
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nop
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# Call variant and platform HAL
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# initialization routines.
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.extern hal_variant_init
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jal hal_variant_init
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nop
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.extern hal_platform_init
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jal hal_platform_init
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nop
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# Call constructors
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.extern cyg_hal_invoke_constructors
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jal cyg_hal_invoke_constructors
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nop
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#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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.extern initialize_stub
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jal initialize_stub
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nop
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#endif
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#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
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.extern hal_ctrlc_isr_init
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jal hal_ctrlc_isr_init
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nop
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#endif
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# Call cyg_start
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.extern cyg_start
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j cyg_start
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lui ra,0
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FUNC_END(_start )
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##-----------------------------------------------------------------------------
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FUNC_START(__warm_start)
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## The following is debug code left in here for now in case it
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## proves useful in the near future.
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#if 0
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move s0,t0
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move s1,a1
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# hal_diag_init
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hal_diag_writec '$'
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mvafc0 a0,$30 # get ErrorEPC
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lar k0,hal_diag_ai_write_hex8
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jalr k0
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nop
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hal_diag_writec '-'
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move a0,s0
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jalr k0
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nop
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hal_diag_writec '-'
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move a0,s1
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jalr k0
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nop
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1:
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b 1b
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nop
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#endif
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| 278 |
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# Treat a warm-start either as a cold-start or an NMI
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#if defined(CYGHWR_HAL_MIPS_WARMSTART_COLDSTART)
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lar v0,_start # jump to start
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jr v0
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| 282 |
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nop # (delay slot)
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#else
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# Defaults to NMI
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b __nmi_entry
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nop
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#endif
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| 289 |
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FUNC_END(__warm_start)
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| 291 |
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##-----------------------------------------------------------------------------
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| 293 |
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FUNC_START(__nmi_entry)
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# Clear exception state
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| 296 |
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hal_cpu_except_enable
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| 297 |
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| 298 |
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# Move the ErrorEPC register to the EPC register so that the
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| 299 |
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# default exception handler saves the right PC value.
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| 300 |
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mvafc0 k0,$30
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| 301 |
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nop; nop; nop;
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| 302 |
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mvatc0 k0,epc
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| 303 |
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nop; nop; nop;
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| 304 |
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| 305 |
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#if (INITIAL_SR & 0x00400000) == 0
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| 306 |
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# Taking this exception will have set the BEV bit to 1.
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| 307 |
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# If we normally run with it zero, we must clear it here.
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| 308 |
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mfc0 k0,status
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| 309 |
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la k1,0xFFBFFFFF
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| 310 |
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and k0,k0,k1
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| 311 |
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mtc0 k0,status
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| 312 |
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#endif
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| 313 |
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| 314 |
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la k0,34*4
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| 315 |
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la k1,hal_vsr_table # Get VSR table
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| 316 |
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lw k1,34*4(k1) # load NMI vector
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| 317 |
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jr k1 # go there
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| 318 |
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nop # (delay slot)
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| 319 |
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| 320 |
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FUNC_END(__nmi_entry)
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| 321 |
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| 322 |
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##-----------------------------------------------------------------------------
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| 323 |
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## Default exception VSR.
|
| 324 |
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## Saves machine state and calls external handling code.
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| 325 |
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|
| 326 |
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FUNC_START(__default_exception_vsr)
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| 327 |
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|
| 328 |
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# We enter here with all of the CPU state still
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| 329 |
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# in its registers except:
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| 330 |
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# K0 = vector index
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| 331 |
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# K1 = address of this function
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| 332 |
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| 333 |
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move k1,sp # K1 = original SP
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| 334 |
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| 335 |
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addi sp,sp,-mips_exception_decrement
|
| 336 |
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# space for registers + safety margin
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| 337 |
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|
| 338 |
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sw k0,mipsreg_vector(sp) # store vector
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| 339 |
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|
| 340 |
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# store GPRs
|
| 341 |
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.set noat
|
| 342 |
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sgpr 0,sp
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| 343 |
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sgpr 1,sp
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| 344 |
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sgpr 2,sp
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| 345 |
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sgpr 3,sp
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| 346 |
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sgpr 4,sp
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| 347 |
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sgpr 5,sp
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| 348 |
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sgpr 6,sp
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| 349 |
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sgpr 7,sp
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| 350 |
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sgpr 8,sp
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| 351 |
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sgpr 9,sp
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| 352 |
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sgpr 10,sp
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| 353 |
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sgpr 11,sp
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| 354 |
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sgpr 12,sp
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| 355 |
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sgpr 13,sp
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| 356 |
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sgpr 14,sp
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| 357 |
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sgpr 15,sp
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| 358 |
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sgpr 16,sp
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| 359 |
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sgpr 17,sp
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| 360 |
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sgpr 18,sp
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| 361 |
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sgpr 19,sp
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| 362 |
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sgpr 20,sp
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| 363 |
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sgpr 21,sp
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| 364 |
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sgpr 22,sp
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| 365 |
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sgpr 23,sp
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| 366 |
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sgpr 24,sp
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| 367 |
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sgpr 25,sp
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| 368 |
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# sgpr 26,sp # == K0
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| 369 |
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# sgpr 27,sp # == K1
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| 370 |
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sgpr 28,sp # == GP
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| 371 |
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# sgpr 29,sp # == SP
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| 372 |
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sgpr 30,sp # == FP
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| 373 |
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sgpr 31,sp # == RA
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| 374 |
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.set at
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| 375 |
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| 376 |
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mfhi a0
|
| 377 |
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mflo a1
|
| 378 |
|
|
shi a0,sp
|
| 379 |
|
|
slo a1,sp
|
| 380 |
|
|
|
| 381 |
|
|
# K1 contains original SP
|
| 382 |
|
|
ssp k1,sp # store in reg dump
|
| 383 |
|
|
|
| 384 |
|
|
# save remaining machine state registers
|
| 385 |
|
|
mfc0 t0,cause
|
| 386 |
|
|
mfc0 t1,status
|
| 387 |
|
|
mfc0 t2,cachectrl
|
| 388 |
|
|
mvafc0 t3,badvr
|
| 389 |
|
|
mfc0 t4,config
|
| 390 |
|
|
mfc0 t5,prid
|
| 391 |
|
|
mvafc0 t6,epc
|
| 392 |
|
|
|
| 393 |
|
|
sw t0,mipsreg_cause(sp)
|
| 394 |
|
|
sw t1,mipsreg_sr(sp)
|
| 395 |
|
|
sw t2,mipsreg_cachectrl(sp)
|
| 396 |
|
|
sva t3,mipsreg_badvr(sp)
|
| 397 |
|
|
sw t4,mipsreg_config(sp)
|
| 398 |
|
|
sw t5,mipsreg_prid(sp)
|
| 399 |
|
|
sva t6,mipsreg_pc(sp)
|
| 400 |
|
|
|
| 401 |
|
|
hal_fpu_save sp
|
| 402 |
|
|
|
| 403 |
|
|
# The machine state is now all saved on the stack.
|
| 404 |
|
|
|
| 405 |
|
|
hal_diag_excpt_start
|
| 406 |
|
|
|
| 407 |
|
|
# Load Global Pointer register.
|
| 408 |
|
|
la gp,_gp
|
| 409 |
|
|
|
| 410 |
|
|
move s0,sp # save pointer to saved state
|
| 411 |
|
|
|
| 412 |
|
|
#if defined(CYGSEM_HAL_ROM_MONITOR) && \
|
| 413 |
|
|
defined(CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK)
|
| 414 |
|
|
|
| 415 |
|
|
la a0,__interrupt_stack # a0 = stack top
|
| 416 |
|
|
la a1,__interrupt_stack_base # a1 = stack base
|
| 417 |
|
|
sub a3,sp,a1 # a3 = sp - base
|
| 418 |
|
|
bltz a3,1f # not on istack if < 0
|
| 419 |
|
|
nop # delay slot
|
| 420 |
|
|
sub t0,a0,sp # t0 = top - sp
|
| 421 |
|
|
bgtz t0,8f # already on istack if > 0
|
| 422 |
|
|
nop # delay slot
|
| 423 |
|
|
1:
|
| 424 |
|
|
move sp,a0 # switch to istack
|
| 425 |
|
|
8:
|
| 426 |
|
|
addi sp,sp,-8 # space for old SP
|
| 427 |
|
|
# (8 to keep dword alignment!)
|
| 428 |
|
|
sw s0,0(sp) # save old SP on stack
|
| 429 |
|
|
|
| 430 |
|
|
#endif
|
| 431 |
|
|
addi sp,sp,-mips_stack_frame_size # make a null frame
|
| 432 |
|
|
|
| 433 |
|
|
# Need to set up back pointers etc. ???
|
| 434 |
|
|
|
| 435 |
|
|
hal_cpu_except_enable # reenable exceptions
|
| 436 |
|
|
|
| 437 |
|
|
.extern cyg_hal_exception_handler
|
| 438 |
|
|
jal cyg_hal_exception_handler # call C code
|
| 439 |
|
|
move a0,s0 # arg0 = register dump (delay slot)
|
| 440 |
|
|
|
| 441 |
|
|
#if defined(CYGSEM_HAL_ROM_MONITOR) && \
|
| 442 |
|
|
defined(CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK)
|
| 443 |
|
|
|
| 444 |
|
|
# If we are returning from the last nested exception, move back
|
| 445 |
|
|
# to the thread stack.
|
| 446 |
|
|
# Since we have arranged for the top of stack location to
|
| 447 |
|
|
# contain the sp we need to go back to here, just pop it off
|
| 448 |
|
|
# and put it in SP.
|
| 449 |
|
|
|
| 450 |
|
|
lw sp,mips_stack_frame_size(sp) # sp = *sp
|
| 451 |
|
|
subu sp,sp,mips_stack_frame_size # make a null frame
|
| 452 |
|
|
#endif
|
| 453 |
|
|
|
| 454 |
|
|
j restore_state
|
| 455 |
|
|
nop
|
| 456 |
|
|
|
| 457 |
|
|
FUNC_END(__default_exception_vsr)
|
| 458 |
|
|
|
| 459 |
|
|
##------------------------------------------------------------------------------
|
| 460 |
|
|
## Default interrupt VSR.
|
| 461 |
|
|
## Saves machine state and calls appropriate ISR. When done, calls
|
| 462 |
|
|
## interrupt_end() to finish up and possibly reschedule.
|
| 463 |
|
|
|
| 464 |
|
|
FUNC_START(__default_interrupt_vsr)
|
| 465 |
|
|
|
| 466 |
|
|
|
| 467 |
|
|
# We enter here with all of the CPU state still
|
| 468 |
|
|
# in its registers except:
|
| 469 |
|
|
# K0 = vector index
|
| 470 |
|
|
# K1 = address of this function
|
| 471 |
|
|
|
| 472 |
|
|
move k1,sp # K1 = original SP
|
| 473 |
|
|
|
| 474 |
|
|
addi sp,sp,-mips_exception_decrement
|
| 475 |
|
|
# space for registers + safety margin
|
| 476 |
|
|
|
| 477 |
|
|
sw k0,mipsreg_vector(sp) # store vector
|
| 478 |
|
|
|
| 479 |
|
|
# store GPRs
|
| 480 |
|
|
.set noat
|
| 481 |
|
|
sgpr 0,sp
|
| 482 |
|
|
sgpr 1,sp
|
| 483 |
|
|
sgpr 2,sp
|
| 484 |
|
|
sgpr 3,sp
|
| 485 |
|
|
sgpr 4,sp
|
| 486 |
|
|
sgpr 5,sp
|
| 487 |
|
|
sgpr 6,sp
|
| 488 |
|
|
sgpr 7,sp
|
| 489 |
|
|
sgpr 8,sp
|
| 490 |
|
|
sgpr 9,sp
|
| 491 |
|
|
sgpr 10,sp
|
| 492 |
|
|
sgpr 11,sp
|
| 493 |
|
|
sgpr 12,sp
|
| 494 |
|
|
sgpr 13,sp
|
| 495 |
|
|
sgpr 14,sp
|
| 496 |
|
|
sgpr 15,sp
|
| 497 |
|
|
sgpr 16,sp
|
| 498 |
|
|
sgpr 17,sp
|
| 499 |
|
|
sgpr 18,sp
|
| 500 |
|
|
sgpr 19,sp
|
| 501 |
|
|
sgpr 20,sp
|
| 502 |
|
|
sgpr 21,sp
|
| 503 |
|
|
sgpr 22,sp
|
| 504 |
|
|
sgpr 23,sp
|
| 505 |
|
|
sgpr 24,sp
|
| 506 |
|
|
sgpr 25,sp
|
| 507 |
|
|
# sgpr 26,sp # == K0
|
| 508 |
|
|
# sgpr 27,sp # == K1
|
| 509 |
|
|
sgpr 28,sp # == GP
|
| 510 |
|
|
# sgpr 29,sp # == SP
|
| 511 |
|
|
sgpr 30,sp # == FP
|
| 512 |
|
|
sgpr 31,sp # == RA
|
| 513 |
|
|
.set at
|
| 514 |
|
|
|
| 515 |
|
|
mfhi a0
|
| 516 |
|
|
mflo a1
|
| 517 |
|
|
shi a0,sp
|
| 518 |
|
|
slo a1,sp
|
| 519 |
|
|
|
| 520 |
|
|
# K1 contains original SP
|
| 521 |
|
|
ssp k1,sp # store in reg dump
|
| 522 |
|
|
|
| 523 |
|
|
mfc0 t1,status
|
| 524 |
|
|
mfc0 t2,cachectrl
|
| 525 |
|
|
mvafc0 t3,epc
|
| 526 |
|
|
|
| 527 |
|
|
sw t1,mipsreg_sr(sp)
|
| 528 |
|
|
sw t2,mipsreg_cachectrl(sp)
|
| 529 |
|
|
sva t3,mipsreg_pc(sp)
|
| 530 |
|
|
|
| 531 |
|
|
hal_fpu_save sp
|
| 532 |
|
|
|
| 533 |
|
|
# The machine state is now all saved on the stack.
|
| 534 |
|
|
|
| 535 |
|
|
# Load Global Pointer register.
|
| 536 |
|
|
la gp,_gp
|
| 537 |
|
|
|
| 538 |
|
|
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
|
| 539 |
|
|
.extern cyg_scheduler_sched_lock
|
| 540 |
|
|
la v0,cyg_scheduler_sched_lock
|
| 541 |
|
|
lw a0,0(v0)
|
| 542 |
|
|
addi a0,a0,1
|
| 543 |
|
|
sw a0,0(v0)
|
| 544 |
|
|
#endif
|
| 545 |
|
|
|
| 546 |
|
|
move s0,sp # save pointer to saved state
|
| 547 |
|
|
|
| 548 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 549 |
|
|
|
| 550 |
|
|
la a0,__interrupt_stack # a0 = stack top
|
| 551 |
|
|
la a1,__interrupt_stack_base # a1 = stack base
|
| 552 |
|
|
sub a3,sp,a1 # a3 = sp - base
|
| 553 |
|
|
bltz a3,1f # not on istack if < 0
|
| 554 |
|
|
nop # delay slot
|
| 555 |
|
|
sub t0,a0,sp # t0 = top - sp
|
| 556 |
|
|
bgtz t0,8f # already on istack if > 0
|
| 557 |
|
|
nop # delay slot
|
| 558 |
|
|
1:
|
| 559 |
|
|
move sp,a0 # switch to istack
|
| 560 |
|
|
8:
|
| 561 |
|
|
addi sp,sp,-8 # space for old SP
|
| 562 |
|
|
# (8 to keep dword alignment!)
|
| 563 |
|
|
sw s0,0(sp) # save old SP on stack
|
| 564 |
|
|
|
| 565 |
|
|
#endif
|
| 566 |
|
|
|
| 567 |
|
|
subu sp,sp,mips_stack_frame_size # make a null frame
|
| 568 |
|
|
|
| 569 |
|
|
# Need to set up back pointers etc. ???
|
| 570 |
|
|
|
| 571 |
|
|
# Decode external interrupt via interrupt controller
|
| 572 |
|
|
|
| 573 |
|
|
hal_intc_decode s2
|
| 574 |
|
|
|
| 575 |
|
|
# Here, s2 contains the number of the interrupt being serviced,
|
| 576 |
|
|
# we need to derive from that the vector number to call in the ISR
|
| 577 |
|
|
# table.
|
| 578 |
|
|
|
| 579 |
|
|
hal_intc_translate s2,s1
|
| 580 |
|
|
|
| 581 |
|
|
# Here s1 is the number of the vector to be called and s2 is
|
| 582 |
|
|
# the number of the interrupt being serviced.
|
| 583 |
|
|
|
| 584 |
|
|
hal_diag_intr_start
|
| 585 |
|
|
|
| 586 |
|
|
#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
|
| 587 |
|
|
|
| 588 |
|
|
# Call cyg_instrument to record that this interrupt is being raised.
|
| 589 |
|
|
|
| 590 |
|
|
li a0,0x0301 # a0 = type = INTR,RAISE
|
| 591 |
|
|
move a1,s1 # a1 = vector number
|
| 592 |
|
|
jal cyg_instrument # call instrument function
|
| 593 |
|
|
move a2,s2 # a2 = interrupt number
|
| 594 |
|
|
#endif
|
| 595 |
|
|
|
| 596 |
|
|
#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
|
| 597 |
|
|
# If we are supporting Ctrl-C interrupts from GDB, we must squirrel
|
| 598 |
|
|
# away a pointer to the save interrupt state here so that we can
|
| 599 |
|
|
# plant a breakpoint at some later time.
|
| 600 |
|
|
|
| 601 |
|
|
.extern hal_saved_interrupt_state
|
| 602 |
|
|
la v0,hal_saved_interrupt_state
|
| 603 |
|
|
sw s0,0(v0)
|
| 604 |
|
|
|
| 605 |
|
|
#endif
|
| 606 |
|
|
|
| 607 |
|
|
sll s1,s1,2 # s1 = byte offset of vector
|
| 608 |
|
|
|
| 609 |
|
|
hal_cpu_except_enable # reenable exceptions
|
| 610 |
|
|
|
| 611 |
|
|
la t2,hal_interrupt_handlers # handler table
|
| 612 |
|
|
add t2,t2,s1 # address of ISR ptr
|
| 613 |
|
|
lw t2,0(t2) # ISR pointer
|
| 614 |
|
|
|
| 615 |
|
|
la a1,hal_interrupt_data # data table
|
| 616 |
|
|
add a1,a1,s1 # address of data ptr
|
| 617 |
|
|
lw a1,0(a1) # Data pointer
|
| 618 |
|
|
|
| 619 |
|
|
move a0,s2 # pass interrupt number
|
| 620 |
|
|
move a2,s0 # pass saved interrupt state
|
| 621 |
|
|
|
| 622 |
|
|
jalr t2 # call ISR via t2
|
| 623 |
|
|
nop # (delay slot)
|
| 624 |
|
|
|
| 625 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 626 |
|
|
|
| 627 |
|
|
# If we are returning from the last nested interrupt, move back
|
| 628 |
|
|
# to the thread stack. interrupt_end() must be called on the
|
| 629 |
|
|
# thread stack since it potentially causes a context switch.
|
| 630 |
|
|
# Since we have arranged for the top of stack location to
|
| 631 |
|
|
# contain the sp we need to go back to here, just pop it off
|
| 632 |
|
|
# and put it in SP.
|
| 633 |
|
|
|
| 634 |
|
|
|
| 635 |
|
|
lw sp,mips_stack_frame_size(sp) # sp = *sp
|
| 636 |
|
|
subu sp,sp,mips_stack_frame_size # make a null frame
|
| 637 |
|
|
#endif
|
| 638 |
|
|
|
| 639 |
|
|
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
|
| 640 |
|
|
|
| 641 |
|
|
# We only need to call _interrupt_end() when there is a kernel
|
| 642 |
|
|
# present to do any tidying up.
|
| 643 |
|
|
|
| 644 |
|
|
# On return v0 bit 1 will indicate whether a DSR is
|
| 645 |
|
|
# to be posted. Pass this together with a pointer to
|
| 646 |
|
|
# the interrupt object we have just used to the
|
| 647 |
|
|
# interrupt tidy up routine.
|
| 648 |
|
|
|
| 649 |
|
|
# Note that s0, s1 and s2 are defined to be preserved across
|
| 650 |
|
|
# calls by the calling convention, so they still contain
|
| 651 |
|
|
# the register dump, the vector offset and the interrupt number
|
| 652 |
|
|
# respectively.
|
| 653 |
|
|
|
| 654 |
|
|
move s2,v0
|
| 655 |
|
|
|
| 656 |
|
|
la a1,hal_interrupt_objects # interrupt object table
|
| 657 |
|
|
add a1,a1,s1 # address of object ptr
|
| 658 |
|
|
lw a1,0(a1) # a1 = object ptr
|
| 659 |
|
|
|
| 660 |
|
|
move a2,s0 # arg3 = saved register dump
|
| 661 |
|
|
|
| 662 |
|
|
.extern interrupt_end
|
| 663 |
|
|
jal interrupt_end # call into C to finish off
|
| 664 |
|
|
move a0,v0 # put ISR result in arg0
|
| 665 |
|
|
|
| 666 |
|
|
move v0,s2 # return value from isr
|
| 667 |
|
|
#endif
|
| 668 |
|
|
|
| 669 |
|
|
restore_state:
|
| 670 |
|
|
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon)
|
| 671 |
|
|
move k0,v0
|
| 672 |
|
|
#endif
|
| 673 |
|
|
|
| 674 |
|
|
# All done, restore CPU state and continue
|
| 675 |
|
|
|
| 676 |
|
|
addi sp,sp,mips_stack_frame_size # retrieve CPU state ptr
|
| 677 |
|
|
|
| 678 |
|
|
# Disable interrupts again while we restore state.
|
| 679 |
|
|
hal_cpu_int_disable
|
| 680 |
|
|
|
| 681 |
|
|
hal_diag_restore
|
| 682 |
|
|
|
| 683 |
|
|
hal_fpu_load sp
|
| 684 |
|
|
|
| 685 |
|
|
lw t0,mipsreg_cachectrl(sp)
|
| 686 |
|
|
lhi t1,sp
|
| 687 |
|
|
llo t2,sp
|
| 688 |
|
|
|
| 689 |
|
|
mtc0 t0,cachectrl
|
| 690 |
|
|
mthi t1
|
| 691 |
|
|
mtlo t2
|
| 692 |
|
|
|
| 693 |
|
|
# load GPRs
|
| 694 |
|
|
.set noat
|
| 695 |
|
|
# lgpr 0,sp
|
| 696 |
|
|
lgpr 1,sp
|
| 697 |
|
|
lgpr 2,sp
|
| 698 |
|
|
lgpr 3,sp
|
| 699 |
|
|
lgpr 4,sp
|
| 700 |
|
|
lgpr 5,sp
|
| 701 |
|
|
lgpr 6,sp
|
| 702 |
|
|
lgpr 7,sp
|
| 703 |
|
|
lgpr 8,sp
|
| 704 |
|
|
lgpr 9,sp
|
| 705 |
|
|
lgpr 10,sp
|
| 706 |
|
|
lgpr 11,sp
|
| 707 |
|
|
lgpr 12,sp
|
| 708 |
|
|
lgpr 13,sp
|
| 709 |
|
|
lgpr 14,sp
|
| 710 |
|
|
lgpr 15,sp
|
| 711 |
|
|
lgpr 16,sp
|
| 712 |
|
|
lgpr 17,sp
|
| 713 |
|
|
lgpr 18,sp
|
| 714 |
|
|
lgpr 19,sp
|
| 715 |
|
|
lgpr 20,sp
|
| 716 |
|
|
lgpr 21,sp
|
| 717 |
|
|
lgpr 22,sp
|
| 718 |
|
|
lgpr 23,sp
|
| 719 |
|
|
lgpr 24,sp
|
| 720 |
|
|
lgpr 25,sp
|
| 721 |
|
|
# lgpr 26,sp # == K0
|
| 722 |
|
|
# lgpr 27,sp # == K1
|
| 723 |
|
|
lgpr 28,sp # == GP
|
| 724 |
|
|
# lgpr 29,sp # == SP
|
| 725 |
|
|
lgpr 30,sp # == FP
|
| 726 |
|
|
lgpr 31,sp # == RA
|
| 727 |
|
|
.set at
|
| 728 |
|
|
|
| 729 |
|
|
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon)
|
| 730 |
|
|
|
| 731 |
|
|
# If we have a Cygmon that wants to listen to network interrupts, then
|
| 732 |
|
|
# the return code from the earlier call to hal_default_isr() will
|
| 733 |
|
|
# have been negative to indicate this. So we jump into Cygmon here
|
| 734 |
|
|
# because Cygmon requires the processor state to be the same as when
|
| 735 |
|
|
# the interrupt was taken, but with k0 as the exception number.
|
| 736 |
|
|
|
| 737 |
|
|
bgez k0,1f
|
| 738 |
|
|
nop
|
| 739 |
|
|
# Check for new cygmon
|
| 740 |
|
|
sw k0,(mipsreg_regs+26*4)(sp) # save k0
|
| 741 |
|
|
la k1,0x80000100 + 41*4 # New cygmon "magic" id
|
| 742 |
|
|
lw k1,0(k1)
|
| 743 |
|
|
lui k0,0x55aa
|
| 744 |
|
|
ori k0,0x4321
|
| 745 |
|
|
bne k0,k1,1f
|
| 746 |
|
|
|
| 747 |
|
|
# Need to let cygmon handle this
|
| 748 |
|
|
la k1,0x80000100 + 39*4 # stub entry vector
|
| 749 |
|
|
lw k0,(mipsreg_regs+26*4)(sp) # restore k0
|
| 750 |
|
|
lw k1,0(k1)
|
| 751 |
|
|
lw sp,(mipsreg_regs+29*4)(sp) # restore SP
|
| 752 |
|
|
sll k0,1 # clear bit 31.
|
| 753 |
|
|
jr k1
|
| 754 |
|
|
srl k0,1
|
| 755 |
|
|
1:
|
| 756 |
|
|
#endif
|
| 757 |
|
|
|
| 758 |
|
|
lw k1,mipsreg_sr(sp) # K1 = saved SR
|
| 759 |
|
|
|
| 760 |
|
|
#if 0 < CYGINT_HAL_MIPS_INTERRUPT_RETURN_KEEP_SR_IM
|
| 761 |
|
|
# Keep the current settings of the IM[7:0] bits within the status
|
| 762 |
|
|
# register. These may be used as interrupt masks, so if an ISR or
|
| 763 |
|
|
# DSR masks interrupts they must be preserved.
|
| 764 |
|
|
# If they are not used, then this does no harm.
|
| 765 |
|
|
ori k0,zero,0xff00
|
| 766 |
|
|
nor k0,k0,k0 # 0xffff00ff
|
| 767 |
|
|
and k1,k1,k0 # all interrupts disabled
|
| 768 |
|
|
|
| 769 |
|
|
mfc0 k0,status # V0 = current SR
|
| 770 |
|
|
nop
|
| 771 |
|
|
nop
|
| 772 |
|
|
andi k0,k0,0xff00 # preserve interrupt set
|
| 773 |
|
|
or k1,k1,k0 # insert into "saved SR"
|
| 774 |
|
|
#endif // 0 < CYGINT_HAL_MIPS_INTERRUPT_RETURN_KEEP_SR_IM
|
| 775 |
|
|
lva k0,mipsreg_pc(sp) # K0 = return PC
|
| 776 |
|
|
lsp sp,sp # load SP
|
| 777 |
|
|
|
| 778 |
|
|
# Invoke CPU specific mechanism for returning from this
|
| 779 |
|
|
# exception
|
| 780 |
|
|
|
| 781 |
|
|
hal_cpu_eret k0,k1
|
| 782 |
|
|
|
| 783 |
|
|
FUNC_END(__default_interrupt_vsr)
|
| 784 |
|
|
|
| 785 |
|
|
hal_intc_decode_data
|
| 786 |
|
|
|
| 787 |
|
|
##-----------------------------------------------------------------------------
|
| 788 |
|
|
## Execute pending DSRs on the interrupt stack with interrupts enabled.
|
| 789 |
|
|
## Note: this can only be called from code running on a thread stack
|
| 790 |
|
|
|
| 791 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 792 |
|
|
.extern cyg_interrupt_call_pending_DSRs
|
| 793 |
|
|
|
| 794 |
|
|
FUNC_START(hal_interrupt_stack_call_pending_DSRs)
|
| 795 |
|
|
mfc0 t0,status # get status register value
|
| 796 |
|
|
la v0,__interrupt_stack # v0 = interrupt stack
|
| 797 |
|
|
move v1,sp # v1 = original stack ptr
|
| 798 |
|
|
move sp,v0 # sp = interrupt stack
|
| 799 |
|
|
addi sp,sp,-32 # make a null frame
|
| 800 |
|
|
sw v1,16(sp) # save old sp
|
| 801 |
|
|
sw ra,20(sp) # save old ra
|
| 802 |
|
|
sw t0,24(sp) # save old sr
|
| 803 |
|
|
|
| 804 |
|
|
hal_cpu_int_enable
|
| 805 |
|
|
|
| 806 |
|
|
jal cyg_interrupt_call_pending_DSRs # call back to kernel
|
| 807 |
|
|
nop
|
| 808 |
|
|
|
| 809 |
|
|
lw a0,24(sp) # get status reg
|
| 810 |
|
|
|
| 811 |
|
|
hal_cpu_int_merge a0 # merge with current SR
|
| 812 |
|
|
|
| 813 |
|
|
lw ra,20(sp) # restore ra
|
| 814 |
|
|
lw sp,16(sp) # restore sp
|
| 815 |
|
|
|
| 816 |
|
|
jr ra # go back
|
| 817 |
|
|
nop # delay slot
|
| 818 |
|
|
|
| 819 |
|
|
FUNC_END(hal_interrupt_stack_call_pending_DSRs)
|
| 820 |
|
|
#endif
|
| 821 |
|
|
|
| 822 |
|
|
##-----------------------------------------------------------------------------
|
| 823 |
|
|
## Short circuit in case any code tries to use "__gccmain()"
|
| 824 |
|
|
|
| 825 |
|
|
FUNC_START(__gccmain)
|
| 826 |
|
|
jr ra
|
| 827 |
|
|
nop
|
| 828 |
|
|
FUNC_END(__gccmain)
|
| 829 |
|
|
|
| 830 |
|
|
##-----------------------------------------------------------------------------
|
| 831 |
|
|
## Switch to a new stack.
|
| 832 |
|
|
## This is used in RedBoot to allow code to execute in a different
|
| 833 |
|
|
## stack context.
|
| 834 |
|
|
|
| 835 |
|
|
FUNC_START(hal_program_new_stack)
|
| 836 |
|
|
# Arguments are:
|
| 837 |
|
|
# a0 = function to call
|
| 838 |
|
|
# a1 = stack pointer to use
|
| 839 |
|
|
|
| 840 |
|
|
move v1,sp # v1 = original stack ptr
|
| 841 |
|
|
move sp,a1 # sp = new stack
|
| 842 |
|
|
addi sp,sp,-32 # make a null frame
|
| 843 |
|
|
sva v1,8(sp) # save old sp
|
| 844 |
|
|
sva ra,16(sp) # save old ra
|
| 845 |
|
|
|
| 846 |
|
|
jalr a0 # call function
|
| 847 |
|
|
nop
|
| 848 |
|
|
|
| 849 |
|
|
lva ra,16(sp) # restore ra
|
| 850 |
|
|
lva sp,8(sp) # restore sp
|
| 851 |
|
|
|
| 852 |
|
|
jr ra # go back
|
| 853 |
|
|
nop # delay slot
|
| 854 |
|
|
|
| 855 |
|
|
FUNC_END(hal_program_new_stack)
|
| 856 |
|
|
|
| 857 |
|
|
##-----------------------------------------------------------------------------
|
| 858 |
|
|
## hal_zero_bss
|
| 859 |
|
|
## Zero bss. Done in assembler to be optimal rather than using memset,
|
| 860 |
|
|
## which would risk zeroing bss while using it.
|
| 861 |
|
|
|
| 862 |
|
|
FUNC_START(hal_zero_bss)
|
| 863 |
|
|
#ifdef CYGHWR_HAL_MIPS_64BIT
|
| 864 |
|
|
#define STORE_OP sd
|
| 865 |
|
|
#define BLOCK_SHIFT 6
|
| 866 |
|
|
#else
|
| 867 |
|
|
#define STORE_OP sw
|
| 868 |
|
|
#define BLOCK_SHIFT 5
|
| 869 |
|
|
#endif
|
| 870 |
|
|
la a0,__bss_start # start of bss
|
| 871 |
|
|
la a1,__bss_end # end of bss
|
| 872 |
|
|
andi a2,a0,mips_regsize-1 # is bss aligned?
|
| 873 |
|
|
bne a2,zero,1f # skip word copy
|
| 874 |
|
|
nop
|
| 875 |
|
|
|
| 876 |
|
|
# loop with 8 stores per loop
|
| 877 |
|
|
subu a3,a1,a0 # get length
|
| 878 |
|
|
srl a3,a3,BLOCK_SHIFT # get number of blocks
|
| 879 |
|
|
sll a3,a3,BLOCK_SHIFT # get length of blocks
|
| 880 |
|
|
addu a3,a0,a3 # get end addr of blocks
|
| 881 |
|
|
2: STORE_OP zero,(mips_regsize*0)(a0)
|
| 882 |
|
|
STORE_OP zero,(mips_regsize*1)(a0)
|
| 883 |
|
|
STORE_OP zero,(mips_regsize*2)(a0)
|
| 884 |
|
|
STORE_OP zero,(mips_regsize*3)(a0)
|
| 885 |
|
|
STORE_OP zero,(mips_regsize*4)(a0)
|
| 886 |
|
|
STORE_OP zero,(mips_regsize*5)(a0)
|
| 887 |
|
|
STORE_OP zero,(mips_regsize*6)(a0)
|
| 888 |
|
|
STORE_OP zero,(mips_regsize*7)(a0)
|
| 889 |
|
|
addu a0,a0,mips_regsize*8 # next addr
|
| 890 |
|
|
bne a3,a0,2b # to next store
|
| 891 |
|
|
nop
|
| 892 |
|
|
|
| 893 |
|
|
# If length is a multiple of block size then we
|
| 894 |
|
|
# are done and need to skip the byte loop
|
| 895 |
|
|
beq a1,a0,3f
|
| 896 |
|
|
nop
|
| 897 |
|
|
|
| 898 |
|
|
# finish 1 byte at a time
|
| 899 |
|
|
1: sb zero,0(a0) # zero memory
|
| 900 |
|
|
addiu a0,a0,1 # next addr
|
| 901 |
|
|
bne a0,a1,1b # to next store
|
| 902 |
|
|
nop
|
| 903 |
|
|
3: jr ra
|
| 904 |
|
|
nop
|
| 905 |
|
|
FUNC_END(hal_zero_bss)
|
| 906 |
|
|
|
| 907 |
|
|
|
| 908 |
|
|
##-----------------------------------------------------------------------------
|
| 909 |
|
|
## VSR springboard for break instruction exceptions
|
| 910 |
|
|
## Both GCC and GDB use break instructions. GCC for division-by-zero
|
| 911 |
|
|
## notification and GDB for program-flow breakpoints. This springboard
|
| 912 |
|
|
## looks for the d-b-z kind and directs them to another vector so libc
|
| 913 |
|
|
## can handle these without affecting the debugger.
|
| 914 |
|
|
|
| 915 |
|
|
FUNC_START(__break_vsr_springboard)
|
| 916 |
|
|
mvafc0 k0,epc
|
| 917 |
|
|
mfc0 k1,cause
|
| 918 |
|
|
bltzl k1,1f
|
| 919 |
|
|
addi k0,k0,4 # delay slot (only executed if BD set)
|
| 920 |
|
|
1: lw k1,0(k0) # get break instruction
|
| 921 |
|
|
la k0,0x0007000d # break 0x7 used by GCC for d-b-z
|
| 922 |
|
|
bne k0,k1,2f
|
| 923 |
|
|
nop
|
| 924 |
|
|
ori k0,$0,14*4 # CYGNUM_HAL_VECTOR_DIV_BY_ZERO
|
| 925 |
|
|
la k1,hal_vsr_table # address of VSR table
|
| 926 |
|
|
add k1,k1,k0 # offset of VSR entry
|
| 927 |
|
|
lw k1,0(k1) # k1 = pointer to VSR
|
| 928 |
|
|
jr k1 # go there
|
| 929 |
|
|
nop # (delay slot)
|
| 930 |
|
|
2: ori k0,$0,9*4 # CYGNUM_HAL_VECTOR_BREAKPOINT
|
| 931 |
|
|
j __default_exception_vsr
|
| 932 |
|
|
nop # (delay slot)
|
| 933 |
|
|
FUNC_END(__break_vsr_springboard)
|
| 934 |
|
|
|
| 935 |
|
|
|
| 936 |
|
|
##-----------------------------------------------------------------------------
|
| 937 |
|
|
## Interrupt Stack.
|
| 938 |
|
|
## Used during intialization and for executing ISRs.
|
| 939 |
|
|
|
| 940 |
|
|
.bss
|
| 941 |
|
|
|
| 942 |
|
|
.balign 16
|
| 943 |
|
|
.global cyg_interrupt_stack_base
|
| 944 |
|
|
cyg_interrupt_stack_base:
|
| 945 |
|
|
__interrupt_stack_base:
|
| 946 |
|
|
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
|
| 947 |
|
|
.byte 0
|
| 948 |
|
|
.endr
|
| 949 |
|
|
.balign 16
|
| 950 |
|
|
.global cyg_interrupt_stack
|
| 951 |
|
|
cyg_interrupt_stack:
|
| 952 |
|
|
__interrupt_stack:
|
| 953 |
|
|
|
| 954 |
|
|
.long 0,0,0,0,0,0,0,0
|
| 955 |
|
|
|
| 956 |
|
|
##-----------------------------------------------------------------------------
|
| 957 |
|
|
## VSR table.
|
| 958 |
|
|
## The main interrupt code indirects through here to find the VSR
|
| 959 |
|
|
## to execute for each architecture defined interrupt.
|
| 960 |
|
|
## This is only used for simulated targets, on real targets a fixed location VSR
|
| 961 |
|
|
## table is now allocated at 0x80000100.
|
| 962 |
|
|
|
| 963 |
|
|
#ifndef CYG_HAL_MIPS_VSR_TABLE_DEFINED
|
| 964 |
|
|
|
| 965 |
|
|
## .section ".vsr_table","a"
|
| 966 |
|
|
|
| 967 |
|
|
.data
|
| 968 |
|
|
|
| 969 |
|
|
.globl hal_vsr_table
|
| 970 |
|
|
|
| 971 |
|
|
hal_vsr_table:
|
| 972 |
|
|
.long __default_interrupt_vsr
|
| 973 |
|
|
.rept 63
|
| 974 |
|
|
.long __default_exception_vsr
|
| 975 |
|
|
.endr
|
| 976 |
|
|
|
| 977 |
|
|
#endif
|
| 978 |
|
|
|
| 979 |
|
|
#------------------------------------------------------------------------------
|
| 980 |
|
|
# Interrupt vector tables.
|
| 981 |
|
|
# These tables contain the isr, data and object pointers used to deliver
|
| 982 |
|
|
# interrupts to user code.
|
| 983 |
|
|
# hal_interrupt_level contains the interrupt level set by
|
| 984 |
|
|
# HAL_INTERRUPT_CONFIGURE().
|
| 985 |
|
|
# This is a default set that provide support only for the 6 external
|
| 986 |
|
|
# interrupts in the status/cause registers. Platforms or boards are expected
|
| 987 |
|
|
# to define their own versions of these if they have their own interrupt mappings.
|
| 988 |
|
|
|
| 989 |
|
|
#ifndef CYG_HAL_MIPS_ISR_TABLES_DEFINED
|
| 990 |
|
|
|
| 991 |
|
|
.extern hal_default_isr
|
| 992 |
|
|
|
| 993 |
|
|
.data
|
| 994 |
|
|
|
| 995 |
|
|
.globl hal_interrupt_handlers
|
| 996 |
|
|
hal_interrupt_handlers:
|
| 997 |
|
|
.long hal_default_isr
|
| 998 |
|
|
.long hal_default_isr
|
| 999 |
|
|
.long hal_default_isr
|
| 1000 |
|
|
.long hal_default_isr
|
| 1001 |
|
|
.long hal_default_isr
|
| 1002 |
|
|
.long hal_default_isr
|
| 1003 |
|
|
|
| 1004 |
|
|
|
| 1005 |
|
|
.globl hal_interrupt_data
|
| 1006 |
|
|
hal_interrupt_data:
|
| 1007 |
|
|
.rept 6
|
| 1008 |
|
|
.long 0
|
| 1009 |
|
|
.endr
|
| 1010 |
|
|
|
| 1011 |
|
|
.globl hal_interrupt_objects
|
| 1012 |
|
|
hal_interrupt_objects:
|
| 1013 |
|
|
.rept 6
|
| 1014 |
|
|
.long 0
|
| 1015 |
|
|
.endr
|
| 1016 |
|
|
|
| 1017 |
|
|
#endif
|
| 1018 |
|
|
|
| 1019 |
|
|
##-----------------------------------------------------------------------------
|
| 1020 |
|
|
## end of vectors.S
|
| 1021 |
|
|
|
| 1022 |
|
|
|
