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##=============================================================================
##
##      platform.S
##
##      MIPS IDT platform code
##
##=============================================================================
## ####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later
## version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License
## along with eCos; if not, write to the Free Software Foundation, Inc.,
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
##
## As a special exception, if other files instantiate templates or use
## macros or inline functions from this file, or you compile this file
## and link it with other works to produce a work based on this file,
## this file does not by itself cause the resulting work to be covered by
## the GNU General Public License. However the source code for this file
## must still be made available in accordance with section (3) of the GNU
## General Public License v2.
##
## This exception does not invalidate any other reasons why a work based
## on this file might be covered by the GNU General Public License.
## -------------------------------------------
## ####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):    tmichals
## Contributors: nickg
## Date:         2002-10-02
## Purpose:
## Description:  MIPS IDT platform code
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
#include 
 
#ifdef CYGPKG_KERNEL
# include 
#endif
 
#include 
#include 
 
 
FUNC_START(hal_memc_setup)
#define PIO_BASE_ADDR     0xb8000600
#define PIO_DC_SET        0x00500050
#define PIO_DC_MASK       0xff0fff0f
 
                li      t0,PIO_BASE_ADDR
                lw      t1,0x4(t0)
                nop
                li      t2,PIO_DC_MASK          #mask the UART bits
                and     t1,t1,t2
                nop
                li      t2,PIO_DC_SET           #rx0=rx1=input, tx0=tx1=output
                or      t1,t1,t2
                nop
                sw      t1,0x4(t0)
 
 
                li      t0,PORT_WIDTH_CNTL_REG /* Set PortWidth and Bus parameters */
                li      t1,PORT_WIDTH_CNTL_VAL
                sw      t1,0(t0)
 
                li      t0,BUS_TURN_AROUND_CNTRL_REG
                li      t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles.  0x18000000*/
                sw      t1,0(t0)
 
                li      t0,BUS_TURN_AROUND_REG
                li      t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0xffffe204*/
                sw      t1,0(t0)
 
 
                li      t0,ADDRESS_LATCH_TIMING_REG
                li      t1,ADDRESS_LATCH_TIMING_VAL
                sw      t1,0(t0)
 
 
 
/* CHIP SELECT 0 for FLASH */
        li      t0,MEM_BASE_BASE
        li      t1,MBA_REG0
        sw      t1,0(t0)                /* 0x18000080 */
        li      t1,MBM_REG0
        sw      t1,0x4(t0)              /* 0x18000084 */
        li      t0,MEM_CTL_BASE
        li      t1,MCR_CS0_BS
        sw      t1,0(t0)                /* 0x18000200 */
 
/* CHIP SELECT 1 for FLASH */
 
        li      t0,MEM_BASE_BASE
        li      t1,MBA_REG1
        sw      t1,8(t0)                /* 0x18000088 */
        li      t1,MBM_REG1             /* 0x1800008C */
        sw      t1,0xc(t0)
        li      t0,MEM_CTL_BASE
        li      t1,MCR_CS1_BS           /* chip select 2 for other flash */
        sw      t1,0x4(t0)              /* 0x18000204 */
 
/* CHIP SELECT 2*/
                li      t1,MCR_CS2_BS
                sw      t1,0x8(t0)
 
/* CHIP SELECT 3*/
                li      t1,MCR_CS3_BS
                sw      t1,0xc(t0)
 
 
/* CHIP SELECT 4*/
                li      t1,MCR_CS4_BS
                sw      t1,0x10(t0)
 
 
/* CHIP SELECT 5*/
                li      t1,MCR_CS5_BS
                sw      t1,0x14(t0)
 
 
 
                li      t0,RHEA_IREG_BASE
                li      t1,DISABLE_TIMER
                sw      t1,0x730(t0)
 
                li      t1,0
                sw      t1,0x310(t0)
 
 
/* SDRAM Initialization:- Start Here!  */
        li      t1,DRAM_BNK0_BASE
        sw      t1,0xc0(t0)
        li      t1,DRAM_BNK1_BASE
        sw      t1,0xc8(t0)
        li      t1,DRAM_BNK2_BASE
        sw      t1,0xd0(t0)
        li      t1,DRAM_BNK3_BASE
        sw      t1,0xd8(t0)
 
        li      t1,DRAM_BNK0_MASK
        sw      t1,0xc4(t0)
        li      t1,DRAM_BNK1_MASK
        sw      t1,0xcc(t0)
        li      t1,DRAM_BNK2_MASK
        sw      t1,0xd4(t0)
        li      t1,DRAM_BNK3_MASK
        sw      t1,0xdc(t0)
 
        li      t0,MEM_BASE_BASE
        li      t1,MBA_REG1
        sw      t1,0x8(t0)
        li      t1,MBM_REG1
        sw      t1,0xc(t0)
 
        li      t0,TIMER_BASE
        li      t1,DISABLE_TIMER
        sw      t1,0x60(t0)
                nop
        li      t1,0x0
        sw      t1,0x64(t0)
        li      t1,CPU_BERR_BS
        sw      t1,0x48(t0)
        li      t1,IP_BERR_BS
        sw      t1,0x58(t0)
 
 
        li      t0,RHEA_IREG_BASE
        li      t1,SDRAM_CR_BS
        sw      t1,0x300(t0)
 
        li      t2,2
        li      t3,0
1:
        li      t1,SDRAM_PC_VAL
        sw      t1,0x300(t0)
        nop
        li      t4,SDRAM_TEST_PATTERN
        li      t5,K1BASE | DRAM_BNK0_BASE
        sw      t4,0x1000(t5)
        addu    t3,1
        bne     t3,t2,1b
                nop
 
        li      t2,2
        li      t3,0
1:
        li      t1,SDRAM_RFRSH_CMD
        sw      t1,0x300(t0)
        sw      t4,0x0(t5)
        addu    t3,1
        bne     t3,t2,1b
                nop
 
 
        li      t1,SDRAM_MODE_REG
        sw      t1,0x300(t0)
        sw      t4,0x80(t5)
 
        li      t0,TIMER_BASE
        li      t1,DRAM_RF_CMPR_BS
        sw      t1,0x68(t0)
        li      t1,ENABLE_TIMER
        sw      t1,0x60(t0)
 
 
       /* Delay for Sdram to stabilise with fast refresh */
        li      t2, 0x2FF00
1:
        subu    t2, 1
        bne     t2, zero,1b
        nop
 
       /* Change the Sdram refresh to a standard refresh */
        li      t0,TIMER_BASE
        li      t1,DRAM_RF_CMPR_SE_BS
        sw      t1,0x68(t0)
 
/* SDRAM Initialization : End Here !  */
 
 
                jr      ra
                nop
 
FUNC_END(hal_memc_setup)
 
 
FUNC_START(hal_setTlbEntry)
         .set noreorder
                mtc0 a0,C0_INX
                mtc0 a1,C0_TLBHI
                mtc0 a2,C0_TLBLO0
                mtc0 a3,C0_TLBLO1
                nop
                nop
                tlbwi
                nop
.set reorder
 
                j ra
         nop
FUNC_END(hal_setTlbEntry)
 
FUNC_START(hal_setPageSize)
        .set noreorder
        mtc0  a0,C0_PAGEMASK
        nop
        nop
        .set reorder
        j    ra
        nop
FUNC_END(hal_setPageSize)
 
 
 
 
FUNC_START (hal_sysConfigOutByte)
      .set noreorder
      li   t0,0xb8002cf8
      li   t1,0xb8002cfc
      li   t2,0x3
      and  a2,t2
      sw   a0,0x0(t0)
      xori a2,0x3
      or   t1,a2
      sb   a1,0x0(t1)
      j    ra
      nop
      .set reorder
FUNC_END(hal_sysConfigOutByte)
 
 
 
FUNC_START(hal_sysConfigOutHalfWord)
      .set noreorder
      li   t0,0xb8002cf8
      li   t1,0xb8002cfc
      li   t2,0x3
      and  a2,t2
      sw   a0,0x0(t0)
      xori a2,0x2
      or   t1,a2
      sh   a1,0x0(t1)
      j    ra
      nop
      .set reorder
FUNC_END (hal_sysConfigOutHalfWord)
 
FUNC_START (hal_sysConfigOutWord)
      .set noreorder
      li   t0,0xb8002cf8
      li   t1,0xb8002cfc
      sw   a0,0x0(t0)
      sw   a1,0x0(t1)
      j    ra
      nop
      .set reorder
FUNC_END (hal_sysConfigOutWord)
 
 
/*
 * Function:
 *      unsigned char sysConfigInByte (int pciConfigAddress) ;
 * Inputs:
 *      a0 - pciConfigAddress
 * Outputs:
 *      v0 - byte read from PCI Configuration space.
 */
 FUNC_START (hal_sysConfigInByte)
sysConfigInByte:
        li      t0, 0xb8000000  /* t0 = Upper 16 bits of PCI config */
                                        /*      space address register */
        andi    t1, a0, 0x00000003      /* t1 = PCI config space byte offset. */
        xor     t2, t1, a0              /* t2 = PCI config address of   */
                                        /*      longword containing byte. */
        xori    t1, 0x00000003  /* t1 = big endian byte offset. */
                                        /*      offset 0 -> 3 */
                                        /*      offset 1 -> 2 */
                                        /*      offset 2 -> 1 */
                                        /*      offset 3 -> 0 */
        or      t1, t0                  /* t1 = byte corrected PCI config */
                                        /*      data address. */
        .set    noreorder               /* Instructions must not be moved ! */
        sw      t2, 0x2cf8 (t0)         /* Write PCI config space address reg */
        lw      $0, 0x2cf8 (t0)         /* wbflush() insures write-then-read */
 
        lbu     v0, 0x2cfc (t1)         /* v0 = PCI config space byte read */
 
        j       ra                      /* Return to caller. */
        sw      $0, 0x2cf8 (t0)         /* BDSLOT - Park PCI bus */
 
        .set    reorder
FUNC_END (hal_sysConfigInByte)
 
/*
 * Function:
 *      unsigned short sysConfigInHalfWord (int pciConfigAddress) ;
 *
 * Inputs:
 *      a0 - pciConfigAddress
 *
 * Outputs:
 *      v0 - half word read from PCI Configuration space.
 */
 
FUNC_START (hal_sysConfigInHalfWord)
sysConfigInHalfWord:
        li      t0, 0xb8000000  /* t0 = Upper 16 bits of PCI config */
                                        /*      space address register */
        andi    t1, a0, 0x00000003      /* t1 = Config space halfword offset. */
        xor     t2, t1, a0              /* t2 = PCI config address of   */
                                        /*      longword containing halfword. */
 
        xori    t1, 0x00000002  /* t1 = big endian halfword offset. */
                                        /*      offset 0 -> 2 */
                                        /*      offset 2 -> 0 */
 
        or      t1, t0                  /* t1 = halfword corrected PCI config */
                                        /*      data address. */
        .set    noreorder               /* Instructions must not be moved ! */
        sw      t2, 0x2cf8 (t0)         /* Write PCI config space address reg */
        lw      $0, 0x2cf8 (t0)         /* wbflush() insures write-then-read */
 
        lhu     v0, 0x2cfc (t1)         /* v0 = config space halfword read */
 
        j       ra                      /* Return to caller. */
        sw      $0, 0x2cf8 (t0)         /* BDSLOT - Park PCI bus */
 
        .set    reorder
FUNC_END (hal_sysConfigInHalfWord)
 
/*
 * Function:
 *      unsigned short sysConfigInWord (int pciConfigAddress) ;
 *
 * Inputs:
 *      a0 - pciConfigAddress
 *
 * Outputs:
 *      v0 - word read from PCI Configuration space.
 */
 
FUNC_START (hal_sysConfigInWord)
        li      t0, 0xb8000000          /* t0 = Upper 16 bits of PCI config */
                                        /*      space address register */
        .set    noreorder               /* Instructions must not be moved ! */
        sw      a0, 0x2cf8 (t0)         /* Write PCI config space address reg */
        lw      $0, 0x2cf8 (t0)         /* wbflush() insures write-then-read */
 
        lw      v0, 0x2cfc (t0)         /* v0 = config space word read */
 
        j       ra                      /* Return to caller. */
        sw      $0, 0x2cf8 (t0)         /* BDSLOT - Park PCI bus */
 
        .set    reorder
FUNC_END(hal_sysConfigInWord)
 
 
##-----------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
 
        .extern hal_default_isr
        .data
 
        .globl  hal_interrupt_handlers
hal_interrupt_handlers:
        .rept   30
        .long   hal_default_isr
        .endr
 
        .globl  hal_interrupt_data
hal_interrupt_data:
        .rept   30
        .long   0
        .endr
 
        .globl  hal_interrupt_objects
hal_interrupt_objects:
        .rept   30
        .long   0
        .endr
 
##-----------------------------------------------------------------------------
## end of platform.S
 

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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [mips/] [idt79s334a/] [current/] [src/] [platform.S] - Blame information for rev 786

Line No.	Rev	Author	Line
1	786	skrzyp	`##=============================================================================`
2			`##`
3			`## platform.S`
4			`##`
5			`## MIPS IDT platform code`
6			`##`
7			`##=============================================================================`
8			`## ####ECOSGPLCOPYRIGHTBEGIN####`
9			`## -------------------------------------------`
10			`## This file is part of eCos, the Embedded Configurable Operating System.`
11			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.`
12			`##`
13			`## eCos is free software; you can redistribute it and/or modify it under`
14			`## the terms of the GNU General Public License as published by the Free`
15			`## Software Foundation; either version 2 or (at your option) any later`
16			`## version.`
17			`##`
18			`## eCos is distributed in the hope that it will be useful, but WITHOUT`
19			`## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`## for more details.`
22			`##`
23			`## You should have received a copy of the GNU General Public License`
24			`## along with eCos; if not, write to the Free Software Foundation, Inc.,`
25			`## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
26			`##`
27			`## As a special exception, if other files instantiate templates or use`
28			`## macros or inline functions from this file, or you compile this file`
29			`## and link it with other works to produce a work based on this file,`
30			`## this file does not by itself cause the resulting work to be covered by`
31			`## the GNU General Public License. However the source code for this file`
32			`## must still be made available in accordance with section (3) of the GNU`
33			`## General Public License v2.`
34			`##`
35			`## This exception does not invalidate any other reasons why a work based`
36			`## on this file might be covered by the GNU General Public License.`
37			`## -------------------------------------------`
38			`## ####ECOSGPLCOPYRIGHTEND####`
39			`##=============================================================================`
40			`#######DESCRIPTIONBEGIN####`
41			`##`
42			`## Author(s): tmichals`
43			`## Contributors: nickg`
44			`## Date: 2002-10-02`
45			`## Purpose:`
46			`## Description: MIPS IDT platform code`
47			`##`
48			`######DESCRIPTIONEND####`
49			`##`
50			`##=============================================================================`
51
52			`#include`
53			`#include`
54
55			`#ifdef CYGPKG_KERNEL`
56			`# include`
57			`#endif`
58
59			`#include`
60			`#include`
61
62
63			`FUNC_START(hal_memc_setup)`
64			`#define PIO_BASE_ADDR 0xb8000600`
65			`#define PIO_DC_SET 0x00500050`
66			`#define PIO_DC_MASK 0xff0fff0f`
67
68			`li t0,PIO_BASE_ADDR`
69			`lw t1,0x4(t0)`
70			`nop`
71			`li t2,PIO_DC_MASK #mask the UART bits`
72			`and t1,t1,t2`
73			`nop`
74			`li t2,PIO_DC_SET #rx0=rx1=input, tx0=tx1=output`
75			`or t1,t1,t2`
76			`nop`
77			`sw t1,0x4(t0)`
78
79
80			`li t0,PORT_WIDTH_CNTL_REG /* Set PortWidth and Bus parameters */`
81			`li t1,PORT_WIDTH_CNTL_VAL`
82			`sw t1,0(t0)`
83
84			`li t0,BUS_TURN_AROUND_CNTRL_REG`
85			`li t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0x18000000*/`
86			`sw t1,0(t0)`
87
88			`li t0,BUS_TURN_AROUND_REG`
89			`li t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0xffffe204*/`
90			`sw t1,0(t0)`
91
92
93			`li t0,ADDRESS_LATCH_TIMING_REG`
94			`li t1,ADDRESS_LATCH_TIMING_VAL`
95			`sw t1,0(t0)`
96
97
98
99			`/* CHIP SELECT 0 for FLASH */`
100			`li t0,MEM_BASE_BASE`
101			`li t1,MBA_REG0`
102			`sw t1,0(t0) /* 0x18000080 */`
103			`li t1,MBM_REG0`
104			`sw t1,0x4(t0) /* 0x18000084 */`
105			`li t0,MEM_CTL_BASE`
106			`li t1,MCR_CS0_BS`
107			`sw t1,0(t0) /* 0x18000200 */`
108
109			`/* CHIP SELECT 1 for FLASH */`
110
111			`li t0,MEM_BASE_BASE`
112			`li t1,MBA_REG1`
113			`sw t1,8(t0) /* 0x18000088 */`
114			`li t1,MBM_REG1 /* 0x1800008C */`
115			`sw t1,0xc(t0)`
116			`li t0,MEM_CTL_BASE`
117			`li t1,MCR_CS1_BS /* chip select 2 for other flash */`
118			`sw t1,0x4(t0) /* 0x18000204 */`
119
120			`/* CHIP SELECT 2*/`
121			`li t1,MCR_CS2_BS`
122			`sw t1,0x8(t0)`
123
124			`/* CHIP SELECT 3*/`
125			`li t1,MCR_CS3_BS`
126			`sw t1,0xc(t0)`
127
128
129			`/* CHIP SELECT 4*/`
130			`li t1,MCR_CS4_BS`
131			`sw t1,0x10(t0)`
132
133
134			`/* CHIP SELECT 5*/`
135			`li t1,MCR_CS5_BS`
136			`sw t1,0x14(t0)`
137
138
139
140			`li t0,RHEA_IREG_BASE`
141			`li t1,DISABLE_TIMER`
142			`sw t1,0x730(t0)`
143
144			`li t1,0`
145			`sw t1,0x310(t0)`
146
147
148			`/* SDRAM Initialization:- Start Here! */`
149			`li t1,DRAM_BNK0_BASE`
150			`sw t1,0xc0(t0)`
151			`li t1,DRAM_BNK1_BASE`
152			`sw t1,0xc8(t0)`
153			`li t1,DRAM_BNK2_BASE`
154			`sw t1,0xd0(t0)`
155			`li t1,DRAM_BNK3_BASE`
156			`sw t1,0xd8(t0)`
157
158			`li t1,DRAM_BNK0_MASK`
159			`sw t1,0xc4(t0)`
160			`li t1,DRAM_BNK1_MASK`
161			`sw t1,0xcc(t0)`
162			`li t1,DRAM_BNK2_MASK`
163			`sw t1,0xd4(t0)`
164			`li t1,DRAM_BNK3_MASK`
165			`sw t1,0xdc(t0)`
166
167			`li t0,MEM_BASE_BASE`
168			`li t1,MBA_REG1`
169			`sw t1,0x8(t0)`
170			`li t1,MBM_REG1`
171			`sw t1,0xc(t0)`
172
173			`li t0,TIMER_BASE`
174			`li t1,DISABLE_TIMER`
175			`sw t1,0x60(t0)`
176			`nop`
177			`li t1,0x0`
178			`sw t1,0x64(t0)`
179			`li t1,CPU_BERR_BS`
180			`sw t1,0x48(t0)`
181			`li t1,IP_BERR_BS`
182			`sw t1,0x58(t0)`
183
184
185			`li t0,RHEA_IREG_BASE`
186			`li t1,SDRAM_CR_BS`
187			`sw t1,0x300(t0)`
188
189			`li t2,2`
190			`li t3,0`
191			`1:`
192			`li t1,SDRAM_PC_VAL`
193			`sw t1,0x300(t0)`
194			`nop`
195			`li t4,SDRAM_TEST_PATTERN`
196			`li t5,K1BASE \| DRAM_BNK0_BASE`
197			`sw t4,0x1000(t5)`
198			`addu t3,1`
199			`bne t3,t2,1b`
200			`nop`
201
202			`li t2,2`
203			`li t3,0`
204			`1:`
205			`li t1,SDRAM_RFRSH_CMD`
206			`sw t1,0x300(t0)`
207			`sw t4,0x0(t5)`
208			`addu t3,1`
209			`bne t3,t2,1b`
210			`nop`
211
212
213			`li t1,SDRAM_MODE_REG`
214			`sw t1,0x300(t0)`
215			`sw t4,0x80(t5)`
216
217			`li t0,TIMER_BASE`
218			`li t1,DRAM_RF_CMPR_BS`
219			`sw t1,0x68(t0)`
220			`li t1,ENABLE_TIMER`
221			`sw t1,0x60(t0)`
222
223
224			`/* Delay for Sdram to stabilise with fast refresh */`
225			`li t2, 0x2FF00`
226			`1:`
227			`subu t2, 1`
228			`bne t2, zero,1b`
229			`nop`
230
231			`/* Change the Sdram refresh to a standard refresh */`
232			`li t0,TIMER_BASE`
233			`li t1,DRAM_RF_CMPR_SE_BS`
234			`sw t1,0x68(t0)`
235
236			`/* SDRAM Initialization : End Here ! */`
237
238
239			`jr ra`
240			`nop`
241
242			`FUNC_END(hal_memc_setup)`
243
244
245			`FUNC_START(hal_setTlbEntry)`
246			`.set noreorder`
247			`mtc0 a0,C0_INX`
248			`mtc0 a1,C0_TLBHI`
249			`mtc0 a2,C0_TLBLO0`
250			`mtc0 a3,C0_TLBLO1`
251			`nop`
252			`nop`
253			`tlbwi`
254			`nop`
255			`.set reorder`
256
257			`j ra`
258			`nop`
259			`FUNC_END(hal_setTlbEntry)`
260
261			`FUNC_START(hal_setPageSize)`
262			`.set noreorder`
263			`mtc0 a0,C0_PAGEMASK`
264			`nop`
265			`nop`
266			`.set reorder`
267			`j ra`
268			`nop`
269			`FUNC_END(hal_setPageSize)`
270
271
272
273
274			`FUNC_START (hal_sysConfigOutByte)`
275			`.set noreorder`
276			`li t0,0xb8002cf8`
277			`li t1,0xb8002cfc`
278			`li t2,0x3`
279			`and a2,t2`
280			`sw a0,0x0(t0)`
281			`xori a2,0x3`
282			`or t1,a2`
283			`sb a1,0x0(t1)`
284			`j ra`
285			`nop`
286			`.set reorder`
287			`FUNC_END(hal_sysConfigOutByte)`
288
289
290
291			`FUNC_START(hal_sysConfigOutHalfWord)`
292			`.set noreorder`
293			`li t0,0xb8002cf8`
294			`li t1,0xb8002cfc`
295			`li t2,0x3`
296			`and a2,t2`
297			`sw a0,0x0(t0)`
298			`xori a2,0x2`
299			`or t1,a2`
300			`sh a1,0x0(t1)`
301			`j ra`
302			`nop`
303			`.set reorder`
304			`FUNC_END (hal_sysConfigOutHalfWord)`
305
306			`FUNC_START (hal_sysConfigOutWord)`
307			`.set noreorder`
308			`li t0,0xb8002cf8`
309			`li t1,0xb8002cfc`
310			`sw a0,0x0(t0)`
311			`sw a1,0x0(t1)`
312			`j ra`
313			`nop`
314			`.set reorder`
315			`FUNC_END (hal_sysConfigOutWord)`
316
317
318			`/*`
319			`* Function:`
320			`* unsigned char sysConfigInByte (int pciConfigAddress) ;`
321			`* Inputs:`
322			`* a0 - pciConfigAddress`
323			`* Outputs:`
324			`* v0 - byte read from PCI Configuration space.`
325			`*/`
326			`FUNC_START (hal_sysConfigInByte)`
327			`sysConfigInByte:`
328			`li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */`
329			`/* space address register */`
330			`andi t1, a0, 0x00000003 /* t1 = PCI config space byte offset. */`
331			`xor t2, t1, a0 /* t2 = PCI config address of */`
332			`/* longword containing byte. */`
333			`xori t1, 0x00000003 /* t1 = big endian byte offset. */`
334			`/* offset 0 -> 3 */`
335			`/* offset 1 -> 2 */`
336			`/* offset 2 -> 1 */`
337			`/* offset 3 -> 0 */`
338			`or t1, t0 /* t1 = byte corrected PCI config */`
339			`/* data address. */`
340			`.set noreorder /* Instructions must not be moved ! */`
341			`sw t2, 0x2cf8 (t0) /* Write PCI config space address reg */`
342			`lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */`
343
344			`lbu v0, 0x2cfc (t1) /* v0 = PCI config space byte read */`
345
346			`j ra /* Return to caller. */`
347			`sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */`
348
349			`.set reorder`
350			`FUNC_END (hal_sysConfigInByte)`
351
352			`/*`
353			`* Function:`
354			`* unsigned short sysConfigInHalfWord (int pciConfigAddress) ;`
355			`*`
356			`* Inputs:`
357			`* a0 - pciConfigAddress`
358			`*`
359			`* Outputs:`
360			`* v0 - half word read from PCI Configuration space.`
361			`*/`
362
363			`FUNC_START (hal_sysConfigInHalfWord)`
364			`sysConfigInHalfWord:`
365			`li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */`
366			`/* space address register */`
367			`andi t1, a0, 0x00000003 /* t1 = Config space halfword offset. */`
368			`xor t2, t1, a0 /* t2 = PCI config address of */`
369			`/* longword containing halfword. */`
370
371			`xori t1, 0x00000002 /* t1 = big endian halfword offset. */`
372			`/* offset 0 -> 2 */`
373			`/* offset 2 -> 0 */`
374
375			`or t1, t0 /* t1 = halfword corrected PCI config */`
376			`/* data address. */`
377			`.set noreorder /* Instructions must not be moved ! */`
378			`sw t2, 0x2cf8 (t0) /* Write PCI config space address reg */`
379			`lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */`
380
381			`lhu v0, 0x2cfc (t1) /* v0 = config space halfword read */`
382
383			`j ra /* Return to caller. */`
384			`sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */`
385
386			`.set reorder`
387			`FUNC_END (hal_sysConfigInHalfWord)`
388
389			`/*`
390			`* Function:`
391			`* unsigned short sysConfigInWord (int pciConfigAddress) ;`
392			`*`
393			`* Inputs:`
394			`* a0 - pciConfigAddress`
395			`*`
396			`* Outputs:`
397			`* v0 - word read from PCI Configuration space.`
398			`*/`
399
400			`FUNC_START (hal_sysConfigInWord)`
401			`li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */`
402			`/* space address register */`
403			`.set noreorder /* Instructions must not be moved ! */`
404			`sw a0, 0x2cf8 (t0) /* Write PCI config space address reg */`
405			`lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */`
406
407			`lw v0, 0x2cfc (t0) /* v0 = config space word read */`
408
409			`j ra /* Return to caller. */`
410			`sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */`
411
412			`.set reorder`
413			`FUNC_END(hal_sysConfigInWord)`
414
415
416			`##-----------------------------------------------------------------------------`
417			`# Interrupt vector tables.`
418			`# These tables contain the isr, data and object pointers used to deliver`
419			`# interrupts to user code.`
420
421			`.extern hal_default_isr`
422			`.data`
423
424			`.globl hal_interrupt_handlers`
425			`hal_interrupt_handlers:`
426			`.rept 30`
427			`.long hal_default_isr`
428			`.endr`
429
430			`.globl hal_interrupt_data`
431			`hal_interrupt_data:`
432			`.rept 30`
433			`.long 0`
434			`.endr`
435
436			`.globl hal_interrupt_objects`
437			`hal_interrupt_objects:`
438			`.rept 30`
439			`.long 0`
440			`.endr`
441
442			`##-----------------------------------------------------------------------------`
443			`## end of platform.S`
444