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skrzyp |
#ifndef CYGONCE_HAL_PLF_INTR_H
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#define CYGONCE_HAL_PLF_INTR_H
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//==========================================================================
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//
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// plf_intr.h
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//
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// Malta Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jskov,
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// gthomas, jlarmour, dmoseley
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// Date: 2001-03-20
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for the Malta board.
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//
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// Usage:
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// #include <cyg/hal/plf_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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// First an assembly safe part
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//--------------------------------------------------------------------------
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// Interrupt vectors.
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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// These are decoded via the IP bits of the cause
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// register when an external interrupt is delivered.
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#define CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR 0
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#define CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_SMI 1
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#define CYGNUM_HAL_INTERRUPT_CBUS_UART 2
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#define CYGNUM_HAL_INTERRUPT_COREHI 3
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#define CYGNUM_HAL_INTERRUPT_CORELO 4
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#define CYGNUM_HAL_INTERRUPT_COMPARE 5
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE 6
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#define CYGNUM_HAL_INTERRUPT_CTRL1_BASE 6
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#define CYGNUM_HAL_INTERRUPT_TIMER 6
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#define CYGNUM_HAL_INTERRUPT_KEYBOARD 7
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#define CYGNUM_HAL_INTERRUPT_CASCADE 8 // this is where int ctrl2 is cascaded
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#define CYGNUM_HAL_INTERRUPT_TTY1 9
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#define CYGNUM_HAL_INTERRUPT_TTY0 10
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#define CYGNUM_HAL_INTERRUPT_11 11
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#define CYGNUM_HAL_INTERRUPT_FLOPPY 12
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#define CYGNUM_HAL_INTERRUPT_PARALLEL 13
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#define CYGNUM_HAL_INTERRUPT_CTRL2_BASE 14
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#define CYGNUM_HAL_INTERRUPT_REAL_TIME_CLOCK 14
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#define CYGNUM_HAL_INTERRUPT_I2C 15
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#define CYGNUM_HAL_INTERRUPT_PCI_AB 16
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#define CYGNUM_HAL_INTERRUPT_PCI_CD 17
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#define CYGNUM_HAL_INTERRUPT_MOUSE 18
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#define CYGNUM_HAL_INTERRUPT_19 19
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#define CYGNUM_HAL_INTERRUPT_IDE_PRIMARY 20
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#define CYGNUM_HAL_INTERRUPT_IDE_SECONDARY 21
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#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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// This overlaps with CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE above but it
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// doesn't matter. It's only used by the HAL to access the special
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// chaining entry in the ISR tables. All other attempted access to
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// the ISR table will be redirected to this entry (courtesy of
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// HAL_TRANSLATE_VECTOR). The other vector definitions are still
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// valid, but only for enable/disable/config etc. (i.e., in chaining
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// mode they have associated entries in the ISR tables).
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#define CYGNUM_HAL_INTERRUPT_CHAINING 6
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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(_index_) = CYGNUM_HAL_INTERRUPT_CHAINING
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// Min/Max ISR numbers
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_CHAINING
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#else
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// Min/Max ISR numbers
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_IDE_SECONDARY
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#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
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// The vector used by the Real time clock
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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#ifndef __ASSEMBLER__
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/plf_io.h>
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//--------------------------------------------------------------------------
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// Interrupt controller access.
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#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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// Array which stores the configured priority levels for the configured
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// interrupts.
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externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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CYG_MACRO_START \
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if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL2_BASE; \
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HAL_READ_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
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_mask_ |= (1<<_shift_); \
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
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} \
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else /* CTRL1 */ \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL1_BASE; \
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HAL_READ_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
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_mask_ |= (1<<_shift_); \
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"or $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL2_BASE; \
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HAL_READ_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
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_mask_ &= ~(1<<_shift_); \
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
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} \
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else /* CTRL1 */ \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL1_BASE; \
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HAL_READ_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
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_mask_ &= ~(1<<_shift_); \
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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cyg_uint32 _srvector_ = _vector_; \
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if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
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{ \
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW3, 0x20 ); \
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} \
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if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL1_BASE) \
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{ \
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW3, 0x20 ); \
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} \
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if ((_vector_) >= CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) { \
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_srvector_ = CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR; \
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} \
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asm volatile ( \
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"mfc0 $3,$13\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$13\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_srvector_) \
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: "$2", "$3" \
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); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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CYG_MACRO_START \
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if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL2_BASE; \
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HAL_READ_UINT8(HAL_PIIX4_ELCR2, _mask_ ); \
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_mask_ &= ~(1<<_shift_); \
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if (_level_) _mask_ |= (1<<_shift_); \
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_mask_ &= HAL_PIIX4_ELCR2_MASK; \
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HAL_WRITE_UINT8(HAL_PIIX4_ELCR2, _mask_ ); \
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} \
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else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL1_BASE) \
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{ \
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cyg_uint8 _mask_; \
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cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL1_BASE; \
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HAL_READ_UINT8(HAL_PIIX4_ELCR1, _mask_ ); \
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_mask_ &= ~(1<<_shift_); \
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if (_level_) _mask_ |= (1<<_shift_); \
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_mask_ &= HAL_PIIX4_ELCR1_MASK; \
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HAL_WRITE_UINT8(HAL_PIIX4_ELCR1, _mask_ ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
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#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Control-C support.
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#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
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# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_SER
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externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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# define HAL_CTRLC_ISR hal_ctrlc_isr
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#endif
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//----------------------------------------------------------------------------
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// Reset.
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#ifndef CYGHWR_HAL_RESET_DEFINED
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extern void hal_malta_reset( void );
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#define CYGHWR_HAL_RESET_DEFINED
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#define HAL_PLATFORM_RESET() hal_malta_reset()
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#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
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#endif // CYGHWR_HAL_RESET_DEFINED
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#endif // __ASSEMBLER__
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PLF_INTR_H
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// End of plf_intr.h
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