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//==========================================================================
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//
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// plf_misc.c
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//
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// HAL platform miscellaneous functions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jlarmour, dmoseley, jskov
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// Date: 2001-03-20
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// Purpose: HAL miscellaneous functions
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// Description: This file contains miscellaneous functions provided by the
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// HAL.
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h> // Base types
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/hal/hal_arch.h> // architectural definitions
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#include <cyg/hal/hal_intr.h> // Interrupt handling
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#include <cyg/hal/hal_cache.h> // Cache handling
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#include <cyg/hal/hal_if.h>
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#include <cyg/io/pci_hw.h>
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#include <cyg/io/pci.h>
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//--------------------------------------------------------------------------
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externC void cyg_hal_init_superIO(void);
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static void hal_init_irq(void);
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//--------------------------------------------------------------------------
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void hal_platform_init(void)
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{
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HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, 0xff);
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#if defined(CYGPKG_CYGMON)
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'C');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'Y');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'G');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'M');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'O');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 'N');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
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#elif defined(CYGPKG_REDBOOT)
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, 'R');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'e');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'd');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'B');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'o');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 't');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
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#else
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' ');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'e');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'C');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 's');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' ');
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HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
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#endif
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// Initialize PCI before VV since serial registers need to be in
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// place before that time.
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cyg_hal_plf_pci_init();
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// Init interrupt controller on PIIX4
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hal_init_irq();
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// Initialize super IO controller
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cyg_hal_init_superIO();
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// Set up eCos/ROM interfaces
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hal_if_init();
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HAL_ICACHE_INVALIDATE_ALL();
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HAL_ICACHE_ENABLE();
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HAL_DCACHE_INVALIDATE_ALL();
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HAL_DCACHE_ENABLE();
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}
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/*------------------------------------------------------------------------*/
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/* Reset support */
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void hal_malta_reset(void)
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{
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*HAL_MALTA_SOFTRES = HAL_MALTA_GORESET;
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for(;;); // wait for it
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}
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//--------------------------------------------------------------------------
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// IRQ init
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static void
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hal_init_irq(void)
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{
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cyg_uint32 v;
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// Enable SERIRQ on PIIX4
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v = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
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CYG_PCI_CFG_PIIX4_GENCFG);
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v |= CYG_PCI_CFG_PIIX4_GENCFG_SERIRQ;
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cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
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CYG_PCI_CFG_PIIX4_GENCFG, v);
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// Enable SERIRQ and set to continous mode.
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v = cyg_hal_plf_pci_cfg_read_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
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CYG_PCI_CFG_PIIX4_SERIRQC);
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v |= CYG_PCI_CFG_PIIX4_SERIRQC_ENABLE | CYG_PCI_CFG_PIIX4_SERIRQC_CONT;
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cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
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CYG_PCI_CFG_PIIX4_SERIRQC, v);
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// Init master interrupt controller (4.2.2, pp 74-78)
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW1, HAL_PIIX4_ICW1_SEL | HAL_PIIX4_ICW1_WR);
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW2, CYGNUM_HAL_INTERRUPT_CTRL1_BASE - CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE);
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW3, HAL_PIIX4_ICW3_CASCADE);
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW4, HAL_PIIX4_ICW4_UPMODE);
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW3, HAL_PIIX4_OCW3_SEL | HAL_PIIX4_OCW3_ESSM | HAL_PIIX4_OCW3_REQ);
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// Init slave interrupt controller
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW1, HAL_PIIX4_ICW1_SEL | HAL_PIIX4_ICW1_WR);
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW2, CYGNUM_HAL_INTERRUPT_CTRL2_BASE - CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE);
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW3, HAL_PIIX4_ICW3_SLAVE);
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW4, HAL_PIIX4_ICW4_UPMODE);
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// Mask all sources
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HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1,
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0xff & ~(1<<(CYGNUM_HAL_INTERRUPT_CASCADE-CYGNUM_HAL_INTERRUPT_CTRL1_BASE)));
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HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW1, 0xff);
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// Set PCI interrupt routing and set those interrupts to level
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// sense as per 4.1.10 page 59 in 82371AB doc.
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v = ( (CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 0
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|(CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 8
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|(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 16
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|(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 24);
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cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
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CYG_PCI_CFG_PIIX4_PIRQR, v);
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HAL_READ_UINT8(HAL_PIIX4_ELCR2, v);
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v |= (1 << (CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_CTRL2_BASE))
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|(1 << (CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_CTRL2_BASE));
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HAL_WRITE_UINT8(HAL_PIIX4_ELCR2, v);
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// Let south bridge interrupt
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HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR);
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}
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/*------------------------------------------------------------------------*/
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/* PCI support */
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#if defined(CYGPKG_IO_PCI)
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#define PCIMEM_START 0x08000000 // PCI memory address
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#define PCIMEM_SIZE 0x10000000 // 256 MByte
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#define PCIIO_START 0x18000000 // PCI io address
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#define PCIIO_SIZE 0x03E00000 // 62 MByte
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static int __check_bar(cyg_uint32 addr, cyg_uint32 size)
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{
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int n;
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for (n = 0; n <= 31; n++)
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if (size == (1 << n)) {
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/* Check that address is naturally aligned */
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if (addr != (addr & ~(size-1)))
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return 0;
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return size - 1;
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}
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return 0;
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}
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// One-time PCI initialization.
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void cyg_hal_plf_pci_init(void)
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{
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cyg_uint32 bar_ena, start10, start32, end, size;
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cyg_uint8 next_bus;
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cyg_uint32 v;
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| 229 |
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static int initialized = 0;
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if (initialized) return;
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initialized = 1;
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// Setup for bus mastering
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cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_COMMAND,
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CYG_PCI_CFG_COMMAND_IO |
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CYG_PCI_CFG_COMMAND_MEMORY |
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CYG_PCI_CFG_COMMAND_MASTER |
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CYG_PCI_CFG_COMMAND_PARITY |
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| 240 |
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CYG_PCI_CFG_COMMAND_SERR);
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| 241 |
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| 242 |
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// Setup latency timer field
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cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_LATENCY_TIMER, 6);
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| 245 |
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// Disable all BARs
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| 247 |
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bar_ena = 0x1ff;
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| 248 |
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// Check for active SCS10
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| 250 |
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start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << 21;
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end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << 21;
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| 252 |
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if (end > start10) {
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| 253 |
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if ((size = __check_bar(start10, end - start10)) != 0) {
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| 254 |
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// Enable BAR
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| 255 |
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HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size);
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| 256 |
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bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
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| 257 |
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}
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| 258 |
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}
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| 259 |
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| 260 |
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// Check for active SCS32
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| 261 |
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start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << 21;
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| 262 |
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end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << 21;
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| 263 |
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if (end > start32) {
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| 264 |
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if ((size = __check_bar(start32, end - start32)) != 0) {
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| 265 |
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// Enable BAR
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| 266 |
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HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size);
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| 267 |
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bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32;
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| 268 |
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}
|
| 269 |
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}
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| 270 |
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| 271 |
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bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
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| 272 |
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HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena);
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| 273 |
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| 274 |
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| 275 |
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cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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| 276 |
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CYG_PCI_CFG_BAR_0, 0xffffffff);
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| 277 |
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| 278 |
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end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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| 279 |
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CYG_PCI_CFG_BAR_0);
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| 280 |
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| 281 |
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cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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| 282 |
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CYG_PCI_CFG_BAR_0, start10);
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| 283 |
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| 284 |
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| 285 |
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cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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| 286 |
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CYG_PCI_CFG_BAR_1, 0xffffffff);
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| 287 |
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| 288 |
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end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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| 289 |
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CYG_PCI_CFG_BAR_1);
|
| 290 |
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| 291 |
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cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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| 292 |
|
|
CYG_PCI_CFG_BAR_1, start32);
|
| 293 |
|
|
|
| 294 |
|
|
|
| 295 |
|
|
// enable ISA bridge on PIIX4
|
| 296 |
|
|
v = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
|
| 297 |
|
|
CYG_PCI_CFG_PIIX4_GENCFG);
|
| 298 |
|
|
v |= CYG_PCI_CFG_PIIX4_GENCFG_ISA;
|
| 299 |
|
|
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
|
| 300 |
|
|
CYG_PCI_CFG_PIIX4_GENCFG, v);
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
v = cyg_hal_plf_pci_cfg_read_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
|
| 304 |
|
|
CYG_PCI_CFG_PIIX4_TOM);
|
| 305 |
|
|
v &= ~CYG_PCI_CFG_PIIX4_TOM_TOM_MASK;
|
| 306 |
|
|
v |= CYG_PCI_CFG_PIIX4_TOM_TOM_16M;
|
| 307 |
|
|
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
|
| 308 |
|
|
CYG_PCI_CFG_PIIX4_TOM, v);
|
| 309 |
|
|
|
| 310 |
|
|
cyg_pci_init();
|
| 311 |
|
|
// Configure PCI bus.
|
| 312 |
|
|
next_bus = 1;
|
| 313 |
|
|
cyg_pci_configure_bus(0, &next_bus);
|
| 314 |
|
|
}
|
| 315 |
|
|
|
| 316 |
|
|
|
| 317 |
|
|
// Check for configuration error.
|
| 318 |
|
|
static int pci_config_errcheck(void)
|
| 319 |
|
|
{
|
| 320 |
|
|
cyg_uint32 irq;
|
| 321 |
|
|
|
| 322 |
|
|
// Check for master or target abort
|
| 323 |
|
|
irq = HAL_GALILEO_GETREG(HAL_GALILEO_IRQ_CAUSE_OFFSET);
|
| 324 |
|
|
|
| 325 |
|
|
if (irq & (HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT)) {
|
| 326 |
|
|
// Error. Clear bits.
|
| 327 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_IRQ_CAUSE_OFFSET,
|
| 328 |
|
|
~(HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT));
|
| 329 |
|
|
return 1;
|
| 330 |
|
|
}
|
| 331 |
|
|
return 0;
|
| 332 |
|
|
}
|
| 333 |
|
|
|
| 334 |
|
|
cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
|
| 335 |
|
|
cyg_uint32 devfn,
|
| 336 |
|
|
cyg_uint32 offset)
|
| 337 |
|
|
{
|
| 338 |
|
|
cyg_uint32 config_data;
|
| 339 |
|
|
|
| 340 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
|
| 341 |
|
|
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
|
| 342 |
|
|
(bus << 16) | (devfn << 8) | offset);
|
| 343 |
|
|
|
| 344 |
|
|
config_data = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
|
| 345 |
|
|
|
| 346 |
|
|
if (pci_config_errcheck())
|
| 347 |
|
|
return 0xffffffff;
|
| 348 |
|
|
return config_data;
|
| 349 |
|
|
}
|
| 350 |
|
|
|
| 351 |
|
|
cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
|
| 352 |
|
|
cyg_uint32 devfn,
|
| 353 |
|
|
cyg_uint32 offset)
|
| 354 |
|
|
{
|
| 355 |
|
|
cyg_uint32 config_dword;
|
| 356 |
|
|
|
| 357 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
|
| 358 |
|
|
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
|
| 359 |
|
|
(bus << 16) | (devfn << 8) | (offset & ~3));
|
| 360 |
|
|
|
| 361 |
|
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
|
| 362 |
|
|
|
| 363 |
|
|
if (pci_config_errcheck())
|
| 364 |
|
|
return 0xffff;
|
| 365 |
|
|
return (cyg_uint16)((config_dword >> ((offset & 3) * 8)) & 0xffff);
|
| 366 |
|
|
}
|
| 367 |
|
|
|
| 368 |
|
|
cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
|
| 369 |
|
|
cyg_uint32 devfn,
|
| 370 |
|
|
cyg_uint32 offset)
|
| 371 |
|
|
{
|
| 372 |
|
|
cyg_uint32 config_dword;
|
| 373 |
|
|
|
| 374 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
|
| 375 |
|
|
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
|
| 376 |
|
|
(bus << 16) | (devfn << 8) | (offset & ~3));
|
| 377 |
|
|
|
| 378 |
|
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
|
| 379 |
|
|
|
| 380 |
|
|
if (pci_config_errcheck())
|
| 381 |
|
|
return 0xff;
|
| 382 |
|
|
return (cyg_uint8)((config_dword >> ((offset & 3) * 8)) & 0xff);
|
| 383 |
|
|
}
|
| 384 |
|
|
|
| 385 |
|
|
void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
|
| 386 |
|
|
cyg_uint32 devfn,
|
| 387 |
|
|
cyg_uint32 offset,
|
| 388 |
|
|
cyg_uint32 data)
|
| 389 |
|
|
{
|
| 390 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
|
| 391 |
|
|
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
|
| 392 |
|
|
(bus << 16) | (devfn << 8) | offset);
|
| 393 |
|
|
|
| 394 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, data);
|
| 395 |
|
|
|
| 396 |
|
|
(void)pci_config_errcheck();
|
| 397 |
|
|
}
|
| 398 |
|
|
|
| 399 |
|
|
void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
|
| 400 |
|
|
cyg_uint32 devfn,
|
| 401 |
|
|
cyg_uint32 offset,
|
| 402 |
|
|
cyg_uint16 data)
|
| 403 |
|
|
{
|
| 404 |
|
|
cyg_uint32 config_dword, shift;
|
| 405 |
|
|
|
| 406 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
|
| 407 |
|
|
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
|
| 408 |
|
|
(bus << 16) | (devfn << 8) | (offset & ~3));
|
| 409 |
|
|
|
| 410 |
|
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
|
| 411 |
|
|
if (pci_config_errcheck())
|
| 412 |
|
|
return;
|
| 413 |
|
|
|
| 414 |
|
|
shift = (offset & 3) * 8;
|
| 415 |
|
|
config_dword &= ~(0xffff << shift);
|
| 416 |
|
|
config_dword |= (data << shift);
|
| 417 |
|
|
|
| 418 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
|
| 419 |
|
|
|
| 420 |
|
|
(void)pci_config_errcheck();
|
| 421 |
|
|
}
|
| 422 |
|
|
|
| 423 |
|
|
void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
|
| 424 |
|
|
cyg_uint32 devfn,
|
| 425 |
|
|
cyg_uint32 offset,
|
| 426 |
|
|
cyg_uint8 data)
|
| 427 |
|
|
{
|
| 428 |
|
|
cyg_uint32 config_dword, shift;
|
| 429 |
|
|
|
| 430 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
|
| 431 |
|
|
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
|
| 432 |
|
|
(bus << 16) | (devfn << 8) | (offset & ~3));
|
| 433 |
|
|
|
| 434 |
|
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
|
| 435 |
|
|
if (pci_config_errcheck())
|
| 436 |
|
|
return;
|
| 437 |
|
|
|
| 438 |
|
|
shift = (offset & 3) * 8;
|
| 439 |
|
|
config_dword &= ~(0xff << shift);
|
| 440 |
|
|
config_dword |= (data << shift);
|
| 441 |
|
|
|
| 442 |
|
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
|
| 443 |
|
|
|
| 444 |
|
|
(void)pci_config_errcheck();
|
| 445 |
|
|
}
|
| 446 |
|
|
#endif // defined(CYGPKG_IO_PCI)
|
| 447 |
|
|
|
| 448 |
|
|
|
| 449 |
|
|
/*------------------------------------------------------------------------*/
|
| 450 |
|
|
/* IDE support */
|
| 451 |
|
|
|
| 452 |
|
|
int
|
| 453 |
|
|
cyg_hal_plf_ide_init(void)
|
| 454 |
|
|
{
|
| 455 |
|
|
cyg_uint32 v;
|
| 456 |
|
|
|
| 457 |
|
|
// enable IDE
|
| 458 |
|
|
v = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_IDE),
|
| 459 |
|
|
CYG_PCI_CFG_PIIX4_IDETIM);
|
| 460 |
|
|
v |= (CYG_PCI_CFG_PIIX4_IDETIM_IDE << 16) | CYG_PCI_CFG_PIIX4_IDETIM_IDE;
|
| 461 |
|
|
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_IDE),
|
| 462 |
|
|
CYG_PCI_CFG_PIIX4_IDETIM, v);
|
| 463 |
|
|
return HAL_IDE_NUM_CONTROLLERS;
|
| 464 |
|
|
}
|
| 465 |
|
|
|
| 466 |
|
|
|
| 467 |
|
|
/*------------------------------------------------------------------------*/
|
| 468 |
|
|
/* End of plf_misc.c */
|
