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#ifndef CYGONCE_HAL_VAR_ARCH_H
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#define CYGONCE_HAL_VAR_ARCH_H
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//==========================================================================
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//
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// var_arch.h
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//
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// Architecture specific abstractions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, dmoseley
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// Date: 1999-02-17
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// Purpose: Define architecture abstractions
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// Description: This file contains any extra or modified definitions for
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// this variant of the architecture.
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// Usage: #include <cyg/hal/var_arch.h>
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#ifndef __ASSEMBLER__
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#endif
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//--------------------------------------------------------------------------
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// Define macros for accessing CP0 registers
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#define HAL_GET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ ) \
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{ \
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cyg_uint32 tmp; \
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asm volatile ("mfc0 %0,$%1,%2\nnop\n" \
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: "=r" (tmp) \
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: "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \
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_regval_ = tmp; \
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}
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#define HAL_SET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ ) \
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{ \
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cyg_uint32 tmp = _regval_; \
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asm volatile ("mtc0 %1,$%2,%3\nnop\n" \
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: "=r" (tmp) \
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: "r" (tmp), "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \
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}
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#define HAL_GET_CP0_REGISTER_64( _regval_, _cp0_regno_, _cp0_regsel_ ) \
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HAL_GET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ )
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#define HAL_SET_CP0_REGISTER_64( _regval_, _cp0_regno_, _cp0_regsel_ ) \
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HAL_SET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ )
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//--------------------------------------------------------------------------
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// Bit manipulation macros
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#ifndef CYGHWR_HAL_BIT_INDEXES_DEFINED
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//--------------------------------------------------------
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// Determine the index of the ls bit of the supplied mask.
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#define HAL_LSBIT_INDEX(_index_, _mask_) \
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CYG_MACRO_START \
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unsigned _reg_; \
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\
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_reg_ = (_mask_); \
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_reg_ &= -_reg_; \
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asm volatile ("clz %0, %1\n" \
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: "=r" (_reg_) \
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: "r" (_reg_) ); \
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(_index_) = 31 - _reg_; \
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CYG_MACRO_END
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//--------------------------------------------------------
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// Determine the index of the ms bit of the supplied mask.
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#define HAL_MSBIT_INDEX(_index_, _mask_) \
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CYG_MACRO_START \
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unsigned _reg_; \
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\
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_reg_ = (_mask_); \
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asm volatile ("clz %0, %1\n" \
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: "=r" (_reg_) \
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: "r" (_reg_) ); \
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(_index_) = 31 - _reg_; \
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CYG_MACRO_END
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#define CYGHWR_HAL_BIT_INDEXES_DEFINED
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#endif
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//--------------------------------------------------------------------------
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#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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/* System Control Coprocessor (CP0) exception processing registers */
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/* These supplement the definitions in mips-regs.h */
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#define C0_INDEX $0 /* Index into TLB Array - 4Kc core */
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#define C0_RANDOM $1 /* Randomly generated index into TLB Array - 4Kc core */
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#define C0_ENTRYLO0 $2 /* Low-order portion of the TLB entry for even-numbered virtual pages - 4Kc core */
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#define C0_ENTRYLO1 $3 /* Low-order portion of the TLB entry for odd-numbered virtual pages - 4Kc core */
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#define CO_PAGEMASK $5 /* Pointer to page table entry in memory - 4Kc core */
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#define C0_WIRED $6 /* Number of fixed TLB entries - 4Kc core */
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#define C0_ENTRYHI $10 /* High-order portion of the TLB entry - 4Kc core */
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#define C0_PRId $15 /* Processor Identification and Revision */
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#define C0_CONFIG $16 /* Configuration Register */
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#define C0_LLADDR $17 /* Load linked address */
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#define C0_LLADDR $17 /* Load linked address */
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#define C0_DEBUG $23 /* Debug control and exception status */
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#define C0_DEPC $24 /* Program counter at last debug exception */
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#define C0_TAGLO $28 /* Low-order portion of cache tag interface */
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#define C0_TAGHI $29 /* High-order portion of cache tag interface (not implemented in 4K cores */
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#define C0_DESAVE $31 /* Debug handler scratch pad register */
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/* Coprocessor Register selector field */
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#define C0_SELECTOR_0 0x0
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#define C0_SELECTOR_1 0x1
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/* Status register fields */
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#define SR_RP 0x08000000 /* Enter reduced-power mode */
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#define SR_NMI 0x00080000 /* Reset vector called through assertion of the NMI signal */
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/* Cause register fields */
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#define CAUSE_IV 0x00800000 /* Interrupt vector to use -- Bit=0 -> offset=0x180;
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Bit=1 -> offset=0x200; */
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#define CAUSE_WP 0x00400000 /* Watch exception deferred due to either Status[EXL] or Status[ERL] */
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#define CAUSE_MIPS32IP7 CAUSE_IP8 /* The MIPS32 architecture refers to these bits using a 0 base, */
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#define CAUSE_MIPS32IP6 CAUSE_IP7 /* but the generic mips-regs.h refers to them with a 1 base */
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#define CAUSE_MIPS32IP5 CAUSE_IP6
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#define CAUSE_MIPS32IP4 CAUSE_IP5
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#define CAUSE_MIPS32IP3 CAUSE_IP4
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#define CAUSE_MIPS32IP2 CAUSE_IP3
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#define CAUSE_MIPS32IP1 CAUSE_IP2
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#define CAUSE_MIPS32IP0 CAUSE_IP1
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#define CAUSE_MIPS32HW5 CAUSE_MIPS32IP1
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#define CAUSE_MIPS32HW4 CAUSE_MIPS32IP1
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#define CAUSE_MIPS32HW3 CAUSE_MIPS32IP1
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#define CAUSE_MIPS32HW2 CAUSE_MIPS32IP1
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#define CAUSE_MIPS32HW1 CAUSE_MIPS32IP1
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#define CAUSE_MIPS32HW0 CAUSE_MIPS32IP1
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#define CAUSE_MIPS32SW1 CAUSE_MIPS32IP1
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#define CAUSE_MIPS32SW0 CAUSE_MIPS32IP0
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/* Exception Codes */
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#define EXC_WATCH 23 /* Reference to the Watch address */
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#define EXC_MCHECK 24 /* Machine Check */
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/* Processor Identification fields */
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#define PRId_COMPANY_ID_MASK 0x00FF0000 /* Which company manufactured this chip */
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#define PRId_COMPANY_MIPS_TECHNOLOGIES 0x00010000
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#define PRId_PROCESSOR_ID_MASK 0x0000FF00 /* Which processor is this */
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#define PRId_PROCESSOR_4Kc 0x00008000
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#define PRId_PROCESSOR_4Kp_4Km 0x00008300
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#define PRId_REVISION 0x000000FF /* Which revision is this */
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/* Config register fields */
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#define CONFIG_M 0x80000000 /* Hardwired to '1' to indicate presence of Config1 register */
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#define CONFIG_K23 0x70000000 /* Controls cacheability of kseg2 and kseg3 in BAT */
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#define CONFIG_KU 0x0E000000 /* Controls cacheability of ksegu in BAT */
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#define CONFIG_MDU 0x00100000 /* MDU Type: 0 == Fast Multiplier Array; 1 == Iterative */
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#define CONFIG_MM 0x00060000 /* Merge mode */
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#define CONFIG_BM 0x00010000 /* Burst mode: 0 == Sequential; 1 == SubBlock */
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#define CONFIG_BE 0x00008000 /* Endian mode: 0 == Little Endian; 1 == Big Endian */
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#define CONFIG_AT 0x00006000 /* Architecture Type */
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#define CONFIG_AR 0x00001C00 /* Architecture Revision */
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#define CONFIG_MT 0x00000380 /* MMU Type */
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#define CONFIG_K0 0x00000007 /* kseg0 coherency algorithm */
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/* KSEG cache control codes */
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#define CONFIG_KSEG2_3_CACHEABLE 0x30000000 /* KSeg2 and KSeg3 are cacheable/noncoherent/write-through/no write-allocate */
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#define CONFIG_KSEG2_3_UNCACHEABLE 0x20000000 /* KSeg2 and KSeg3 are cacheable/noncoherent/write-through/no write-allocate */
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#define CONFIG_KSEGU_CACHEABLE 0x06000000 /* KSegu is cacheable/noncoherent/write-through/no write-allocate */
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#define CONFIG_KSEGU_UNCACHEABLE 0x04000000 /* KSegu is cacheable/noncoherent/write-through/no write-allocate */
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#define CONFIG_KSEG0_CACHEABLE 0x00000003 /* KSeg0 is cacheable/noncoherent/write-through/no write-allocate */
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#define CONFIG_KSEG0_UNCACHEABLE 0x00000002 /* KSeg0 is cacheable/noncoherent/write-through/no write-allocate */
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/* Merge mode control codes */
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#define CONFIG_NO_MERGING 0x00000000
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#define CONFIG_SYSAD_VALID_MERGING 0x00200000
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#define CONFIG_FULL_MERGING 0x00400000
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/* Architecture Type codes */
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#define CONFIG_AT_MIPS32 0x00000000
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/* Architecture Revision codes */
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#define CONFIG_AR_REVISION_1 0x00000000
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/* MMU Type codes */
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#define CONFIG_MMU_TYPE_STANDARD_TLB 0x00000080
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#define CONFIG_MMU_TYPE_FIXED 0x00000180
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/* Config1 register fields */
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#define CONFIG1_MMU_SIZE_MASK 0x7E000000 /* Number of entries in the TLB minus 1 */
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#define CONFIG1_IS 0x01C00000 /* Number of instruction cache sets per way */
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#define CONFIG1_IL 0x00380000 /* Instruction cache line size */
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#define CONFIG1_IA 0x00030000 /* Level of Instruction cache associativity */
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#define CONFIG1_DS 0x0000E000 /* Number of data cache sets per way */
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#define CONFIG1_DL 0x00001C00 /* Data cache line size */
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#define CONFIG1_DA 0x00000380 /* Level of Data cache associativity */
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#define CONFIG1_PC 0x00000010 /* Performance Counter registers implemented */
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#define CONFIG1_WR 0x00000008 /* Watch registers implemented */
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#define CONFIG1_CA 0x00000004 /* Code compression implemented */
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#define CONFIG1_EP 0x00000002 /* EJTAG implemented */
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#define CONFIG1_FP 0x00000001 /* FPU implemented */
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/* Instruction cache sets-per-way codes */
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#define CONFIG1_ICACHE_64_SETS_PER_WAY 0x00000000
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#define CONFIG1_ICACHE_128_SETS_PER_WAY 0x00400000
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#define CONFIG1_ICACHE_256_SETS_PER_WAY 0x00800000
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/* Instruction cache line size codes */
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#define CONFIG1_ICACHE_NOT_PRESET 0x00000000
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#define CONFIG1_ICACHE_LINE_SIZE_16_BYTES 0x00180000
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/* Instruction cache associativity codes */
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#define CONFIG1_ICACHE_DIRECT_MAPPED 0x00000000
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#define CONFIG1_ICACHE_2_WAY 0x00010000
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#define CONFIG1_ICACHE_3_WAY 0x00020000
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#define CONFIG1_ICACHE_4_WAY 0x00030000
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/* Data cache sets-per-way codes */
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#define CONFIG1_DCACHE_64_SETS_PER_WAY 0x00000000
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#define CONFIG1_DCACHE_128_SETS_PER_WAY 0x00002000
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#define CONFIG1_DCACHE_256_SETS_PER_WAY 0x00004000
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/* Data cache line size codes */
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#define CONFIG1_DCACHE_NOT_PRESET 0x00000000
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#define CONFIG1_DCACHE_LINE_SIZE_16_BYTES 0x00000C00
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/* Data cache associativity codes */
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#define CONFIG1_DCACHE_DIRECT_MAPPED 0x00000000
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#define CONFIG1_DCACHE_2_WAY 0x00000080
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#define CONFIG1_DCACHE_3_WAY 0x00000100
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#define CONFIG1_DCACHE_4_WAY 0x00000180
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#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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//--------------------------------------------------------------------------
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#endif // CYGONCE_HAL_VAR_ARCH_H
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// End of var_arch.h
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