OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [mips/] [mips64/] [current/] [src/] [var_misc.c] - Blame information for rev 868

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
//==========================================================================
2
//
3
//      var_misc.c
4
//
5
//      HAL implementation miscellaneous functions
6
//
7
//==========================================================================
8
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
9
// -------------------------------------------                              
10
// This file is part of eCos, the Embedded Configurable Operating System.   
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under    
14
// the terms of the GNU General Public License as published by the Free     
15
// Software Foundation; either version 2 or (at your option) any later      
16
// version.                                                                 
17
//
18
// eCos is distributed in the hope that it will be useful, but WITHOUT      
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
21
// for more details.                                                        
22
//
23
// You should have received a copy of the GNU General Public License        
24
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
25
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
26
//
27
// As a special exception, if other files instantiate templates or use      
28
// macros or inline functions from this file, or you compile this file      
29
// and link it with other works to produce a work based on this file,       
30
// this file does not by itself cause the resulting work to be covered by   
31
// the GNU General Public License. However the source code for this file    
32
// must still be made available in accordance with section (3) of the GNU   
33
// General Public License v2.                                               
34
//
35
// This exception does not invalidate any other reasons why a work based    
36
// on this file might be covered by the GNU General Public License.         
37
// -------------------------------------------                              
38
// ####ECOSGPLCOPYRIGHTEND####                                              
39
//==========================================================================
40
//#####DESCRIPTIONBEGIN####
41
//
42
// Author(s):    nickg
43
// Contributors: nickg, jlarmour, dmoseley
44
// Date:         2000-07-14
45
// Purpose:      HAL miscellaneous functions
46
// Description:  This file contains miscellaneous functions provided by the
47
//               HAL.
48
//
49
//####DESCRIPTIONEND####
50
//
51
//========================================================================*/
52
 
53
#include <pkgconf/hal.h>
54
 
55
#include <cyg/infra/cyg_type.h>         // Base types
56
#include <cyg/infra/cyg_trac.h>         // tracing macros
57
#include <cyg/infra/cyg_ass.h>          // assertion macros
58
 
59
#include <cyg/hal/hal_intr.h>
60
 
61
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
62
#include <cyg/hal/hal_arch.h>
63
#include <cyg/hal/var_arch.h>
64
#include <cyg/hal/plf_io.h>
65
#include <cyg/hal/hal_cache.h>
66
 
67
/*------------------------------------------------------------------------*/
68
// Array which stores the configured priority levels for the configured
69
// interrupts.
70
 
71
volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
72
 
73
/*------------------------------------------------------------------------*/
74
 
75
void hal_variant_init(void)
76
{
77
}
78
 
79
/*
80
 * Uncomment the following to allow for dynamic cache sizing.
81
 * Currently we are going to assume the exact part specified in the ecosconfig stuff.
82
 * Perhaps in the near future this can all be done dynamically.
83
 */
84
/* define DYNAMIC_CACHE_SIZING */
85
 
86
#if 0
87
#ifndef DYNAMIC_CACHE_SIZING
88
#warning "                                                                           \n\
89
STILL NEED TO IMPLEMENT DYNAMIC_CACHE_SIZING.                                        \n\
90
ALSO, the HAL_PLATFORM_CPU/etc defines need to be dynamic.                           \n\
91
ALSO, need to do big endian stuff as well.                                           \n\
92
Determine if network debug is necessary.                                             \n\
93
Remove MIPS memc_init code"
94
#endif
95
#endif
96
 
97
/*------------------------------------------------------------------------*/
98
// Initialize the caches
99
 
100
int hal_init_icache(unsigned long config1_val)
101
{
102
#ifdef DYNAMIC_CACHE_SIZING
103
  int icache_linesize, icache_assoc, icache_sets, icache_lines, icache_size;
104
  unsigned long cache_addr;
105
 
106
  switch (config1_val & CONFIG1_IL)
107
    {
108
    case CONFIG1_ICACHE_LINE_SIZE_32_BYTES: icache_linesize = 32;      break;
109
    case CONFIG1_ICACHE_NOT_PRESET:         return -1;                 break;
110
    default:      /* Error */               return -1;                 break;
111
    }
112
 
113
  switch (config1_val & CONFIG1_IA)
114
    {
115
    case CONFIG1_ICACHE_DIRECT_MAPPED:      icache_assoc = 1;          break;
116
    case CONFIG1_ICACHE_2_WAY:              icache_assoc = 2;          break;
117
    case CONFIG1_ICACHE_3_WAY:              icache_assoc = 3;          break;
118
    case CONFIG1_ICACHE_4_WAY:              icache_assoc = 4;          break;
119
    default:      /* Error */               return -1;                 break;
120
    }
121
 
122
  switch (config1_val & CONFIG1_IS)
123
    {
124
    case CONFIG1_ICACHE_64_SETS_PER_WAY:    icache_sets = 64;          break;
125
    case CONFIG1_ICACHE_128_SETS_PER_WAY:   icache_sets = 128;         break;
126
    case CONFIG1_ICACHE_256_SETS_PER_WAY:   icache_sets = 256;         break;
127
    default:      /* Error */               return -1;                 break;
128
    }
129
 
130
  icache_lines = icache_sets * icache_assoc;
131
  icache_size = icache_lines * icache_linesize;
132
#endif /* DYNAMIC_CACHE_SIZING */
133
 
134
  /*
135
   * Reset does not invalidate the cache so let's do so now.
136
   */
137
  HAL_ICACHE_INVALIDATE_ALL();
138
 
139
#ifdef DYNAMIC_CACHE_SIZING
140
  return icache_size;
141
#else
142
  return HAL_ICACHE_SIZE;
143
#endif
144
}
145
 
146
int hal_init_dcache(unsigned long config1_val)
147
{
148
#ifdef DYNAMIC_CACHE_SIZING
149
  int dcache_linesize, dcache_assoc, dcache_sets, dcache_lines, dcache_size;
150
 
151
  switch (config1_val & CONFIG1_DL)
152
    {
153
    case CONFIG1_DCACHE_LINE_SIZE_32_BYTES: dcache_linesize = 32;      break;
154
    case CONFIG1_DCACHE_NOT_PRESET:         return -1;                 break;
155
    default:      /* Error */               return -1;                 break;
156
    }
157
 
158
  switch (config1_val & CONFIG1_DA)
159
    {
160
    case CONFIG1_DCACHE_DIRECT_MAPPED:      dcache_assoc = 1;          break;
161
    case CONFIG1_DCACHE_2_WAY:              dcache_assoc = 2;          break;
162
    case CONFIG1_DCACHE_3_WAY:              dcache_assoc = 3;          break;
163
    case CONFIG1_DCACHE_4_WAY:              dcache_assoc = 4;          break;
164
    default:      /* Error */               return -1;                 break;
165
    }
166
 
167
  switch (config1_val & CONFIG1_DS)
168
    {
169
    case CONFIG1_DCACHE_64_SETS_PER_WAY:    dcache_sets = 64;          break;
170
    case CONFIG1_DCACHE_128_SETS_PER_WAY:   dcache_sets = 128;         break;
171
    case CONFIG1_DCACHE_256_SETS_PER_WAY:   dcache_sets = 256;         break;
172
    default:      /* Error */               return -1;                 break;
173
    }
174
 
175
  dcache_lines = dcache_sets * dcache_assoc;
176
  dcache_size = dcache_lines * dcache_linesize;
177
#endif /* DYNAMIC_CACHE_SIZING */
178
 
179
  /*
180
   * Reset does not invalidate the cache so let's do so now.
181
   */
182
  HAL_DCACHE_INVALIDATE_ALL();
183
 
184
#ifdef DYNAMIC_CACHE_SIZING
185
  return dcache_size;
186
#else
187
  return HAL_DCACHE_SIZE;
188
#endif
189
}
190
 
191
void hal_c_cache_init(unsigned long config1_val)
192
{
193
  volatile unsigned val;
194
 
195
  if (hal_init_icache(config1_val) == -1)
196
    {
197
        /* Error */
198
        ;
199
    }
200
 
201
  if (hal_init_dcache(config1_val) == -1)
202
    {
203
        /* Error */
204
        ;
205
    }
206
 
207
  // enable cached KSEG0
208
  asm volatile("mfc0 %0,$16;" : "=r"(val));
209
  val &= ~3;
210
  asm volatile("mtc0 %0,$16;" : : "r"(val));
211
}
212
 
213
void hal_icache_sync(void)
214
{
215
    HAL_ICACHE_INVALIDATE_ALL();
216
}
217
 
218
void hal_dcache_sync(void)
219
{
220
    HAL_DCACHE_INVALIDATE_ALL();
221
}
222
 
223
/*------------------------------------------------------------------------*/
224
/* End of var_misc.c                                                      */

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.