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skrzyp |
#ifndef CYGONCE_HAL_IMP_INTR_H
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#define CYGONCE_HAL_IMP_INTR_H
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//==========================================================================
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//
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// imp_intr.h
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//
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// TX39 Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jskov,
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// gthomas, jlarmour
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// Date: 1999-02-16
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// Purpose: TX39 Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for variants of the TX39 MIPS
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// architecture.
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//
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// Usage:
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// #include <cyg/hal/imp_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/plf_intr.h>
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//--------------------------------------------------------------------------
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// Interrupt vectors.
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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// These are decoded via the IP bits of the cause
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// register when an external interrupt is delivered.
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#define CYGNUM_HAL_INTERRUPT_1 0
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#define CYGNUM_HAL_INTERRUPT_2 1
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#define CYGNUM_HAL_INTERRUPT_3 2
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#define CYGNUM_HAL_INTERRUPT_4 3
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#define CYGNUM_HAL_INTERRUPT_5 4
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#define CYGNUM_HAL_INTERRUPT_6 5
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#define CYGNUM_HAL_INTERRUPT_7 6
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#define CYGNUM_HAL_INTERRUPT_DMAC1_CH3 7
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#define CYGNUM_HAL_INTERRUPT_DMAC1_CH2 8
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#define CYGNUM_HAL_INTERRUPT_DMAC0_CH1 9
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#define CYGNUM_HAL_INTERRUPT_DMAC0_CH0 10
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#define CYGNUM_HAL_INTERRUPT_SIO_0 11
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#define CYGNUM_HAL_INTERRUPT_SIO_1 12
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#define CYGNUM_HAL_INTERRUPT_TMR_0 13
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#define CYGNUM_HAL_INTERRUPT_TMR_1 14
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#define CYGNUM_HAL_INTERRUPT_TMR_2 15
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#define CYGNUM_HAL_INTERRUPT_0 16
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 16
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#define CYGNUM_HAL_ISR_COUNT 17
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// The vector used by the Real time clock
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMR_0
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Interrupt controller access.
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#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#if defined(CYGPKG_HAL_MIPS_TX3904)
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#define CYG_HAL_MIPS_TX3904_ILR0 0xFFFFC010
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#define CYG_HAL_MIPS_TX3904_CConR 0xFFFFE000
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// Array which stores the configured priority levels for the configured
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// interrupts.
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externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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{ \
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HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
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CYG_WORD32 _ilr_; \
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_reg_ += (_vector_)&0xC; \
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HAL_READ_UINT32( _reg_, _ilr_ ); \
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_ilr_ &= ~(7 << (((_vector_)&0x3)<<3)); \
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HAL_WRITE_UINT32( _reg_, _ilr_ ); \
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}
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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{ \
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HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
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CYG_WORD32 _ilr_; \
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_reg_ += (_vector_)&0xC; \
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HAL_READ_UINT32( _reg_, _ilr_ ); \
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_ilr_ |= hal_interrupt_level[_vector_] << (((_vector_)&0x3)<<3); \
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HAL_WRITE_UINT32( _reg_, _ilr_ ); \
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}
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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{ \
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if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \
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_vector_ == CYGNUM_HAL_INTERRUPT_0 ) \
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{ \
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cyg_uint32 _v_ = _vector_ + 1; \
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cyg_uint8 _reg_; \
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\
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/* adjust vector to bit offset in CConR */ \
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if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \
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\
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/* get CConR */ \
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HAL_READ_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_ ); \
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\
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/* clear old value and set new */ \
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_reg_ &= ~(7 << 5); \
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_reg_ |= _v_ << 5; \
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HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_); \
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} \
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}
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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{ \
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if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \
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_vector_ == CYGNUM_HAL_INTERRUPT_0 ) \
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{ \
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cyg_uint32 _v_ = _vector_ + 1; \
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cyg_uint32 _val_ = 0; \
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cyg_uint16 _reg_; \
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\
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/* adjust vector to bit offset in CConR */ \
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if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \
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_v_ <<= 1; \
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\
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/* set bits according to requirements */ \
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if( _up_ ) _val_ |= 1; \
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if( !(_level_) ) _val_ |= 2; \
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\
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/* get CConR */ \
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HAL_READ_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \
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\
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/* clear old value and set new */ \
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_reg_ &= ~(3 << _v_); \
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_reg_ |= _val_ << _v_; \
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HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \
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} \
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}
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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{ \
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HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
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CYG_WORD32 _ilr_; \
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_reg_ += (_vector_)&0xC; \
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HAL_READ_UINT32( _reg_, _ilr_ ); \
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_ilr_ |= (_level_) << (((_vector_)&0x3)<<3); \
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HAL_WRITE_UINT32( _reg_, _ilr_ ); \
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hal_interrupt_level[_vector_] = _level_; \
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}
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#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#else
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#error Unspecified TX39 variant
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#endif
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#endif
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//--------------------------------------------------------------------------
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// Clock control
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#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED
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#if defined(CYGPKG_HAL_MIPS_TX3904)
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#define CYG_HAL_MIPS_TX3904_TIMER_BASE 0xFFFFF000
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#define CYG_HAL_MIPS_TX3904_TIMER_CR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x00)
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#define CYG_HAL_MIPS_TX3904_TIMER_SR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x04)
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#define CYG_HAL_MIPS_TX3904_TIMER_CPR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x08)
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#define CYG_HAL_MIPS_TX3904_TIMER_IMR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x10)
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#define CYG_HAL_MIPS_TX3904_TIMER_DR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x20)
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#define CYG_HAL_MIPS_TX3904_TIMER_RR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0xF0)
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#define HAL_CLOCK_INITIALIZE( _period_ ) \
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{ \
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HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_DR, 0x00000003 ); \
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HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CPR, _period_ ); \
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HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \
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HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_IMR, 0x00008001 ); \
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HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CR, 0x000000C0 ); \
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}
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#define HAL_CLOCK_RESET( _vector_, _period_ ) \
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{ \
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HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \
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}
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#if defined(CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC) && \
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!defined(CYGPKG_HAL_MIPS_SIM)
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// We need to sync and check the coprocessor 0 condition - this
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// indicates whether data is present in the write buffer. We need to
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// wait until the data to be written is flushed out. This works
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// around a tx39 bug. gcc will insert a NOP after the asm insns.
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# define HAL_CLOCK_READ( _pvalue_ ) \
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CYG_MACRO_START \
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asm volatile ( \
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"sync; nop; 1: ; bc0f 1b" \
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: \
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: \
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: "$0" \
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); \
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HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \
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CYG_MACRO_END
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#else
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# define HAL_CLOCK_READ( _pvalue_ ) \
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CYG_MACRO_START \
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HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \
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CYG_MACRO_END
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#endif
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#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
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!defined(HAL_CLOCK_LATENCY)
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#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
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#endif
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#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED
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#else
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#error Unspecified TX39 variant
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#endif
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#endif
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//--------------------------------------------------------------------------
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// Timeout exception support. This is TX39 specific.
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#if defined(CYGPKG_HAL_MIPS_TX3904)
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#define HAL_TX39_DEBUG_TOE_ENABLE() \
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{ \
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HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \
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CYG_WORD32 _cconr_; \
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HAL_READ_UINT32( _reg_, _cconr_); \
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_cconr_ |= 0x04000000; \
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HAL_WRITE_UINT32( _reg_, _cconr_); \
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}
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#define HAL_TX39_DEBUG_TOE_DISABLE() \
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{ \
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HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \
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CYG_WORD32 _cconr_; \
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HAL_READ_UINT32( _reg_, _cconr_); \
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_cconr_ &= 0xFBFFFFFF; \
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HAL_WRITE_UINT32( _reg_, _cconr_); \
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}
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#else
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#define HAL_TX39_DEBUG_TOE_ENABLE()
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#define HAL_TX39_DEBUG_TOE_DISABLE()
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#endif
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_IMP_INTR_H
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// End of imp_intr.h
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