OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [mips/] [upd985xx/] [current/] [src/] [hal_diag.c] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
/*=============================================================================
2
//
3
//      hal_diag.c
4
//
5
//      HAL diagnostic output code
6
//
7
//=============================================================================
8
// ####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later
16
// version.
17
//
18
// eCos is distributed in the hope that it will be useful, but WITHOUT
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
// for more details.
22
//
23
// You should have received a copy of the GNU General Public License
24
// along with eCos; if not, write to the Free Software Foundation, Inc.,
25
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26
//
27
// As a special exception, if other files instantiate templates or use
28
// macros or inline functions from this file, or you compile this file
29
// and link it with other works to produce a work based on this file,
30
// this file does not by itself cause the resulting work to be covered by
31
// the GNU General Public License. However the source code for this file
32
// must still be made available in accordance with section (3) of the GNU
33
// General Public License v2.
34
//
35
// This exception does not invalidate any other reasons why a work based
36
// on this file might be covered by the GNU General Public License.
37
// -------------------------------------------
38
// ####ECOSGPLCOPYRIGHTEND####
39
//=============================================================================
40
//#####DESCRIPTIONBEGIN####
41
//
42
// Author(s):   hmt, nickg
43
// Contributors:        nickg
44
// Date:        2001-05-25
45
// Purpose:     HAL diagnostic output
46
// Description: Implementations of HAL diagnostic output support.
47
//
48
//####DESCRIPTIONEND####
49
//
50
//===========================================================================*/
51
 
52
#include <pkgconf/hal.h>
53
 
54
#include <cyg/infra/cyg_type.h>         // base types
55
#include <cyg/infra/cyg_trac.h>         // tracing macros
56
#include <cyg/infra/cyg_ass.h>          // assertion macros
57
 
58
#include <cyg/hal/hal_arch.h>           // which includes var_arch => UART.
59
#include <cyg/hal/hal_diag.h>
60
#include <cyg/hal/hal_intr.h>
61
#include <cyg/hal/hal_io.h>
62
#include <cyg/hal/drv_api.h>
63
#include <cyg/hal/hal_if.h>             // interface API
64
#include <cyg/hal/hal_misc.h>           // Helper functions
65
 
66
/*---------------------------------------------------------------------------*/
67
//#define CYG_KERNEL_DIAG_GDB
68
 
69
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
70
 
71
#define CYG_KERNEL_DIAG_GDB
72
 
73
#endif
74
 
75
/*---------------------------------------------------------------------------*/
76
static inline
77
void hal_uart_setbaud( int baud )
78
{
79
    // now set the baud rate
80
    *UARTLCR |= UARTLCR_DLAB;
81
    *UARTDLM = UARTDLM_VAL( baud );
82
    *UARTDLL = UARTDLL_VAL( baud );
83
    *UARTLCR &=~UARTLCR_DLAB;
84
}
85
 
86
void hal_uart_init(void)
87
{
88
    // Ensure that we use the internal clock
89
    *S_GMR &=~S_GMR_UCSEL;
90
 
91
    *UARTFCR = UARTFCR_16550_MODE;
92
    *UARTLCR = UARTLCR_8N1;
93
    *UARTIER = UARTIER_ERBFI;           // rx interrupts enabled for CTRL-C
94
 
95
    hal_uart_setbaud( CYGHWR_HAL_MIPS_UPD985XX_DIAG_BAUD );
96
}
97
 
98
void hal_uart_write_char(char c)
99
{
100
    while ( 0 == (UARTLSR_THRE & *UARTLSR) )
101
        /* do nothing */ ;
102
 
103
    *UARTTHR = (unsigned int)c;
104
 
105
    // Ensure that this write does not provoke a spurious interrupt.
106
    HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
107
}
108
 
109
void hal_uart_read_char(char *c)
110
{
111
    while ( 0 == (UARTLSR_DR & *UARTLSR) )
112
        /* do nothing */ ;
113
 
114
    *c = (char)*UARTRBR;
115
 
116
    // Ensure that this read does not provoke a spurious interrupt.
117
    HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
118
}
119
 
120
int hal_uart_read_char_nonblock(char *c)
121
{
122
    if ( 0 == (UARTLSR_DR & *UARTLSR) )
123
        return 0;
124
 
125
    *c = (char)*UARTRBR;
126
 
127
    // Ensure that this read does not provoke a spurious interrupt.
128
    HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
129
 
130
    return 1;
131
}
132
 
133
 
134
/*---------------------------------------------------------------------------*/
135
 
136
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
137
 
138
#include <cyg/hal/hal_if.h>
139
 
140
// This is lame, duplicating all these wrappers with slightly different details.
141
// All this should be in hal_if.c
142
static void
143
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
144
{
145
    CYGARC_HAL_SAVE_GP();
146
    hal_uart_write_char( (char)c );
147
    CYGARC_HAL_RESTORE_GP();
148
}
149
 
150
static cyg_uint8
151
cyg_hal_plf_serial_getc(void* __ch_data)
152
{
153
    cyg_uint8 result;
154
    CYGARC_HAL_SAVE_GP();
155
    hal_uart_read_char( (char *)&result );
156
    CYGARC_HAL_RESTORE_GP();
157
    return result;
158
}
159
 
160
static int
161
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8 *pc)
162
{
163
    return hal_uart_read_char_nonblock( (char *)pc );
164
}
165
 
166
static void
167
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
168
                         cyg_uint32 __len)
169
{
170
    CYGARC_HAL_SAVE_GP();
171
 
172
    while(__len-- > 0)
173
        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
174
 
175
    CYGARC_HAL_RESTORE_GP();
176
}
177
 
178
static void
179
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
180
{
181
    CYGARC_HAL_SAVE_GP();
182
 
183
    while(__len-- > 0)
184
        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
185
 
186
    CYGARC_HAL_RESTORE_GP();
187
}
188
 
189
static int chan__msec_timeout = 0;
190
static int chan__irq_state = 0;
191
static int chan__baud_rate = CYGHWR_HAL_MIPS_UPD985XX_DIAG_BAUD;
192
 
193
cyg_bool
194
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
195
{
196
    int delay_count;
197
    cyg_bool res;
198
    CYGARC_HAL_SAVE_GP();
199
 
200
    delay_count = chan__msec_timeout * 10; // delay in .1 ms steps
201
 
202
    for(;;) {
203
        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
204
        if (res || 0 >= delay_count--)
205
            break;
206
 
207
        CYGACC_CALL_IF_DELAY_US(100);
208
    }
209
 
210
    CYGARC_HAL_RESTORE_GP();
211
    return res;
212
}
213
 
214
static int
215
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
216
{
217
    int ret = -1;
218
    va_list ap;
219
 
220
    CYGARC_HAL_SAVE_GP();
221
    va_start(ap, __func);
222
 
223
    switch (__func) {
224
    case __COMMCTL_GETBAUD:
225
        ret = chan__baud_rate;
226
        break;
227
    case __COMMCTL_SETBAUD:
228
        ret = 0;
229
        chan__baud_rate = va_arg(ap, cyg_int32);
230
        hal_uart_setbaud( chan__baud_rate );
231
        break;
232
    case __COMMCTL_IRQ_ENABLE:
233
        ret = chan__irq_state;
234
        chan__irq_state = 1;
235
        HAL_INTERRUPT_UNMASK( CYGHWR_HAL_GDB_PORT_VECTOR );
236
        break;
237
    case __COMMCTL_IRQ_DISABLE:
238
        ret = chan__irq_state;
239
        chan__irq_state = 0;
240
        HAL_INTERRUPT_MASK( CYGHWR_HAL_GDB_PORT_VECTOR );
241
        break;
242
    case __COMMCTL_DBG_ISR_VECTOR:
243
        ret = CYGHWR_HAL_GDB_PORT_VECTOR;
244
        break;
245
    case __COMMCTL_SET_TIMEOUT:
246
        ret = chan__msec_timeout;
247
        chan__msec_timeout = va_arg(ap, cyg_uint32);
248
        break;
249
    default:
250
        break;
251
    }
252
    va_end(ap);
253
    CYGARC_HAL_RESTORE_GP();
254
    return ret;
255
}
256
 
257
static int
258
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
259
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
260
{
261
    int ret = 0;
262
    char c;
263
 
264
    *__ctrlc = 0;
265
 
266
    if ( hal_uart_read_char_nonblock( &c ) ) {
267
        if ( cyg_hal_is_break( &c , 1 ) )
268
            *__ctrlc = 1;
269
        ret = CYG_ISR_HANDLED;
270
    }
271
 
272
    return ret;
273
}
274
 
275
static void
276
cyg_hal_plf_serial_init(void)
277
{
278
    hal_virtual_comm_table_t* comm;
279
    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
280
 
281
    // Init channels
282
    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
283
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
284
    CYGACC_COMM_IF_CH_DATA_SET(*comm, comm);
285
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
286
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
287
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
288
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
289
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
290
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
291
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
292
 
293
    // Restore original console
294
    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
295
}
296
 
297
void
298
cyg_hal_plf_comms_init(void)
299
{
300
    static int initialized = 0;
301
 
302
    if (initialized)
303
        return;
304
 
305
    initialized = 1;
306
 
307
    hal_uart_init();
308
    cyg_hal_plf_serial_init();
309
}
310
 
311
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
312
 
313
// ------------------------------------------------------------------------
314
 
315
void hal_diag_init(void)
316
{
317
    hal_uart_init();
318
}
319
 
320
void hal_diag_read_char(char *c)
321
{
322
    hal_uart_read_char(c);
323
}
324
 
325
extern cyg_bool cyg_hal_is_break(char *buf, int size);
326
extern void cyg_hal_user_break(CYG_ADDRWORD *regs);
327
 
328
void hal_diag_write_char(char c)
329
{
330
#ifdef CYG_KERNEL_DIAG_GDB    
331
    static char line[100];
332
    static int pos = 0;
333
 
334
    // No need to send CRs
335
    if( c == '\r' ) return;
336
 
337
    line[pos++] = c;
338
 
339
    if( c == '\n' || pos == sizeof(line) )
340
    {
341
 
342
        // Disable interrupts. This prevents GDB trying to interrupt us
343
        // while we are in the middle of sending a packet. The serial
344
        // receive interrupt will be seen when we re-enable interrupts
345
        // later.
346
        CYG_INTERRUPT_STATE oldstate;
347
        HAL_DISABLE_INTERRUPTS(oldstate);
348
 
349
        while(1)
350
        {
351
            static char hex[] = "0123456789ABCDEF";
352
            cyg_uint8 csum = 0;
353
            int i;
354
            char c1;
355
 
356
            hal_uart_write_char('$');
357
            hal_uart_write_char('O');
358
            csum += 'O';
359
            for( i = 0; i < pos; i++ )
360
            {
361
                char ch = line[i];
362
                char h = hex[(ch>>4)&0xF];
363
                char l = hex[ch&0xF];
364
                hal_uart_write_char(h);
365
                hal_uart_write_char(l);
366
                csum += h;
367
                csum += l;
368
            }
369
            hal_uart_write_char('#');
370
            hal_uart_write_char(hex[(csum>>4)&0xF]);
371
            hal_uart_write_char(hex[csum&0xF]);
372
 
373
            hal_uart_read_char( &c1 );
374
 
375
            if( c1 == '+' ) break;
376
 
377
            if( cyg_hal_is_break( &c1 , 1 ) )
378
                cyg_hal_user_break( NULL );
379
 
380
        }
381
 
382
        pos = 0;
383
 
384
        // Disabling the interrupts for an extended period of time
385
        // can provoke a spurious interrupt.
386
 
387
        // Ensure that this write does not provoke a spurious interrupt.
388
        HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
389
 
390
        // And re-enable interrupts
391
        HAL_RESTORE_INTERRUPTS( oldstate );
392
 
393
    }
394
#else
395
    hal_uart_write_char(c);
396
#endif    
397
}
398
 
399
/*---------------------------------------------------------------------------*/
400
/* End of hal_diag.c */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.