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skrzyp |
#ifndef CYGONCE_HAL_PLF_INTR_H
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#define CYGONCE_HAL_PLF_INTR_H
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//==========================================================================
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//
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// plf_intr.h
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//
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// VRC437X Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jskov,
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// gthomas, jlarmour
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// Date: 1999-02-16
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for the VRC437X board.
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//
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// Usage:
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// #include <cyg/hal/plf_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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//--------------------------------------------------------------------------
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// Interrupt controller stuff.
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// The first 6 correspond to the interrupt lines in the status/cause regs
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#define CYGNUM_HAL_INTERRUPT_VRC437X 0
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#define CYGNUM_HAL_INTERRUPT_IPL0 1
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#define CYGNUM_HAL_INTERRUPT_IPL1 2
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#define CYGNUM_HAL_INTERRUPT_IPL2 3
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#define CYGNUM_HAL_INTERRUPT_POWER 4
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#define CYGNUM_HAL_INTERRUPT_COMPARE 5
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// The next 32 correspond to the interrupt lines in the 4372 interrupt
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// controller. These are decoded from the controller when an interrupt
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// on any of the IPL[0:2] lines in signalled.
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#define CYGNUM_HAL_INTERRUPT_REALTIME_A 6
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#define CYGNUM_HAL_INTERRUPT_REALTIME_B 7
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#define CYGNUM_HAL_INTERRUPT_DUART 8
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#define CYGNUM_HAL_INTERRUPT_TIMER 9
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#define CYGNUM_HAL_INTERRUPT_PARALLEL 10
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#define CYGNUM_HAL_INTERRUPT_PCI_INTA 11
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#define CYGNUM_HAL_INTERRUPT_PCI_INTB 12
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#define CYGNUM_HAL_INTERRUPT_PCI_INTC 13
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#define CYGNUM_HAL_INTERRUPT_PCI_INTD 14
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#define CYGNUM_HAL_INTERRUPT_INT_9 15
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#define CYGNUM_HAL_INTERRUPT_INT_10 16
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#define CYGNUM_HAL_INTERRUPT_INT_11 17
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#define CYGNUM_HAL_INTERRUPT_INT_12 18
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#define CYGNUM_HAL_INTERRUPT_INT_13 19
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#define CYGNUM_HAL_INTERRUPT_DMA_0 20
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#define CYGNUM_HAL_INTERRUPT_DMA_1 21
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#define CYGNUM_HAL_INTERRUPT_DMA_2 22
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#define CYGNUM_HAL_INTERRUPT_DMA_3 23
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#define CYGNUM_HAL_INTERRUPT_TICK_0 24
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#define CYGNUM_HAL_INTERRUPT_TICK_1 25
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#define CYGNUM_HAL_INTERRUPT_UNUSED_20 26
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#define CYGNUM_HAL_INTERRUPT_UNUSED_21 27
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#define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT 28
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#define CYGNUM_HAL_INTERRUPT_PCI_PERR 29
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#define CYGNUM_HAL_INTERRUPT_PCI_SERR 30
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#define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA 31
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#define CYGNUM_HAL_INTERRUPT_PCI_REC_TA 32
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#define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA 33
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#define CYGNUM_HAL_INTERRUPT_PCI_ADD 34
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#define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR 35
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#define CYGNUM_HAL_INTERRUPT_UNUSED_30 36
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#define CYGNUM_HAL_INTERRUPT_UNUSED_31 37
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// Min/Max ISR numbers and how many there are
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 37
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#define CYGNUM_HAL_ISR_COUNT 38
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// The vector used by the Real time clock. The default here is to use
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// interrupt 5, which is connected to the counter/comparator registers
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// in many MIPS variants.
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#ifndef CYGNUM_HAL_INTERRUPT_RTC
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
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#endif
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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//--------------------------------------------------------------------------
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// Vector translation.
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// For chained interrupts we only have a single vector though which all
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// are passed. For unchained interrupts we have a vector per interrupt.
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// Vector 0 has a special catcher ISR for spurious interrupts from the VRC437X
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// and vectors 1-3 are springboards, so we chain through vector 4.
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#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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{ \
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if ((_vector_)==0) \
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(_index_) = 0; \
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else \
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(_index_) = 4; \
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}
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#endif
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//--------------------------------------------------------------------------
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// controller access code
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#define CYGHWR_HAL_MIPS_VRC4372_BASE 0xbc000000
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_POL (CYGHWR_HAL_MIPS_VRC4372_BASE+0x200)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4372_BASE+0x204)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_PINS (CYGHWR_HAL_MIPS_VRC4372_BASE+0x208)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x20c)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x210)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x214)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x218)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x21c)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x220)
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#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF 8
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// Array which stores the configured priority levels for the configured
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// interrupts.
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externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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CYG_MACRO_START \
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if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else \
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{ \
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CYG_WORD32 _mask_; \
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CYG_BYTE _shift_; \
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HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \
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cyg_hal_interrupt_level[_vector_] * \
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CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
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HAL_READ_UINT32( _maskreg_, _mask_ ); \
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_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
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_mask_ &= ~(1<<_shift_); \
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HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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CYG_MACRO_START \
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if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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asm volatile ( \
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"mfc0 $3,$12\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"or $3,$3,$2\n" \
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"mtc0 $3,$12\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_vector_) \
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: "$2", "$3" \
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); \
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} \
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else \
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{ \
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CYG_WORD32 _mask_; \
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CYG_BYTE _shift_; \
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HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \
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cyg_hal_interrupt_level[_vector_] * \
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CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
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HAL_READ_UINT32( _maskreg_, _mask_ ); \
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_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
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_mask_ |= 1<<_shift_; \
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HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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CYG_WORD32 _srvector_ = _vector_; \
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if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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CYG_WORD32 _stat_; \
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CYG_BYTE _shift_; \
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HAL_IO_REGISTER _statreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 +\
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cyg_hal_interrupt_level[_vector_] * \
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CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
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HAL_READ_UINT32( _statreg_, _stat_ ); \
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_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
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_stat_ &= ~(1<<_shift_); \
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HAL_WRITE_UINT32( _statreg_, _stat_ ); \
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_srvector_ = cyg_hal_interrupt_level[_vector_] + \
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CYGNUM_HAL_INTERRUPT_IPL0; \
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} \
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asm volatile ( \
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"mfc0 $3,$13\n" \
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"la $2,0x00000400\n" \
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"sllv $2,$2,%0\n" \
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"nor $2,$2,$0\n" \
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"and $3,$3,$2\n" \
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"mtc0 $3,$13\n" \
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"nop; nop; nop\n" \
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: \
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: "r"(_srvector_) \
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: "$2", "$3" \
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); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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CYG_MACRO_START \
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if( (_vector_ >= CYGNUM_HAL_INTERRUPT_REALTIME_A) && \
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(_vector_ <= CYGNUM_HAL_INTERRUPT_INT_13)) \
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{ \
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CYG_WORD32 mask = 1<<(_vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A); \
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CYG_WORD32 pol; \
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CYG_WORD32 trig; \
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HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \
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HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \
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if( _level_ ) \
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{ \
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pol &= ~mask; \
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if( _up_ ) trig |= mask; \
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else trig &= ~mask; \
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} \
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else \
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{ \
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pol |= mask; \
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if( !(_up_) ) trig |= mask; \
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else trig &= ~mask; \
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} \
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HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \
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HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \
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} \
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CYG_MACRO_END
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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CYG_MACRO_START \
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if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
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{ \
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cyg_uint32 _ilevel_ = _level_; \
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while( _ilevel_ > 2 ) _ilevel_ -= 2; \
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cyg_hal_interrupt_level[_vector_] = _ilevel_; \
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} \
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CYG_MACRO_END
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#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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//--------------------------------------------------------------------------
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| 297 |
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// Control-C support.
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| 299 |
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#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
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# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART
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externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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#define HAL_CTRLC_ISR hal_ctrlc_isr
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#endif
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//----------------------------------------------------------------------------
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// Reset.
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#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
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#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PLF_INTR_H
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// End of plf_intr.h
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