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skrzyp |
#ifndef CYGONCE_PLF_IO_H
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#define CYGONCE_PLF_IO_H
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//=============================================================================
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//
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// plf_io.h
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//
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// Platform specific IO support
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt, jskov, nickg
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// Contributors: hmt, jskov, nickg
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// Date: 1999-08-09
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// Purpose: VRC4373 PCI IO support macros
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// Description:
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// Usage: #include <cyg/hal/plf_io.h>
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//
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// Note: Based on information in
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// "VRC4373 System Controller Data Sheet"
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/hal/hal_intr.h> // Interrupt vectors
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//-----------------------------------------------------------------------------
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// PCI access registers
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#define HAL_PCI_ADDRESS_WINDOW_1 0xAF000014
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#define HAL_PCI_ADDRESS_WINDOW_2 0xAF000018
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#define HAL_PCI_IO_WINDOW 0xAF000024
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#define HAL_PCI_CONFIG_SPACE_DATA 0xAF000028
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#define HAL_PCI_CONFIG_SPACE_ADDR 0xAF00002C
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#define HAL_PCI_ENABLE_REG 0xAF000074
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//-----------------------------------------------------------------------------
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// Mappings for PCI memory and IO spaces
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// This is where the PCI spaces are mapped in the CPU's (virtual)
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// address space.
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#define HAL_PCI_PHYSICAL_IO_BASE 0xA0000000
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#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xBC100000
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//-----------------------------------------------------------------------------
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// Initialize the PCI bus.
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externC void cyg_hal_plf_pci_init(void);
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#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
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// Compute address necessary to access PCI config space for the given
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// bus and device.
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#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
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({ \
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cyg_uint32 __addr; \
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cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
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if (0 == __bus) { \
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__addr = (1 << (__dev+16)); \
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} else { \
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/* We need better info about how to form type 1 addresses */ \
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__addr = 0x800000000 | (__bus << 16) | (__dev << 11); \
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} \
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__addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \
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__addr |= (__offset)&~3; \
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__addr; \
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})
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// The following function allows us to read locations in the PCI config
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// space that we are not sure contains a valid device. Support in platform.S
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// catches and fixes any bus errors caused.
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externC CYG_WORD32 hal_pci_config_read(CYG_ADDRESS addr);
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#define HAL_PCI_CONFIG_READ( __addr, __val ) __val = hal_pci_config_read(__addr)
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// Read a value from the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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// We can only make 32 bit accesses to the PCI config data register, hence
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// all the shifing and masking in these macros.
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// Note that we may only use HAL_PCI_CONFIG_READ() here.
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#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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CYG_MACRO_START \
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CYG_WORD32 _val_; \
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CYG_WORD32 _offset_ = __offset & 3; \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
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HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
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__val = (CYG_BYTE)((_val_>>(_offset_*8))&0xFF); \
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CYG_MACRO_END
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#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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CYG_MACRO_START \
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CYG_WORD32 _val_; \
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CYG_WORD32 _offset_ = __offset & 2; \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
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HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
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__val = (CYG_WORD16)((_val_>>(_offset_*8))&0xFFFF); \
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CYG_MACRO_END
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#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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CYG_MACRO_START \
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CYG_WORD32 _val_; \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
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HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
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__val = (CYG_WORD32)_val_; \
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CYG_MACRO_END
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// Write a value to the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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// We can only make 32 bit accesses to the PCI config data register, hence
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// all the shifing and masking in these macros.
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// Note that we do not need to use HAL_PCI_CONFIG_READ() here since we
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// should not be writing to config space locations that we do not already
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// know are valid.
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#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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CYG_MACRO_START \
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CYG_WORD32 _val_; \
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CYG_WORD32 _offset_ = __offset & 3; \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
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HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
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_val_ &= ~(0xFF<<(_offset_*8)); \
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_val_ |= (__val)<<(_offset_*8); \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
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CYG_MACRO_END
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#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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CYG_MACRO_START \
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CYG_WORD32 _val_; \
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CYG_WORD32 _offset_ = __offset & 2; \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
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HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
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_val_ &= ~(0xFFFF<<(_offset_*8)); \
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_val_ |= (__val)<<(_offset_*8); \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
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CYG_MACRO_END
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#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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CYG_MACRO_START \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
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HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, __val); \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// Resources
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// Map PCI device resources starting from these addresses in PCI space.
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#define HAL_PCI_ALLOC_BASE_MEMORY 0
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#define HAL_PCI_ALLOC_BASE_IO 0x0c000000
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// Translate the PCI interrupt requested by the device (INTA#, INTB#,
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// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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// We don't actually know what the mappings are at present for this
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// board. The following is therefore just a temporary guess until
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// we can find out.
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#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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CYG_MACRO_START \
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cyg_uint8 __req; \
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HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
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if (0 != __req) { \
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CYG_ADDRWORD __translation[4] = { \
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CYGNUM_HAL_INTERRUPT_PCI_INTA, /* INTA# */ \
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CYGNUM_HAL_INTERRUPT_PCI_INTB, /* INTB# */ \
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CYGNUM_HAL_INTERRUPT_PCI_INTC, /* INTC# */ \
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CYGNUM_HAL_INTERRUPT_PCI_INTD };/* INTD# */ \
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\
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__vec = __translation[(((__req-1)+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
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\
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__valid = true; \
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} else { \
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/* Device will not generate interrupt requests. */ \
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__valid = false; \
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} \
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CYG_MACRO_END
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// Ignore all devices on not on bus 0 since those all seem to map to the
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// Nile II controller itself.
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#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
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((__bus) != 0)
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//-----------------------------------------------------------------------------
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// end of plf_io.h
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#endif // CYGONCE_PLF_IO_H
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