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#ifndef CYGONCE_FREESCALE_EDMA_H
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#define CYGONCE_FREESCALE_EDMA_H
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//===========================================================================
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//
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// freescale_edma.h
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//
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// Freescale eDMA specific registers
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//
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//===========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//===========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Ilija Kocho <ilijak@siva.com.mk>
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// Date: 2011-11-04
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// Purpose: Freescale eDMA specific registers
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// Description:
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// Usage: #include <cyg/hal/freescale_edma.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================
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// ----------------------------------------------------------------------------
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// DMAMUX DMA Multiplexer
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// DMAMUX - Peripheral register structure
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typedef volatile struct cyghwr_hal_freescale_dmamux_s {
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cyg_uint8 chcfg[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Channel Configuration Register
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} cyghwr_hal_freescale_dmamux_t;
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// DMAMUX - Peripheral instance base addresses
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#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000)
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// ----------------------------------------------------------------------------
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// DMAMUX Register Masks
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// CHCFG Bit Fields
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#define FREESCALE_DMAMUX_CHCFG_SOURCE_M 0x3F
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#define FREESCALE_DMAMUX_CHCFG_SOURCE(__val) \
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(__val & FREESCALE_DMAMUX_CHCFG_SOURCE_M)
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#define FREESCALE_DMAMUX_CHCFG_TRIG_M 0x40
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#define FREESCALE_DMAMUX_CHCFG_TRIG_S 6
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#define FREESCALE_DMAMUX_CHCFG_ENBL_M 0x80
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#define FREESCALE_DMAMUX_CHCFG_ENBL_S 7
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#define FREESCALE_DMAMUX_CHCFG_ASIS FREESCALE_DMAMUX_CHCFG_ENBL_M
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// DMAMUX DMA request sources
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// Provided by HAL (var_io_devs.h)
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#define FREESCALE_DMAMUX_SRC(__src) (_src)
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//---------------------------------------------------------------------------
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// eDMA
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// Indices for cyghwr_hal_freescale_edma_t::dchpri[]
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enum {
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FREESCALE_DMA_PRI_CH3, FREESCALE_DMA_PRI_CH2,
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FREESCALE_DMA_PRI_CH1, FREESCALE_DMA_PRI_CH0,
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FREESCALE_DMA_PRI_CH7, FREESCALE_DMA_PRI_CH6,
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FREESCALE_DMA_PRI_CH5, FREESCALE_DMA_PRI_CH4,
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FREESCALE_DMA_PRI_CH11, FREESCALE_DMA_PRI_CH10,
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FREESCALE_DMA_PRI_CH9, FREESCALE_DMA_PRI_CH8,
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FREESCALE_DMA_PRI_CH15, FREESCALE_DMA_PRI_CH14,
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FREESCALE_DMA_PRI_CH13, FREESCALE_DMA_PRI_CH12
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};
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// Transfer control descriptor
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typedef volatile struct cyghwr_hal_freescale_edma_tcd_s
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cyghwr_hal_freescale_edma_tcd_t;
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#define CYGBLD_FREESCALE_EDMA_TCD_ALIGN CYGBLD_ATTRIB_ALIGN(32)
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struct cyghwr_hal_freescale_edma_tcd_s {
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volatile void* saddr; // Source Address
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cyg_uint16 soff; // Signed Source Address Offset
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cyg_uint16 attr; // Transfer Attributes
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union {
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cyg_uint32 mlno; // Minor Byte Count (Minor Loop Dis)
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// Signed Minor Loop Off:
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cyg_uint32 mloffyes; // MinoL Eena and Off Dis
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cyg_uint32 mloffno; // Minor Loop and Off Ena
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} nbytes;
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cyg_uint32 slast; // Last Source Address Adjustment
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volatile void *daddr; // Destination Address
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cyg_uint16 doff; // Signed Destination Address Offset
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union { // Current Minor Loop Link:
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cyg_uint16 elinkyes; // Major Loop Count (Ch Lnkng Ena)
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cyg_uint16 elinkno; // Major Loop Count (Ch Lnkng Dis)
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} citer;
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union {
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cyg_uint32 dlast; // Last Dst Addr Adj/Scat Gath Addr
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cyghwr_hal_freescale_edma_tcd_t *sga; // Last Dst Addr Adj/Scat Gath Addr
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};
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cyg_uint16 csr; // Control and Status
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union { // Beginning Minor Loop Link:
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cyg_uint16 elinkno; // Major Loop Cnt (Ch Lnkng Dis)
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cyg_uint16 elinkyes; // Major Loop Cnt (Ch Lnkng Ena)
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} biter;
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};
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// DMA - Peripheral register structure
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typedef volatile struct cyghwr_hal_freescale_edma_s {
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cyg_uint32 cr; // Control Register
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cyg_uint32 es; // Error Status Register
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cyg_uint32 reserved_0;
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cyg_uint32 erq; // Enable Request Register
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cyg_uint32 reserved_1;
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cyg_uint32 eei; // Enable Error Interrupt Register
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cyg_uint8 ceei; // Clear Enable Error Interrupt Register
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cyg_uint8 seei; // Set Enable Error Interrupt Register
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cyg_uint8 cerq; // Clear Enable Request Register
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cyg_uint8 serq; // Set Enable Request Register
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cyg_uint8 cdne; // Clear DONE Status Bit Register
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cyg_uint8 ssrt; // Set START Bit Register
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cyg_uint8 cerr; // Clear Error Register
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cyg_uint8 cint; // Clear Interrupt Request Register
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cyg_uint32 reserved_2;
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cyg_uint32 irq; // Interrupt Request Register
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cyg_uint32 reserved_3;
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cyg_uint32 err; // Error Register
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cyg_uint32 reserved_4;
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cyg_uint32 hrs; // Hardware Request Status Register
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cyg_uint8 reserved_5[0x8100 - (0x8034 + 4)];
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cyg_uint8 dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Priorities
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cyg_uint8 reserved_6[0x9000 - 0x8100 - CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM];
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cyghwr_hal_freescale_edma_tcd_t
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tcd[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Transfer control descriptors
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} cyghwr_hal_freescale_edma_t;
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#define CYGHWR_HAL_FREESCALE_EDMA0_P ((cyghwr_hal_freescale_edma_t *)0x40008000)
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// ----------------------------------------------------------------------------
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// DMA Register Bits
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// CR Bit Fields
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#define FREESCALE_EDMA_CR_EDBG_M 0x2
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#define FREESCALE_EDMA_CR_EDBG_S 1
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#define FREESCALE_EDMA_CR_ERCA_M 0x4
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#define FREESCALE_EDMA_CR_ERCA_S 2
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#define FREESCALE_EDMA_CR_HOE_M 0x10
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#define FREESCALE_EDMA_CR_HOE_S 4
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#define FREESCALE_EDMA_CR_HALT_M 0x20
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#define FREESCALE_EDMA_CR_HALT_S 5
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#define FREESCALE_EDMA_CR_CLM_M 0x40
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#define FREESCALE_EDMA_CR_CLM_S 6
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#define FREESCALE_EDMA_CR_EMLM_M 0x80
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#define FREESCALE_EDMA_CR_EMLM_S 7
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#define FREESCALE_EDMA_CR_ECX_M 0x10000
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#define FREESCALE_EDMA_CR_ECX_S 16
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#define FREESCALE_EDMA_CR_CX_M 0x20000
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#define FREESCALE_EDMA_CR_CX_S 17
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// ES Bit Fields
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#define FREESCALE_EDMA_ES_DBE_M 0x1
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#define FREESCALE_EDMA_ES_DBE_S 0
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#define FREESCALE_EDMA_ES_SBE_M 0x2
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#define FREESCALE_EDMA_ES_SBE_S 1
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#define FREESCALE_EDMA_ES_SGE_M 0x4
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#define FREESCALE_EDMA_ES_SGE_S 2
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#define FREESCALE_EDMA_ES_NCE_M 0x8
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#define FREESCALE_EDMA_ES_NCE_S 3
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#define FREESCALE_EDMA_ES_DOE_M 0x10
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#define FREESCALE_EDMA_ES_DOE_S 4
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#define FREESCALE_EDMA_ES_DAE_M 0x20
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#define FREESCALE_EDMA_ES_DAE_S 5
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#define FREESCALE_EDMA_ES_SOE_M 0x40
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#define FREESCALE_EDMA_ES_SOE_S 6
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#define FREESCALE_EDMA_ES_SAE_M 0x80
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#define FREESCALE_EDMA_ES_SAE_S 7
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#define FREESCALE_EDMA_ES_ERRCHN_M 0xF00
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#define FREESCALE_EDMA_ES_ERRCHN_S 8
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#define FREESCALE_EDMA_ES_ERRCHN(__val) \
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VALUE_(FREESCALE_EDMA_ES_ERRCHN_S, __val)
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#define FREESCALE_EDMA_ES_CPE_M 0x4000
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#define FREESCALE_EDMA_ES_CPE_S 14
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#define FREESCALE_EDMA_ES_ECX_M 0x10000
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#define FREESCALE_EDMA_ES_ECX_S 16
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#define FREESCALE_EDMA_ES_VLD_M 0x80000000
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#define FREESCALE_EDMA_ES_VLD_S 31
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// ERQ Bit Fields
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#define FREESCALE_EDMA_ERQ(__rq) BIT(__rq)
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// EEI Bit Fields
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#define FREESCALE_EDMA_EEI(__rq) BIT(__rq)
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#define FREESCALE_EDMA_CHAN_M 0x0F
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// CEEI Bit Fields
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#define FREESCALE_EDMA_CEEI_CEEI(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_CEEI_CAEE_M 0x40
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#define FREESCALE_EDMA_CEEI_CAEE_S 6
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#define FREESCALE_EDMA_CEEI_NOP_M 0x80
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#define FREESCALE_EDMA_CEEI_NOP_S 7
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// SEEI Bit Fields
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#define FREESCALE_EDMA_SEEI_SEEI_M 0xF
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#define FREESCALE_EDMA_SEEI_SEEI(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_SEEI_SAEE_M 0x40
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#define FREESCALE_EDMA_SEEI_SAEE_S 6
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#define FREESCALE_EDMA_SEEI_NOP_M 0x80
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#define FREESCALE_EDMA_SEEI_NOP_S 7
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// CERQ Bit Fields
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#define FREESCALE_EDMA_CERQ_CERQ(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_CERQ_CAER_M 0x40
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#define FREESCALE_EDMA_CERQ_CAER_S 6
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#define FREESCALE_EDMA_CERQ_NOP_M 0x80
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#define FREESCALE_EDMA_CERQ_NOP_S 7
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// SERQ Bit Fields
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#define FREESCALE_EDMA_SERQ_SERQ(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_SERQ_SAER_M 0x40
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#define FREESCALE_EDMA_SERQ_SAER_S 6
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#define FREESCALE_EDMA_SERQ_NOP_M 0x80
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#define FREESCALE_EDMA_SERQ_NOP_S 7
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// CDNE Bit Fields
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#define FREESCALE_EDMA_CDNE_CDNE(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_CDNE_CADN_M 0x40
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#define FREESCALE_EDMA_CDNE_CADN_S 6
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#define FREESCALE_EDMA_CDNE_NOP_M 0x80
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#define FREESCALE_EDMA_CDNE_NOP_S 7
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// SSRT Bit Fields
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#define FREESCALE_EDMA_SSRT_SSRT(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_SSRT_SAST_M 0x40
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#define FREESCALE_EDMA_SSRT_SAST_S 6
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#define FREESCALE_EDMA_SSRT_NOP_M 0x80
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#define FREESCALE_EDMA_SSRT_NOP_S 7
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// CERR Bit Fields
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#define FREESCALE_EDMA_CERR_CERR(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_CERR_CAEI_M 0x40
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#define FREESCALE_EDMA_CERR_CAEI_S 6
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#define FREESCALE_EDMA_CERR_NOP_M 0x80
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#define FREESCALE_EDMA_CERR_NOP_S 7
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// CINT Bit Fields
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#define FREESCALE_EDMA_CINT_CINT(__val) (__val & FREESCALE_EDMA_CHAN_M)
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#define FREESCALE_EDMA_CINT_CAIR_M 0x40
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#define FREESCALE_EDMA_CINT_CAIR_S 6
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#define FREESCALE_EDMA_CINT_NOP_M 0x80
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#define FREESCALE_EDMA_CINT_NOP_S 7
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// INT Bit Fields
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#define FREESCALE_EDMA_INT(__ch) BIT(__ch)
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// ERR Bit Fields
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#define FREESCALE_EDMA_ERR(__ch) BIT(__ch)
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// HRS Bit Fields
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#define FREESCALE_EDMA_HRS(__ch) BIT(__ch)
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// DCHPRI Bit Fields
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#define FREESCALE_EDMA_DCHPRI_CHPRI_M 0xF
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#define FREESCALE_EDMA_DCHPRI_CHPRI(__val) \
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(__val & FREESCALE_EDMA_DCHPRI_CHPRI_M)
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#define FREESCALE_EDMA_DCHPRI_DPA_M 0x40
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#define FREESCALE_EDMA_DCHPRI_DPA_S 6
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#define FREESCALE_EDMA_DCHPRI_ECP_M 0x80
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#define FREESCALE_EDMA_DCHPRI_ECP_S 7
|
275 |
|
|
#define FREESCALE_EDMA_DCHPRI_ASIS 0x20
|
276 |
|
|
// SOFF Bit Fields
|
277 |
|
|
#define FREESCALE_EDMA_SOFF_SOFF_M 0xFFFF
|
278 |
|
|
#define FREESCALE_EDMA_SOFF_SOFF(__val) \
|
279 |
|
|
(__val & FREESCALE_EDMA_SOFF_SOFF_M)
|
280 |
|
|
// ATTR Bit Fields
|
281 |
|
|
#define FREESCALE_EDMA_ATTR_DSIZE_M 0x7
|
282 |
|
|
#define FREESCALE_EDMA_ATTR_DSIZE(__val) \
|
283 |
|
|
(__val & FREESCALE_EDMA_ATTR_DSIZE_M)
|
284 |
|
|
#define FREESCALE_EDMA_ATTR_DMOD_M 0xF8
|
285 |
|
|
#define FREESCALE_EDMA_ATTR_DMOD_S 3
|
286 |
|
|
#define FREESCALE_EDMA_ATTR_DMOD(__val) \
|
287 |
|
|
VALUE_(FREESCALE_EDMA_ATTR_DMOD_S, __val)
|
288 |
|
|
#define FREESCALE_EDMA_ATTR_SSIZE_M 0x700
|
289 |
|
|
#define FREESCALE_EDMA_ATTR_SSIZE_S 8
|
290 |
|
|
#define FREESCALE_EDMA_ATTR_SSIZE(__val) \
|
291 |
|
|
VALUE_(FREESCALE_EDMA_ATTR_SSIZE_S, __val)
|
292 |
|
|
#define FREESCALE_EDMA_ATTR_SMOD_M 0xF800
|
293 |
|
|
#define FREESCALE_EDMA_ATTR_SMOD_S 11
|
294 |
|
|
#define FREESCALE_EDMA_ATTR_SMOD(__val) \
|
295 |
|
|
VALUE_(FREESCALE_EDMA_ATTR_SMOD_S, __val)
|
296 |
|
|
#define FREESCALE_EDMA_ATTR_SIZE_8 0
|
297 |
|
|
#define FREESCALE_EDMA_ATTR_SIZE_16 1
|
298 |
|
|
#define FREESCALE_EDMA_ATTR_SIZE_32 2
|
299 |
|
|
#define FREESCALE_EDMA_ATTR_SIZE_16B 4
|
300 |
|
|
// NBYTES_MLOFFNO Bit Fields
|
301 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES_M 0x3FFFFFFF
|
302 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES(__val) \
|
303 |
|
|
(__val & FREESCALE_EDMA_NBYTES_MLOFFNO_NBYTES_M)
|
304 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFNO_DMLOE_M 0x40000000
|
305 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFNO_DMLOE_S 30
|
306 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFNO_SMLOE_M 0x80000000
|
307 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFNO_SMLOE_S 31
|
308 |
|
|
// NBYTES_MLOFFYES Bit Fields
|
309 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES_M 0x3FF
|
310 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES(__val) \
|
311 |
|
|
(__val & FREESCALE_EDMA_NBYTES_MLOFFYES_NBYTES(__val))
|
312 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_M 0x3FFFFC00
|
313 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_S 10
|
314 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF(__val) \
|
315 |
|
|
VALUE_(FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF_S, __val)
|
316 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_DMLOE_M 0x40000000
|
317 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_DMLOE_S 30
|
318 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_SMLOE_M 0x80000000
|
319 |
|
|
#define FREESCALE_EDMA_NBYTES_MLOFFYES_SMLOE_S 31
|
320 |
|
|
// DOFF Bit Fields
|
321 |
|
|
#define FREESCALE_EDMA_DOFF_DOFF_M 0xFFFF
|
322 |
|
|
#define FREESCALE_EDMA_DOFF_DOFF(__val) (__val & FREESCALE_EDMA_DOFF_DOFF_M)
|
323 |
|
|
// CITER_ELINKYES Bit Fields
|
324 |
|
|
#define FREESCALE_EDMA_CITER_ELINKYES_CITER_M 0x1FF
|
325 |
|
|
#define FREESCALE_EDMA_CITER_ELINKYES_CITER(__val) \
|
326 |
|
|
(__val & FREESCALE_EDMA_CITER_ELINKYES_CITER_M)
|
327 |
|
|
#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH_M 0x1E00
|
328 |
|
|
#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH_S 9
|
329 |
|
|
#define FREESCALE_EDMA_CITER_ELINKYES_LINKCH(__val) \
|
330 |
|
|
VALUE_(FREESCALE_EDMA_CITER_ELINKYES_LINKCH_S, __val)
|
331 |
|
|
#define FREESCALE_EDMA_CITER_ELINKYES_ELINK_M 0x8000
|
332 |
|
|
#define FREESCALE_EDMA_CITER_ELINKYES_ELINK_S 15
|
333 |
|
|
// CITER_ELINKNO Bit Fields
|
334 |
|
|
#define FREESCALE_EDMA_CITER_ELINKNO_CITER_M 0x7FFF
|
335 |
|
|
#define FREESCALE_EDMA_CITER_ELINKNO_CITER(__val) \
|
336 |
|
|
(__val & FREESCALE_EDMA_CITER_ELINKNO_CITER_M)
|
337 |
|
|
#define FREESCALE_EDMA_CITER_ELINKNO_ELINK_M 0x8000
|
338 |
|
|
#define FREESCALE_EDMA_CITER_ELINKNO_ELINK_S 15
|
339 |
|
|
// CSR Bit Fields
|
340 |
|
|
#define FREESCALE_EDMA_CSR_START_M 0x1
|
341 |
|
|
#define FREESCALE_EDMA_CSR_START_S 0
|
342 |
|
|
#define FREESCALE_EDMA_CSR_INTMAJOR_M 0x2
|
343 |
|
|
#define FREESCALE_EDMA_CSR_INTMAJOR_S 1
|
344 |
|
|
#define FREESCALE_EDMA_CSR_INTHALF_M 0x4
|
345 |
|
|
#define FREESCALE_EDMA_CSR_INTHALF_S 2
|
346 |
|
|
#define FREESCALE_EDMA_CSR_DREQ_M 0x8
|
347 |
|
|
#define FREESCALE_EDMA_CSR_DREQ_S 3
|
348 |
|
|
#define FREESCALE_EDMA_CSR_ESG_M 0x10
|
349 |
|
|
#define FREESCALE_EDMA_CSR_ESG_S 4
|
350 |
|
|
#define FREESCALE_EDMA_CSR_MAJORELINK_M 0x20
|
351 |
|
|
#define FREESCALE_EDMA_CSR_MAJORELINK_S 5
|
352 |
|
|
#define FREESCALE_EDMA_CSR_ACTIVE_M 0x40
|
353 |
|
|
#define FREESCALE_EDMA_CSR_ACTIVE_S 6
|
354 |
|
|
#define FREESCALE_EDMA_CSR_DONE_M 0x80
|
355 |
|
|
#define FREESCALE_EDMA_CSR_DONE_S 7
|
356 |
|
|
#define FREESCALE_EDMA_CSR_MAJORLINKCH_M 0xF00
|
357 |
|
|
#define FREESCALE_EDMA_CSR_MAJORLINKCH_S 8
|
358 |
|
|
#define FREESCALE_EDMA_CSR_MAJORLINKCH(__val) \
|
359 |
|
|
VALUE_(FREESCALE_EDMA_CSR_MAJORLINKCH_S, __val)
|
360 |
|
|
#define FREESCALE_EDMA_CSR_BWC_M 0xC000
|
361 |
|
|
#define FREESCALE_EDMA_CSR_BWC_S 14
|
362 |
|
|
#define FREESCALE_EDMA_CSR_BWC(__val) \
|
363 |
|
|
VALUE_(FREESCALE_EDMA_CSR_BWC_S, __val)
|
364 |
|
|
#define FREESCALE_EDMA_CSR_BWC_0 0
|
365 |
|
|
#define FREESCALE_EDMA_CSR_BWC_MEDIUM FREESCALE_EDMA_CSR_BWC(2)
|
366 |
|
|
#define FREESCALE_EDMA_CSR_BWC_NICE FREESCALE_EDMA_CSR_BWC(3)
|
367 |
|
|
|
368 |
|
|
// BITER_ELINKNO Bit Fields
|
369 |
|
|
#define FREESCALE_EDMA_BITER_ELINKNO_BITER_M 0x7FFF
|
370 |
|
|
#define FREESCALE_EDMA_BITER_ELINKNO_BITER(__val) \
|
371 |
|
|
(__val FREESCALE_EDMA_BITER_ELINKNO_BITER_M)
|
372 |
|
|
#define FREESCALE_EDMA_BITER_ELINKNO_ELINK_M 0x8000
|
373 |
|
|
#define FREESCALE_EDMA_BITER_ELINKNO_ELINK_S 15
|
374 |
|
|
// BITER_ELINKYES Bit Fields
|
375 |
|
|
#define FREESCALE_EDMA_BITER_ELINKYES_BITER_M 0x1FF
|
376 |
|
|
#define FREESCALE_EDMA_BITER_ELINKYES_BITER(__val) \
|
377 |
|
|
(__val & FREESCALE_EDMA_BITER_ELINKYES_BITER_M)
|
378 |
|
|
#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH_M 0x1E00
|
379 |
|
|
#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH_S 9
|
380 |
|
|
#define FREESCALE_EDMA_BITER_ELINKYES_LINKCH(__val) \
|
381 |
|
|
VALUE_(FREESCALE_EDMA_BITER_ELINKYES_LINKCH_S, __val)
|
382 |
|
|
#define FREESCALE_EDMA_BITER_ELINKYES_ELINK_M 0x8000
|
383 |
|
|
#define FREESCALE_EDMA_BITER_ELINKYES_ELINK_S 15
|
384 |
|
|
|
385 |
|
|
//-----------------------------------------------------------------------------
|
386 |
|
|
|
387 |
|
|
// DMA Channel data
|
388 |
|
|
typedef struct cyghwr_hal_freescale_dma_chan_set_s {
|
389 |
|
|
cyg_uint8 dma_src; // Data source
|
390 |
|
|
cyg_uint8 dma_chan_i; // Channel index
|
391 |
|
|
cyg_uint8 dma_prio; // DMA channel priority
|
392 |
|
|
cyg_uint8 isr_prio; // Interrupt priority
|
393 |
|
|
cyg_uint8 isr_num; // Interrupt vector
|
394 |
|
|
cyg_uint8 isr_ena; // Interruot enable
|
395 |
|
|
} cyghwr_hal_freescale_dma_chan_set_t;
|
396 |
|
|
|
397 |
|
|
// DMA Channel set
|
398 |
|
|
typedef struct cyghwr_hal_freescale_dma_set_s {
|
399 |
|
|
cyghwr_hal_freescale_edma_t *edma_p;
|
400 |
|
|
cyghwr_hal_freescale_dmamux_t *dmamux_p;
|
401 |
|
|
const cyghwr_hal_freescale_dma_chan_set_t *chan_p;
|
402 |
|
|
cyg_uint8 chan_n;
|
403 |
|
|
} cyghwr_hal_freescale_dma_set_t;
|
404 |
|
|
|
405 |
|
|
|
406 |
|
|
__externC void
|
407 |
|
|
hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p);
|
408 |
|
|
|
409 |
|
|
__externC void
|
410 |
|
|
hal_freescale_edma_diag(cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask);
|
411 |
|
|
|
412 |
|
|
__externC void
|
413 |
|
|
hal_freescale_edma_transfer_init(cyghwr_hal_freescale_edma_t *edma_p,
|
414 |
|
|
cyg_uint8 chan_i,
|
415 |
|
|
const cyghwr_hal_freescale_edma_tcd_t *tcd_cfg_p);
|
416 |
|
|
__externC void
|
417 |
|
|
hal_freescale_edma_tcd_diag(cyghwr_hal_freescale_edma_tcd_t *tcd_p, cyg_int32 chan_i, const char *prefix);
|
418 |
|
|
|
419 |
|
|
__externC void
|
420 |
|
|
hal_freescale_edma_transfer_diag (cyghwr_hal_freescale_edma_t *edma_p,
|
421 |
|
|
cyg_uint8 chan_i, cyg_bool recurse);
|
422 |
|
|
|
423 |
|
|
__externC inline void
|
424 |
|
|
hal_freescale_edma_erq_enable(cyghwr_hal_freescale_edma_t *edma_p,
|
425 |
|
|
cyg_uint8 chan_i)
|
426 |
|
|
{
|
427 |
|
|
edma_p->serq = chan_i;
|
428 |
|
|
}
|
429 |
|
|
|
430 |
|
|
__externC inline void
|
431 |
|
|
hal_freescale_edma_erq_disable(cyghwr_hal_freescale_edma_t *edma_p,
|
432 |
|
|
cyg_uint8 chan_i)
|
433 |
|
|
{
|
434 |
|
|
edma_p->cerq = chan_i;
|
435 |
|
|
}
|
436 |
|
|
|
437 |
|
|
__externC inline void
|
438 |
|
|
hal_freescale_edma_cleardone(cyghwr_hal_freescale_edma_t *edma_p,
|
439 |
|
|
cyg_uint8 chan_i)
|
440 |
|
|
{
|
441 |
|
|
edma_p->cdne = chan_i;
|
442 |
|
|
}
|
443 |
|
|
|
444 |
|
|
__externC inline void
|
445 |
|
|
hal_freescale_edma_irq_enable(cyghwr_hal_freescale_edma_t *edma_p,
|
446 |
|
|
cyg_uint8 chan_i)
|
447 |
|
|
{
|
448 |
|
|
edma_p->seei = chan_i;
|
449 |
|
|
}
|
450 |
|
|
|
451 |
|
|
__externC inline void
|
452 |
|
|
hal_freescale_edma_irq_disable(cyghwr_hal_freescale_edma_t *edma_p,
|
453 |
|
|
cyg_uint8 chan_i)
|
454 |
|
|
{
|
455 |
|
|
edma_p->ceei = chan_i;
|
456 |
|
|
}
|
457 |
|
|
|
458 |
|
|
__externC inline void
|
459 |
|
|
hal_freescale_edma_irq_clear(cyghwr_hal_freescale_edma_t *edma_p,
|
460 |
|
|
cyg_uint8 chan_i)
|
461 |
|
|
{
|
462 |
|
|
edma_p->cint = chan_i;
|
463 |
|
|
}
|
464 |
|
|
|
465 |
|
|
__externC inline void
|
466 |
|
|
hal_freescale_edma_transfer_clear(cyghwr_hal_freescale_edma_t *edma_p,
|
467 |
|
|
cyg_uint8 chan_i)
|
468 |
|
|
{
|
469 |
|
|
edma_p->tcd[chan_i].csr &= ~FREESCALE_EDMA_CSR_DONE_M;
|
470 |
|
|
}
|
471 |
|
|
|
472 |
|
|
__externC inline void
|
473 |
|
|
hal_freescale_edma_transfer_start(cyghwr_hal_freescale_edma_t *edma_p,
|
474 |
|
|
cyg_uint8 chan_i)
|
475 |
|
|
{
|
476 |
|
|
edma_p->ssrt = chan_i;
|
477 |
|
|
}
|
478 |
|
|
|
479 |
|
|
#define HAL_DMA_TRANSFER_STOP(__edma,__chan) \
|
480 |
|
|
hal_freescale_edma_erq_disable(__edma, __chan)
|
481 |
|
|
#define HAL_DMA_TRANSFER_START(__edma,__chan) \
|
482 |
|
|
hal_freescale_edma_erq_enable(__edma, __chan)
|
483 |
|
|
#define HAL_DMA_TRANSFER_CLEAR(__edma,__chan) \
|
484 |
|
|
hal_freescale_edma_cleardone(__edma, __chan)
|
485 |
|
|
|
486 |
|
|
// end of var_io_dma.h
|
487 |
|
|
#endif // CYGONCE_FREESCALE_EDMA_H
|