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skrzyp |
#ifndef CYGONCE_HAL_VAR_INTR_H
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#define CYGONCE_HAL_VAR_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// AM31 Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jskov,
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// gthomas, jlarmour
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// Date: 1999-02-16
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// Purpose: AM31 Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for AM31 variants of the MN10300
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// architecture.
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//
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// Usage:
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// #include <cyg/hal/var_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/plf_intr.h>
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//--------------------------------------------------------------------------
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// The MN10300 has a somewhat complex interrupt structure. Besides the
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// reset and NMI vectors there are seven maskable interrupt vectors
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// which must point to code in the 64k starting at 0x40000000. There
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// are also 25 Interrupt control groups, each of which can have 4
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// interrupt lines attached, for a theoretical total of 100 interrupts
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// (!). Some of these are dedicated to specific devices, other to
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// external pins, and others are not connected to anything, resulting
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// in only 45 that can actually be delivered. Each control group may
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// be assigned one of seven interrupt levels, and is delivered to the
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// corresponding vector. Software can then use a register to determine
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// the delivering group and detect from there which interrupt has been
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// delivered.
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//
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// The approach we will adopt at present is for the code attached to
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// each vector to save state and jump via a table to a VSR. The
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// default VSR will fully decode the delivered interrupt into a table
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// of isr/data/object entries. VSR replacement will operate on the
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// first level indirection table rather than the hardware
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// vectors. This is the fastest mechanism, however it needs 100*3*4 +
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// 7*4 = 1228 bytes for the tables.
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//
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//--------------------------------------------------------------------------
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// Interrupt vectors.
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// The level-specific hardware vectors
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// These correspond to VSRs and are the values to use for HAL_VSR_GET/SET
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#define CYGNUM_HAL_VECTOR_0 0
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#define CYGNUM_HAL_VECTOR_1 1
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#define CYGNUM_HAL_VECTOR_2 2
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#define CYGNUM_HAL_VECTOR_3 3
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#define CYGNUM_HAL_VECTOR_4 4
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#define CYGNUM_HAL_VECTOR_5 5
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#define CYGNUM_HAL_VECTOR_6 6
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#define CYGNUM_HAL_VECTOR_NMI_ENTRY 7
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#define CYGNUM_HAL_VECTOR_TRAP 8
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#define CYGNUM_HAL_VECTOR_NMI 9
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#define CYGNUM_HAL_VECTOR_WATCHDOG 10
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#define CYGNUM_HAL_VECTOR_SYSTEM_ERROR 11
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#define CYGNUM_HAL_VSR_MIN 0
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#define CYGNUM_HAL_VSR_MAX 11
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#define CYGNUM_HAL_VSR_COUNT 12
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// Exception numbers. These are the values used when passed out to an
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// external exception handler using cyg_hal_deliver_exception()
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#define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI
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#define CYGNUM_HAL_EXCEPTION_WATCHDOG CYGNUM_HAL_VECTOR_WATCHDOG
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#define CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR CYGNUM_HAL_VECTOR_SYSTEM_ERROR
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#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN
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#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
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#define CYGNUM_HAL_EXCEPTION_COUNT CYGNUM_HAL_VSR_COUNT
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// The decoded interrupts
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#define CYGNUM_HAL_INTERRUPT_NMIRQ 0
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#define CYGNUM_HAL_INTERRUPT_WATCHDOG 1
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#define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR 2
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#define CYGNUM_HAL_INTERRUPT_RESERVED_3 3
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#define CYGNUM_HAL_INTERRUPT_RESERVED_4 4
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#define CYGNUM_HAL_INTERRUPT_RESERVED_5 5
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#define CYGNUM_HAL_INTERRUPT_RESERVED_6 6
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#define CYGNUM_HAL_INTERRUPT_RESERVED_7 7
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#define CYGNUM_HAL_INTERRUPT_TIMER_0 8
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#define CYGNUM_HAL_INTERRUPT_RESERVED_9 9
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#define CYGNUM_HAL_INTERRUPT_RESERVED_10 10
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#define CYGNUM_HAL_INTERRUPT_RESERVED_11 11
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#define CYGNUM_HAL_INTERRUPT_TIMER_1 12
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#define CYGNUM_HAL_INTERRUPT_RESERVED_13 13
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#define CYGNUM_HAL_INTERRUPT_RESERVED_14 14
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#define CYGNUM_HAL_INTERRUPT_RESERVED_15 15
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#define CYGNUM_HAL_INTERRUPT_TIMER_2 16
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#define CYGNUM_HAL_INTERRUPT_RESERVED_17 17
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#define CYGNUM_HAL_INTERRUPT_RESERVED_18 18
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#define CYGNUM_HAL_INTERRUPT_RESERVED_19 19
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#define CYGNUM_HAL_INTERRUPT_TIMER_3 20
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#define CYGNUM_HAL_INTERRUPT_RESERVED_21 21
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#define CYGNUM_HAL_INTERRUPT_RESERVED_22 22
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#define CYGNUM_HAL_INTERRUPT_RESERVED_23 23
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#define CYGNUM_HAL_INTERRUPT_TIMER_4 24
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#define CYGNUM_HAL_INTERRUPT_RESERVED_25 25
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#define CYGNUM_HAL_INTERRUPT_RESERVED_26 26
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#define CYGNUM_HAL_INTERRUPT_RESERVED_27 27
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#define CYGNUM_HAL_INTERRUPT_TIMER_5 28
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#define CYGNUM_HAL_INTERRUPT_RESERVED_29 29
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#define CYGNUM_HAL_INTERRUPT_RESERVED_30 30
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#define CYGNUM_HAL_INTERRUPT_RESERVED_31 31
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#define CYGNUM_HAL_INTERRUPT_TIMER_6 32
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#define CYGNUM_HAL_INTERRUPT_RESERVED_33 33
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#define CYGNUM_HAL_INTERRUPT_RESERVED_34 34
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#define CYGNUM_HAL_INTERRUPT_RESERVED_35 35
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#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A 36
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#define CYGNUM_HAL_INTERRUPT_RESERVED_37 37
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#define CYGNUM_HAL_INTERRUPT_RESERVED_38 38
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#define CYGNUM_HAL_INTERRUPT_RESERVED_39 39
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#define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B 40
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#define CYGNUM_HAL_INTERRUPT_RESERVED_41 41
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#define CYGNUM_HAL_INTERRUPT_RESERVED_42 42
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#define CYGNUM_HAL_INTERRUPT_RESERVED_43 43
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#define CYGNUM_HAL_INTERRUPT_RESERVED_44 44
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#define CYGNUM_HAL_INTERRUPT_RESERVED_45 45
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#define CYGNUM_HAL_INTERRUPT_RESERVED_46 46
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#define CYGNUM_HAL_INTERRUPT_RESERVED_47 47
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#define CYGNUM_HAL_INTERRUPT_DMA0 48
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#define CYGNUM_HAL_INTERRUPT_RESERVED_49 49
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#define CYGNUM_HAL_INTERRUPT_RESERVED_50 50
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#define CYGNUM_HAL_INTERRUPT_RESERVED_51 51
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#define CYGNUM_HAL_INTERRUPT_DMA1 52
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#define CYGNUM_HAL_INTERRUPT_RESERVED_53 53
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#define CYGNUM_HAL_INTERRUPT_RESERVED_54 54
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#define CYGNUM_HAL_INTERRUPT_RESERVED_55 55
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#define CYGNUM_HAL_INTERRUPT_DMA2 56
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#define CYGNUM_HAL_INTERRUPT_RESERVED_57 57
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#define CYGNUM_HAL_INTERRUPT_RESERVED_58 58
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#define CYGNUM_HAL_INTERRUPT_RESERVED_59 59
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#define CYGNUM_HAL_INTERRUPT_DMA3 60
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#define CYGNUM_HAL_INTERRUPT_RESERVED_61 61
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#define CYGNUM_HAL_INTERRUPT_RESERVED_62 62
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#define CYGNUM_HAL_INTERRUPT_RESERVED_63 63
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#define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX 64
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#define CYGNUM_HAL_INTERRUPT_RESERVED_65 65
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#define CYGNUM_HAL_INTERRUPT_RESERVED_66 66
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#define CYGNUM_HAL_INTERRUPT_RESERVED_67 67
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#define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX 68
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#define CYGNUM_HAL_INTERRUPT_RESERVED_69 69
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#define CYGNUM_HAL_INTERRUPT_RESERVED_70 70
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#define CYGNUM_HAL_INTERRUPT_RESERVED_71 71
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#define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 72
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#define CYGNUM_HAL_INTERRUPT_RESERVED_73 73
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#define CYGNUM_HAL_INTERRUPT_RESERVED_74 74
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#define CYGNUM_HAL_INTERRUPT_RESERVED_75 75
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#define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 76
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#define CYGNUM_HAL_INTERRUPT_RESERVED_77 77
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#define CYGNUM_HAL_INTERRUPT_RESERVED_78 78
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#define CYGNUM_HAL_INTERRUPT_RESERVED_79 79
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#define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX 80
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#define CYGNUM_HAL_INTERRUPT_RESERVED_81 81
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#define CYGNUM_HAL_INTERRUPT_RESERVED_82 82
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#define CYGNUM_HAL_INTERRUPT_RESERVED_83 83
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#define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX 84
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#define CYGNUM_HAL_INTERRUPT_RESERVED_85 85
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#define CYGNUM_HAL_INTERRUPT_RESERVED_86 86
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#define CYGNUM_HAL_INTERRUPT_RESERVED_87 87
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#define CYGNUM_HAL_INTERRUPT_RESERVED_88 88
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#define CYGNUM_HAL_INTERRUPT_RESERVED_89 89
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#define CYGNUM_HAL_INTERRUPT_RESERVED_90 90
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#define CYGNUM_HAL_INTERRUPT_RESERVED_91 91
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 92
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#define CYGNUM_HAL_INTERRUPT_RESERVED_93 93
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#define CYGNUM_HAL_INTERRUPT_RESERVED_94 94
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#define CYGNUM_HAL_INTERRUPT_RESERVED_95 95
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 96
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#define CYGNUM_HAL_INTERRUPT_RESERVED_97 97
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#define CYGNUM_HAL_INTERRUPT_RESERVED_98 98
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#define CYGNUM_HAL_INTERRUPT_RESERVED_99 99
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 100
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#define CYGNUM_HAL_INTERRUPT_RESERVED_101 101
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#define CYGNUM_HAL_INTERRUPT_RESERVED_102 102
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#define CYGNUM_HAL_INTERRUPT_RESERVED_103 103
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 104
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#define CYGNUM_HAL_INTERRUPT_RESERVED_105 105
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#define CYGNUM_HAL_INTERRUPT_RESERVED_106 106
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#define CYGNUM_HAL_INTERRUPT_RESERVED_107 107
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 108
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#define CYGNUM_HAL_INTERRUPT_RESERVED_109 109
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#define CYGNUM_HAL_INTERRUPT_RESERVED_110 110
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#define CYGNUM_HAL_INTERRUPT_RESERVED_111 111
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 112
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#define CYGNUM_HAL_INTERRUPT_RESERVED_113 113
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#define CYGNUM_HAL_INTERRUPT_RESERVED_114 114
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#define CYGNUM_HAL_INTERRUPT_RESERVED_115 115
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 116
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#define CYGNUM_HAL_INTERRUPT_RESERVED_117 117
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#define CYGNUM_HAL_INTERRUPT_RESERVED_118 118
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#define CYGNUM_HAL_INTERRUPT_RESERVED_119 119
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 120
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#define CYGNUM_HAL_INTERRUPT_RESERVED_121 121
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#define CYGNUM_HAL_INTERRUPT_RESERVED_122 122
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#define CYGNUM_HAL_INTERRUPT_RESERVED_123 123
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 123
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#define CYGNUM_HAL_ISR_COUNT (3+((CYGNUM_HAL_ISR_MAX+1)/4))
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// The vector used by the Real time clock
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5
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//--------------------------------------------------------------------------
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// Interrupt vector translation.
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#if !defined(HAL_TRANSLATE_VECTOR) && !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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| 300 |
|
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_index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \
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| 301 |
|
|
(_vector_) : \
|
| 302 |
|
|
(((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3))
|
| 303 |
|
|
|
| 304 |
|
|
#endif
|
| 305 |
|
|
|
| 306 |
|
|
//--------------------------------------------------------------------------
|
| 307 |
|
|
// MN10300 specific version of HAL_INTERRUPT_CONFIGURE
|
| 308 |
|
|
|
| 309 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
|
| 310 |
|
|
CYG_MACRO_START \
|
| 311 |
|
|
if( _vector_ >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 ) \
|
| 312 |
|
|
{ \
|
| 313 |
|
|
cyg_uint32 _v_ = _vector_; \
|
| 314 |
|
|
cyg_uint16 _val_ = 0; \
|
| 315 |
|
|
cyg_uint16 _reg_; \
|
| 316 |
|
|
\
|
| 317 |
|
|
/* adjust vector to bit offset in EXTMD */ \
|
| 318 |
|
|
_v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0; \
|
| 319 |
|
|
_v_ >>= 1; \
|
| 320 |
|
|
\
|
| 321 |
|
|
/* set bits according to requirements */ \
|
| 322 |
|
|
if( _up_ ) _val_ |= 1; \
|
| 323 |
|
|
if( !(_level_) ) _val_ |= 2; \
|
| 324 |
|
|
\
|
| 325 |
|
|
/* get EXTMD */ \
|
| 326 |
|
|
_reg_ = mn10300_interrupt_control[0x180>>1]; \
|
| 327 |
|
|
\
|
| 328 |
|
|
/* clear old value and set new */ \
|
| 329 |
|
|
_reg_ &= ~(3<<_v_); \
|
| 330 |
|
|
_reg_ |= _val_<<_v_; \
|
| 331 |
|
|
\
|
| 332 |
|
|
/* restore EXTMD */ \
|
| 333 |
|
|
mn10300_interrupt_control[0x180>>1] = _reg_; \
|
| 334 |
|
|
} \
|
| 335 |
|
|
CYG_MACRO_END
|
| 336 |
|
|
|
| 337 |
|
|
#define HAL_INTERRUPT_CONFIGURE_DEFINED
|
| 338 |
|
|
|
| 339 |
|
|
//--------------------------------------------------------------------------
|
| 340 |
|
|
// Timer control registers.
|
| 341 |
|
|
// On the mn103002 we use timers 4 and 5
|
| 342 |
|
|
|
| 343 |
|
|
#define TIMER4_CR 0x340010a0
|
| 344 |
|
|
#define TIMER4_BR 0x34001090
|
| 345 |
|
|
#define TIMER4_MD 0x34001080
|
| 346 |
|
|
|
| 347 |
|
|
#define TIMER5_CR 0x340010a2
|
| 348 |
|
|
#define TIMER5_BR 0x34001092
|
| 349 |
|
|
#define TIMER5_MD 0x34001082
|
| 350 |
|
|
|
| 351 |
|
|
#define TIMER_CR TIMER5_CR
|
| 352 |
|
|
#define TIMER_BR TIMER5_BR
|
| 353 |
|
|
#define TIMER_MD TIMER5_MD
|
| 354 |
|
|
|
| 355 |
|
|
#define TIMER0_MD 0x34001000
|
| 356 |
|
|
#define TIMER0_BR 0x34001010
|
| 357 |
|
|
#define TIMER0_CR 0x34001020
|
| 358 |
|
|
|
| 359 |
|
|
//--------------------------------------------------------------------------
|
| 360 |
|
|
// Clock control.
|
| 361 |
|
|
|
| 362 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
| 363 |
|
|
{ \
|
| 364 |
|
|
volatile cyg_uint16 *timer4_br = (cyg_uint16 *)TIMER4_BR; \
|
| 365 |
|
|
volatile cyg_uint8 *timer4_md = (cyg_uint8 *)TIMER4_MD; \
|
| 366 |
|
|
volatile cyg_uint16 *timer5_br = (cyg_uint16 *)TIMER5_BR; \
|
| 367 |
|
|
volatile cyg_uint8 *timer5_md = (cyg_uint8 *)TIMER5_MD; \
|
| 368 |
|
|
\
|
| 369 |
|
|
/* Set timers 4 and 5 into cascade mode */ \
|
| 370 |
|
|
\
|
| 371 |
|
|
*timer5_br = (_period_)>>16; \
|
| 372 |
|
|
\
|
| 373 |
|
|
*timer5_md = 0x40; \
|
| 374 |
|
|
*timer5_md = 0x83; \
|
| 375 |
|
|
\
|
| 376 |
|
|
*timer4_br = (_period_)&0x0000FFFF; \
|
| 377 |
|
|
\
|
| 378 |
|
|
*timer4_md = 0x40; \
|
| 379 |
|
|
*timer4_md = 0x80; \
|
| 380 |
|
|
}
|
| 381 |
|
|
|
| 382 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ )
|
| 383 |
|
|
|
| 384 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
| 385 |
|
|
{ \
|
| 386 |
|
|
volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR; \
|
| 387 |
|
|
volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR; \
|
| 388 |
|
|
\
|
| 389 |
|
|
cyg_uint16 t5; \
|
| 390 |
|
|
cyg_uint16 t4; \
|
| 391 |
|
|
\
|
| 392 |
|
|
/* Loop reading the two timers until we can read t5 twice */ \
|
| 393 |
|
|
/* with the same value. This avoids getting silly times if */ \
|
| 394 |
|
|
/* the timers carry between reading the two regs. */ \
|
| 395 |
|
|
do { \
|
| 396 |
|
|
t5 = *timer5_cr; \
|
| 397 |
|
|
t4 = *timer4_cr; \
|
| 398 |
|
|
} while( t5 != *timer5_cr ); \
|
| 399 |
|
|
\
|
| 400 |
|
|
*(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD - ((t5<<16) + t4); \
|
| 401 |
|
|
}
|
| 402 |
|
|
|
| 403 |
|
|
// FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since
|
| 404 |
|
|
// this means the HAL gets configured by kernel options even when the
|
| 405 |
|
|
// kernel is disabled!
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
//--------------------------------------------------------------------------
|
| 409 |
|
|
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
|
| 410 |
|
|
// End of var_intr.h
|
