| 1 |
786 |
skrzyp |
#ifndef CYGONCE_HAL_VAR_ARCH_H
|
| 2 |
|
|
#define CYGONCE_HAL_VAR_ARCH_H
|
| 3 |
|
|
|
| 4 |
|
|
//==========================================================================
|
| 5 |
|
|
//
|
| 6 |
|
|
// var_arch.h
|
| 7 |
|
|
//
|
| 8 |
|
|
// Architecture specific abstractions
|
| 9 |
|
|
//
|
| 10 |
|
|
//==========================================================================
|
| 11 |
|
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
| 12 |
|
|
// -------------------------------------------
|
| 13 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 14 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
| 15 |
|
|
//
|
| 16 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 17 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 18 |
|
|
// Software Foundation; either version 2 or (at your option) any later
|
| 19 |
|
|
// version.
|
| 20 |
|
|
//
|
| 21 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
| 22 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 23 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 24 |
|
|
// for more details.
|
| 25 |
|
|
//
|
| 26 |
|
|
// You should have received a copy of the GNU General Public License
|
| 27 |
|
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 28 |
|
|
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 29 |
|
|
//
|
| 30 |
|
|
// As a special exception, if other files instantiate templates or use
|
| 31 |
|
|
// macros or inline functions from this file, or you compile this file
|
| 32 |
|
|
// and link it with other works to produce a work based on this file,
|
| 33 |
|
|
// this file does not by itself cause the resulting work to be covered by
|
| 34 |
|
|
// the GNU General Public License. However the source code for this file
|
| 35 |
|
|
// must still be made available in accordance with section (3) of the GNU
|
| 36 |
|
|
// General Public License v2.
|
| 37 |
|
|
//
|
| 38 |
|
|
// This exception does not invalidate any other reasons why a work based
|
| 39 |
|
|
// on this file might be covered by the GNU General Public License.
|
| 40 |
|
|
// -------------------------------------------
|
| 41 |
|
|
// ####ECOSGPLCOPYRIGHTEND####
|
| 42 |
|
|
//==========================================================================
|
| 43 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 44 |
|
|
//
|
| 45 |
|
|
// Author(s): nickg
|
| 46 |
|
|
// Contributors: nickg, dmoseley
|
| 47 |
|
|
// Date: 1999-02-17
|
| 48 |
|
|
// Purpose: Define architecture abstractions
|
| 49 |
|
|
// Description: This file contains any extra or modified definitions for
|
| 50 |
|
|
// this variant of the architecture.
|
| 51 |
|
|
// Usage: #include <cyg/hal/var_arch.h>
|
| 52 |
|
|
//
|
| 53 |
|
|
//####DESCRIPTIONEND####
|
| 54 |
|
|
//
|
| 55 |
|
|
//==========================================================================
|
| 56 |
|
|
|
| 57 |
|
|
#include <pkgconf/hal.h>
|
| 58 |
|
|
#include <cyg/infra/cyg_type.h>
|
| 59 |
|
|
|
| 60 |
|
|
//--------------------------------------------------------------------------
|
| 61 |
|
|
// Processor Status word bitmasks
|
| 62 |
|
|
|
| 63 |
|
|
#define HAL_ARCH_AM33_PSW_nSL (1L << 16)
|
| 64 |
|
|
#define HAL_ARCH_AM33_PSW_ML (1L << 19)
|
| 65 |
|
|
#define HAL_ARCH_AM33_PSW_FE (1L << 20)
|
| 66 |
|
|
|
| 67 |
|
|
//--------------------------------------------------------------------------
|
| 68 |
|
|
// Processor saved states:
|
| 69 |
|
|
|
| 70 |
|
|
typedef struct HAL_SavedRegisters
|
| 71 |
|
|
{
|
| 72 |
|
|
// These are common to all saved states and are in the order
|
| 73 |
|
|
// stored and loaded by the movm instruction.
|
| 74 |
|
|
CYG_ADDRWORD vector; /* Vector number/dummy */
|
| 75 |
|
|
CYG_ADDRWORD lar; /* Loop address register */
|
| 76 |
|
|
CYG_ADDRWORD lir; /* Loop instruction register */
|
| 77 |
|
|
CYG_ADDRWORD mdr; /* Multiply/Divide register */
|
| 78 |
|
|
CYG_ADDRWORD a1;
|
| 79 |
|
|
CYG_ADDRWORD a0;
|
| 80 |
|
|
CYG_ADDRWORD d1;
|
| 81 |
|
|
CYG_ADDRWORD d0;
|
| 82 |
|
|
CYG_ADDRWORD a3;
|
| 83 |
|
|
CYG_ADDRWORD a2;
|
| 84 |
|
|
CYG_ADDRWORD d3;
|
| 85 |
|
|
CYG_ADDRWORD d2;
|
| 86 |
|
|
CYG_ADDRWORD mcvf; /* MAC overflow flag */
|
| 87 |
|
|
CYG_ADDRWORD mcrl; /* MAC register low */
|
| 88 |
|
|
CYG_ADDRWORD mcrh; /* MAC register high */
|
| 89 |
|
|
CYG_ADDRWORD mdrq; /* Fast multiply/divide register*/
|
| 90 |
|
|
CYG_ADDRWORD e1; /* extended registers */
|
| 91 |
|
|
CYG_ADDRWORD e0;
|
| 92 |
|
|
CYG_ADDRWORD e7;
|
| 93 |
|
|
CYG_ADDRWORD e6;
|
| 94 |
|
|
CYG_ADDRWORD e5;
|
| 95 |
|
|
CYG_ADDRWORD e4;
|
| 96 |
|
|
CYG_ADDRWORD e3;
|
| 97 |
|
|
CYG_ADDRWORD e2;
|
| 98 |
|
|
|
| 99 |
|
|
/* On interrupts the PC and PSW are pushed automatically by the */
|
| 100 |
|
|
/* CPU and SP is pushed for debugging reasons. On a thread switch */
|
| 101 |
|
|
/* the saved context is made to look the same. */
|
| 102 |
|
|
|
| 103 |
|
|
CYG_ADDRWORD sp; /* Saved copy of SP in some states */
|
| 104 |
|
|
CYG_ADDRWORD psw; /* Status word */
|
| 105 |
|
|
CYG_ADDRWORD pc; /* Program Counter */
|
| 106 |
|
|
|
| 107 |
|
|
} HAL_SavedRegisters;
|
| 108 |
|
|
|
| 109 |
|
|
//--------------------------------------------------------------------------
|
| 110 |
|
|
// Extra initialization for AM33 extended register set.
|
| 111 |
|
|
|
| 112 |
|
|
#define HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_) \
|
| 113 |
|
|
CYG_MACRO_START \
|
| 114 |
|
|
(_regs_)->e0 = (_id_)|0xeee0; \
|
| 115 |
|
|
(_regs_)->e1 = (_id_)|0xeee1; \
|
| 116 |
|
|
(_regs_)->e2 = (_id_)|0xeee2; \
|
| 117 |
|
|
(_regs_)->e3 = (_id_)|0xeee3; \
|
| 118 |
|
|
(_regs_)->e4 = (_id_)|0xeee4; \
|
| 119 |
|
|
(_regs_)->e5 = (_id_)|0xeee5; \
|
| 120 |
|
|
(_regs_)->e6 = (_id_)|0xeee6; \
|
| 121 |
|
|
(_regs_)->e7 = (_id_)|0xeee7; \
|
| 122 |
|
|
(_regs_)->mcrl = 0; \
|
| 123 |
|
|
(_regs_)->mcrh = 0; \
|
| 124 |
|
|
(_regs_)->mdrq = 0; \
|
| 125 |
|
|
(_regs_)->mcvf = 0; \
|
| 126 |
|
|
CYG_MACRO_END
|
| 127 |
|
|
|
| 128 |
|
|
//--------------------------------------------------------------------------
|
| 129 |
|
|
// The following macros copy the extra AM33 registers between a
|
| 130 |
|
|
// HAL_SavedRegisters structure and a GDB register dump.
|
| 131 |
|
|
// The CYGMON version should handle the SSP and USP and MDRQ registers.
|
| 132 |
|
|
|
| 133 |
|
|
#ifdef CYGPKG_CYGMON
|
| 134 |
|
|
#define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) am33_get_gdb_extra_registers( _regval_, _regs_ )
|
| 135 |
|
|
extern void am33_get_gdb_extra_registers(CYG_ADDRWORD *registers, HAL_SavedRegisters *regs);
|
| 136 |
|
|
#else // CYGPKG_CYGMON
|
| 137 |
|
|
#define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) \
|
| 138 |
|
|
CYG_MACRO_START \
|
| 139 |
|
|
(_regval_)[15] = (_regs_)->e0; \
|
| 140 |
|
|
(_regval_)[16] = (_regs_)->e1; \
|
| 141 |
|
|
(_regval_)[17] = (_regs_)->e2; \
|
| 142 |
|
|
(_regval_)[18] = (_regs_)->e3; \
|
| 143 |
|
|
(_regval_)[19] = (_regs_)->e4; \
|
| 144 |
|
|
(_regval_)[20] = (_regs_)->e5; \
|
| 145 |
|
|
(_regval_)[21] = (_regs_)->e6; \
|
| 146 |
|
|
(_regval_)[22] = (_regs_)->e7; \
|
| 147 |
|
|
\
|
| 148 |
|
|
(_regval_)[23] = (_regs_)->sp; \
|
| 149 |
|
|
(_regval_)[24] = (_regs_)->sp; \
|
| 150 |
|
|
(_regval_)[25] = (_regs_)->sp; \
|
| 151 |
|
|
\
|
| 152 |
|
|
(_regval_)[26] = (_regs_)->mcrh; \
|
| 153 |
|
|
(_regval_)[27] = (_regs_)->mcrl; \
|
| 154 |
|
|
(_regval_)[28] = (_regs_)->mcvf; \
|
| 155 |
|
|
CYG_MACRO_END
|
| 156 |
|
|
#endif // CYGPKG_CYGMON
|
| 157 |
|
|
|
| 158 |
|
|
#ifdef CYGPKG_CYGMON
|
| 159 |
|
|
#define HAL_SET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) am33_set_gdb_extra_registers( _regs_, _regval_ )
|
| 160 |
|
|
extern void am33_set_gdb_extra_registers(CYG_ADDRWORD *registers, HAL_SavedRegisters *regs);
|
| 161 |
|
|
#else // CYGPKG_CYGMON
|
| 162 |
|
|
#define HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ) \
|
| 163 |
|
|
CYG_MACRO_START \
|
| 164 |
|
|
(_regs_)->e0 = (_regval_)[15]; \
|
| 165 |
|
|
(_regs_)->e1 = (_regval_)[16]; \
|
| 166 |
|
|
(_regs_)->e2 = (_regval_)[17]; \
|
| 167 |
|
|
(_regs_)->e3 = (_regval_)[18]; \
|
| 168 |
|
|
(_regs_)->e4 = (_regval_)[19]; \
|
| 169 |
|
|
(_regs_)->e5 = (_regval_)[20]; \
|
| 170 |
|
|
(_regs_)->e6 = (_regval_)[21]; \
|
| 171 |
|
|
(_regs_)->e7 = (_regval_)[22]; \
|
| 172 |
|
|
\
|
| 173 |
|
|
(_regs_)->sp = (_regval_)[23]; \
|
| 174 |
|
|
(_regs_)->sp = (_regval_)[24]; \
|
| 175 |
|
|
(_regs_)->sp = (_regval_)[25]; \
|
| 176 |
|
|
\
|
| 177 |
|
|
(_regs_)->mcrh = (_regval_)[26]; \
|
| 178 |
|
|
(_regs_)->mcrl = (_regval_)[27]; \
|
| 179 |
|
|
(_regs_)->mcvf = (_regval_)[28]; \
|
| 180 |
|
|
CYG_MACRO_END
|
| 181 |
|
|
#endif // CYGPKG_CYGMON
|
| 182 |
|
|
|
| 183 |
|
|
//--------------------------------------------------------------------------
|
| 184 |
|
|
#endif // CYGONCE_HAL_VAR_ARCH_H
|
| 185 |
|
|
// End of var_arch.h
|
