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#ifndef CYGONCE_PLF_IO_H
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#define CYGONCE_PLF_IO_H
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//=============================================================================
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//
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// plf_io.h
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//
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// Platform specific IO support
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): dhowells
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// Contributors: dmoseley
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// Date: 2001-05-17
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// Purpose: ASB2305 platform IO support
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// Description:
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// Usage: #include <cyg/hal/plf_io.h>
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#ifndef __ASSEMBLER__
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#include <cyg/hal/hal_intr.h>
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#endif
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#ifdef __ASSEMBLER__
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#define HAL_REG_8(x) x
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#define HAL_REG_16(x) x
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#define HAL_REG_32(x) x
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#else
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#define HAL_REG_8(x) (volatile cyg_uint8*)(x)
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#define HAL_REG_16(x) (volatile cyg_uint16*)(x)
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#define HAL_REG_32(x) (volatile cyg_uint32*)(x)
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#endif
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# define CYGARC_UNCACHED_ADDRESS(x) ((x)|0x20000000)
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//-----------------------------------------------------------------------------
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/* ASB GPIO Registers */
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#define HAL_GPIO_BASE 0xDB000000
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#define HAL_GPIO_0_MODE_OFFSET 0x0000
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#define HAL_GPIO_0_IN_OFFSET 0x0004
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#define HAL_GPIO_0_OUT_OFFSET 0x0008
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#define HAL_GPIO_1_MODE_OFFSET 0x0100
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#define HAL_GPIO_1_IN_OFFSET 0x0104
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#define HAL_GPIO_1_OUT_OFFSET 0x0108
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#define HAL_GPIO_2_MODE_OFFSET 0x0200
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#define HAL_GPIO_2_IN_OFFSET 0x0204
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#define HAL_GPIO_2_OUT_OFFSET 0x0208
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#define HAL_GPIO_3_MODE_OFFSET 0x0300
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#define HAL_GPIO_3_IN_OFFSET 0x0304
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#define HAL_GPIO_3_OUT_OFFSET 0x0308
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#define HAL_GPIO_4_MODE_OFFSET 0x0400
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#define HAL_GPIO_4_IN_OFFSET 0x0404
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#define HAL_GPIO_4_OUT_OFFSET 0x0408
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#define HAL_GPIO_5_MODE_OFFSET 0x0500
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#define HAL_GPIO_5_IN_OFFSET 0x0504
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#define HAL_GPIO_5_OUT_OFFSET 0x0508
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#define HAL_GPIO_0_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_0_MODE_OFFSET)
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#define HAL_GPIO_0_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_0_IN_OFFSET)
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#define HAL_GPIO_0_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_0_OUT_OFFSET)
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#define HAL_GPIO_1_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_1_MODE_OFFSET)
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#define HAL_GPIO_1_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_1_IN_OFFSET)
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#define HAL_GPIO_1_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_1_OUT_OFFSET)
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#define HAL_GPIO_2_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_2_MODE_OFFSET)
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#define HAL_GPIO_2_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_2_IN_OFFSET)
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#define HAL_GPIO_2_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_2_OUT_OFFSET)
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#define HAL_GPIO_3_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_3_MODE_OFFSET)
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#define HAL_GPIO_3_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_3_IN_OFFSET)
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#define HAL_GPIO_3_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_3_OUT_OFFSET)
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#define HAL_GPIO_4_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_4_MODE_OFFSET)
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#define HAL_GPIO_4_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_4_IN_OFFSET)
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#define HAL_GPIO_4_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_4_OUT_OFFSET)
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#define HAL_GPIO_5_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_5_MODE_OFFSET)
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#define HAL_GPIO_5_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_5_IN_OFFSET)
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#define HAL_GPIO_5_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_5_OUT_OFFSET)
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//-----------------------------------------------------------------------------
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#define HAL_LED_ADDRESS 0xA6F90000
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#define HAL_GPIO_MODE_ALL_OUTPUT 0x5555
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#ifdef __ASSEMBLER__
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# include <cyg/hal/platform.inc>
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# define DEBUG_DISPLAY(hexdig) hal_diag_led hexdig
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# define DEBUG_DELAY() \
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mov 0x20000, d0; \
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0: sub 1, d0; \
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bne 0b; \
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nop
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#else
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extern cyg_uint8 cyg_hal_plf_led_val(CYG_WORD hexdig);
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# define DEBUG_DISPLAY(hexdig) HAL_WRITE_UINT8(HAL_LED_ADDRESS, cyg_hal_plf_led_val(hexdig))
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# define DEBUG_DELAY() \
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{ \
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volatile int i = 0x80000; \
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while (--i) ; \
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}
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#endif
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//-----------------------------------------------------------------------------
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// PCI access stuff
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// Compute address necessary to access PCI config space for the given
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// bus and device.
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#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
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(0x80000000 | ((__bus) << 16) | ((__devfn) << 8) | ((__offset) & ~3))
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// Read a value from the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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do { \
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if ((__bus)==0 && (__devfn)==0) { \
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HAL_READ_UINT8(0xBE040000+(__offset),(__val)); \
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} \
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else { \
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HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_READ_UINT8(0xBFFFFFFC + ((__offset)&3),(__val)); \
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} \
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} while(0)
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#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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do { \
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if ((__bus)==0 && (__devfn)==0) { \
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HAL_READ_UINT16(0xBE040000+(__offset),(__val)); \
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} \
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else { \
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HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_READ_UINT16(0xBFFFFFFC + ((__offset)&2),(__val)); \
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} \
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} while(0)
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#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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do { \
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if ((__bus)==0 && (__devfn)==0) { \
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HAL_READ_UINT32(0xBE040000+(__offset),(__val)); \
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} \
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else { \
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HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_READ_UINT32(0xBFFFFFFC,(__val)); \
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} \
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} while(0)
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// Write a value to the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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do { \
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if ((__bus)==0 && (__devfn)==0) { \
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HAL_WRITE_UINT8(0xBE040000+(__offset),(__val)); \
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} \
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else { \
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HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_WRITE_UINT8(0xBFFFFFFC + ((__offset)&3),(__val)); \
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} \
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} while(0)
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#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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do { \
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if ((__bus)==0 && (__devfn)==0) { \
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HAL_WRITE_UINT16(0xBE040000+(__offset),(__val)); \
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} \
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else { \
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HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_WRITE_UINT16(0xBFFFFFFC + ((__offset)&2),(__val)); \
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} \
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} while(0)
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#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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do { \
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if ((__bus)==0 && (__devfn)==0) { \
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HAL_WRITE_UINT32(0xBE040000+(__offset),(__val)); \
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} \
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else { \
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HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
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HAL_WRITE_UINT32(0xBFFFFFFC,(__val)); \
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} \
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} while(0)
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// Initialize the PCI bus.
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#define HAL_PCI_INIT() \
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do { \
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cyg_uint32 devfn; \
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cyg_uint16 word; \
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\
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/* we need to set up the bridge _now_ or we won't be able to access the */ \
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/* PCI config registers */ \
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HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
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word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY; \
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word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
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HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
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\
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HAL_PCI_CFG_WRITE_UINT16(0,0,CYG_PCI_CFG_STATUS, 0xF800); \
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HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_LATENCY_TIMER, 0x10); \
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HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_BAR_0, 0x80000000); \
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HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_INT_LINE, 1); \
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HAL_PCI_CFG_WRITE_UINT32(0,0,0x48, 0x98000000); \
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HAL_PCI_CFG_WRITE_UINT8 (0,0,0x41, 0x00); \
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HAL_PCI_CFG_WRITE_UINT8 (0,0,0x42, 0x01); \
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HAL_PCI_CFG_WRITE_UINT8 (0,0,0x44, 0x01); \
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HAL_PCI_CFG_WRITE_UINT32(0,0,0x50, 0x00000001); \
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| 243 |
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HAL_PCI_CFG_WRITE_UINT32(0,0,0x58, 0x00000002); \
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HAL_PCI_CFG_WRITE_UINT32(0,0,0x5C, 0x00000001); \
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| 245 |
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\
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/* we also need to set up the PCI-PCI bridge (no BIOS, you see) */ \
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devfn = 3<<3 | 0; \
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\
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| 249 |
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/* IO: 0x00010000-0x0001ffff */ \
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| 250 |
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HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_BASE, 0x01); \
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HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_BASE_UPPER16, 0x0001); \
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HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_LIMIT, 0xF1); \
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HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_LIMIT_UPPER16, 0x0001); \
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| 254 |
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\
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| 255 |
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HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
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| 256 |
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word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY; \
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| 257 |
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word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
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HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
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| 259 |
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HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_BASE, 0x1000); \
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HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_LIMIT, 0x1000); \
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} while(0)
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| 262 |
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| 263 |
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| 264 |
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//-----------------------------------------------------------------------------
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| 265 |
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// Resources
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// Map PCI device resources starting from these addresses in PCI space.
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#define HAL_PCI_ALLOC_BASE_MEMORY 0x10000000
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#define HAL_PCI_ALLOC_BASE_IO 0x1000
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// This is where the PCI spaces are mapped in the CPU's address space.
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#define HAL_PCI_PHYSICAL_MEMORY_BASE 0x80000000
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#define HAL_PCI_PHYSICAL_IO_BASE 0xBE000000
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// Translate the PCI interrupt requested by the device (INTA#, INTB#,
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| 276 |
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// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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| 277 |
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#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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| 278 |
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CYG_MACRO_START \
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| 279 |
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cyg_uint8 __req; \
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| 280 |
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HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
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| 281 |
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if (0 != __req) { \
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/* Interrupt assignment as 21285 sees them. (From */ \
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| 283 |
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/* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */ \
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| 284 |
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|
CYG_ADDRWORD __translation[4] = { \
|
| 285 |
|
|
CYGNUM_HAL_INTERRUPT_RESERVED_170, /* INTC# */ \
|
| 286 |
|
|
CYGNUM_HAL_INTERRUPT_RESERVED_169, /* INTB# */ \
|
| 287 |
|
|
CYGNUM_HAL_INTERRUPT_EXTERNAL_1, /* INTA# */ \
|
| 288 |
|
|
CYGNUM_HAL_INTERRUPT_RESERVED_171}; /* INTD# */ \
|
| 289 |
|
|
\
|
| 290 |
|
|
/* The PCI lines from the different slots are wired like this */ \
|
| 291 |
|
|
/* on the PCI backplane: */ \
|
| 292 |
|
|
/* pin6A pin7B pin7A pin8B */ \
|
| 293 |
|
|
/* System Slot INTA# INTB# INTC# INTD# */ \
|
| 294 |
|
|
/* I/O Slot 1 INTB# INTC# INTD# INTA# */ \
|
| 295 |
|
|
/* I/O Slot 2 INTC# INTD# INTA# INTB# */ \
|
| 296 |
|
|
/* I/O Slot 3 INTD# INTA# INTB# INTC# */ \
|
| 297 |
|
|
/* I/O Slot 4 INTA# INTB# INTC# INTD# */ \
|
| 298 |
|
|
/* */ \
|
| 299 |
|
|
/* (From PCI Development Backplane, 3.2.2 Interrupts) */ \
|
| 300 |
|
|
/* */ \
|
| 301 |
|
|
/* Devsel signals are wired to, resulting in device IDs: */ \
|
| 302 |
|
|
/* I/O Slot 1 AD19 / dev 8 [(8+1)&3 = 1] */ \
|
| 303 |
|
|
/* I/O Slot 2 AD18 / dev 7 [(7+1)&3 = 0] */ \
|
| 304 |
|
|
/* I/O Slot 3 AD17 / dev 6 [(6+1)&3 = 3] */ \
|
| 305 |
|
|
/* I/O Slot 4 AD16 / dev 5 [(5+1)&3 = 2] */ \
|
| 306 |
|
|
/* */ \
|
| 307 |
|
|
/* (From PCI Development Backplane, 3.2.1 General) */ \
|
| 308 |
|
|
/* */ \
|
| 309 |
|
|
/* The observant reader will notice that the array does not */ \
|
| 310 |
|
|
/* match the table of how interrupts are wired. The array */ \
|
| 311 |
|
|
/* does however match observed behavior of the hardware: */ \
|
| 312 |
|
|
/* */ \
|
| 313 |
|
|
/* Observed interrupts with an Intel ethernet card */ \
|
| 314 |
|
|
/* put in the slots in turn and set to generate interrupts: */ \
|
| 315 |
|
|
/* slot 1/intA# (dev 8): caused host INTB# */ \
|
| 316 |
|
|
/* slot 2/intA# (dev 7): caused host INTC# */ \
|
| 317 |
|
|
/* slot 3/intA# (dev 6): caused host INTD# */ \
|
| 318 |
|
|
/* slot 4/intA# (dev 5): caused host INTA# */ \
|
| 319 |
|
|
\
|
| 320 |
|
|
__vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
|
| 321 |
|
|
__valid = true; \
|
| 322 |
|
|
} else { \
|
| 323 |
|
|
/* Device will not generate interrupt requests. */ \
|
| 324 |
|
|
__valid = false; \
|
| 325 |
|
|
} \
|
| 326 |
|
|
CYG_MACRO_END
|
| 327 |
|
|
|
| 328 |
|
|
|
| 329 |
|
|
//-----------------------------------------------------------------------------
|
| 330 |
|
|
// Bus address translation macros
|
| 331 |
|
|
#define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr) \
|
| 332 |
|
|
CYG_MACRO_START \
|
| 333 |
|
|
(__bus_addr) = (CYG_ADDRESS)((cyg_uint32)(__cpu_addr)&~0x20000000); \
|
| 334 |
|
|
CYG_MACRO_END
|
| 335 |
|
|
|
| 336 |
|
|
#define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr) \
|
| 337 |
|
|
CYG_MACRO_START \
|
| 338 |
|
|
(__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr); \
|
| 339 |
|
|
CYG_MACRO_END
|
| 340 |
|
|
|
| 341 |
|
|
//-----------------------------------------------------------------------------
|
| 342 |
|
|
// end of plf_io.h
|
| 343 |
|
|
#endif // CYGONCE_PLF_IO_H
|
