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1 786 skrzyp
//==========================================================================
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//
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//      hal_arch.h
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//
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//      Architecture specific abstractions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####                                            
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// -------------------------------------------                              
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// This file is part of eCos, the Embedded Configurable Operating System.   
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under    
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// the terms of the GNU General Public License as published by the Free     
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// Software Foundation; either version 2 or (at your option) any later      
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// version.                                                                 
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT      
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
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// for more details.                                                        
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//
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// You should have received a copy of the GNU General Public License        
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// along with eCos; if not, write to the Free Software Foundation, Inc.,    
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
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//
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// As a special exception, if other files instantiate templates or use      
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// macros or inline functions from this file, or you compile this file      
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// and link it with other works to produce a work based on this file,       
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// this file does not by itself cause the resulting work to be covered by   
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// the GNU General Public License. However the source code for this file    
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// must still be made available in accordance with section (3) of the GNU   
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// General Public License v2.                                               
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//
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// This exception does not invalidate any other reasons why a work based    
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// on this file might be covered by the GNU General Public License.         
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// -------------------------------------------                              
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// ####ECOSGPLCOPYRIGHTEND####                                              
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    sfurman
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// Contributors: 
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// Date:         2003-01-17
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// Purpose:      Define architecture abstractions
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// Usage:        #include <cyg/hal/hal_arch.h>
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//              
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#ifndef CYGONCE_HAL_HAL_ARCH_H
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#define CYGONCE_HAL_HAL_ARCH_H
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// Include macros to access special-purpose registers (SPRs)
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#include <cyg/hal/spr_defs.h>
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#define CYG_HAL_OPENRISC_REG_SIZE 4
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#ifndef __ASSEMBLER__
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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//--------------------------------------------------------------------------
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// Processor saved states:
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// The layout of this structure is also defined in "arch.inc", for assembly
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// code. Do not change this without changing that (or vice versa).
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#define CYG_HAL_OPENRISC_REG CYG_WORD32
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typedef struct
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{
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    // These are common to all saved states
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    CYG_HAL_OPENRISC_REG    r[32];          // GPR regs
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    CYG_HAL_OPENRISC_REG    machi;          // High and low words of
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    CYG_HAL_OPENRISC_REG    maclo;          //   multiply/accumulate reg
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    // These are only saved for exceptions and interrupts
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    CYG_WORD32              vector;         /* Vector number            */
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    CYG_WORD32              sr;             /* Status Reg               */
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    CYG_HAL_OPENRISC_REG    pc;             /* Program Counter          */
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    // Saved only for exceptions, and not restored when continued:
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    // Effective address of instruction/data access that caused exception
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    CYG_HAL_OPENRISC_REG    eear;           /* Exception effective address reg */
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} HAL_SavedRegisters;
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//--------------------------------------------------------------------------
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//  Utilities
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// Move from architecture special register (SPR)
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#define MFSPR(_spr_)                                      \
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({  CYG_HAL_OPENRISC_REG _result_;                        \
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    asm volatile ("l.mfspr %0, r0, %1;"                   \
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        : "=r"(_result_)                                  \
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        : "K"(_spr_)                                      \
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    );                                                    \
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    _result_;})
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// Move data to architecture special registers (SPR)
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#define MTSPR(_spr_, _val_)                               \
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CYG_MACRO_START                                           \
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    CYG_HAL_OPENRISC_REG val = _val_;                     \
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    asm volatile ("l.mtspr r0, %0, %1;"                   \
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        :                                                 \
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        : "r"(val), "K"(_spr_)                            \
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    );                                                    \
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CYG_MACRO_END
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//--------------------------------------------------------------------------
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// Exception handling function.
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// This function is defined by the kernel according to this prototype. It is
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// invoked from the HAL to deal with any CPU exceptions that the HAL does
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// not want to deal with itself. It usually invokes the kernel's exception
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// delivery mechanism.
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externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
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119
//--------------------------------------------------------------------------
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// Bit manipulation macros
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122
externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
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externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
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125
#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
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// NOTE - Below can be optimized with l.ff1 instruction if that optional
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//        instruction is implemented in HW.  OR12k does not implement
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//        it at this time, however.
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#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
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132
//--------------------------------------------------------------------------
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// Context Initialization
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// Initialize the context of a thread.
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// Arguments:
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// _sparg_ name of variable containing current sp, will be written with new sp
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// _thread_ thread object address, passed as argument to entry point
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// _entry_ entry point address.
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// _id_ bit pattern used in initializing registers, for debugging.
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#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )                     \
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{                                                                                       \
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    int _i_;                                                                            \
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    register CYG_WORD _sp_ = ((CYG_WORD)_sparg_);                                       \
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    register HAL_SavedRegisters *_regs_;                                                \
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    _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\
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    _sp_ &= ~(CYGARC_ALIGNMENT);                                                        \
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    for( _i_ = 1; _i_ < 32; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_;                      \
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    (_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_);       /* SP = top of stack      */   \
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    (_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_);       /* FP = top of stack      */   \
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    (_regs_)->r[3] = (CYG_HAL_OPENRISC_REG)(_thread_);   /* R3 = arg1 = thread ptr */   \
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    (_regs_)->maclo = 0;                                 /* MACLO = 0              */   \
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    (_regs_)->machi = 0;                                 /* MACHI = 0              */   \
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    (_regs_)->sr = (SPR_SR_TEE|SPR_SR_IEE);              /* Interrupts enabled     */   \
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    (_regs_)->pc = (CYG_HAL_OPENRISC_REG)(_entry_);      /* PC = entry point       */   \
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    (_regs_)->r[9] = (CYG_HAL_OPENRISC_REG)(_entry_);    /* PC = entry point       */   \
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    _sparg_ = (CYG_ADDRESS)_regs_;                                                      \
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}
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161
//--------------------------------------------------------------------------
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// Context switch macros.
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164
// The arguments to these macros are *pointers* to locations where the
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// stack pointer of the thread is to be stored/retrieved, i.e. *not*
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// the value of the stack pointer itself.
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168
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
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externC void hal_thread_load_context( CYG_ADDRESS to )
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    __attribute__ ((noreturn));
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172
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_)                    \
173
        hal_thread_switch_context( (CYG_ADDRESS)_tspptr_,               \
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                                   (CYG_ADDRESS)_fspptr_);
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176
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_)                               \
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        hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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179
// Translate a stack pointer as saved by the thread context macros above into
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// a pointer to a HAL_SavedRegisters structure.
181
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )  \
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        (_regs_) = (HAL_SavedRegisters *)(_sp_)
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//--------------------------------------------------------------------------
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// Execution reorder barrier.
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// When optimizing the compiler can reorder code. In multithreaded systems
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// where the order of actions is vital, this can sometimes cause problems.
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// This macro may be inserted into places where reordering should not happen.
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// The "memory" keyword is potentially unnecessary, but it is harmless to
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// keep it.
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192
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
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194
//--------------------------------------------------------------------------
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// Breakpoint support
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// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
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//    occur if executed.
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// HAL_BREAKINST is the value of the breakpoint instruction and...
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// HAL_BREAKINST_SIZE is its size in bytes and...
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// HAL_BREAKINST_TYPE is its type.
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#define HAL_BREAKPOINT(_label_)                 \
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asm volatile (" .globl  " #_label_ ";"          \
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              #_label_ ":"                      \
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              " l.trap 1;"                      \
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    );
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#define HAL_BREAKINST           (0x21000001)    // l.trap 1 instruction
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210
#define HAL_BREAKINST_SIZE      4
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212
#define HAL_BREAKINST_TYPE      cyg_uint32
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//--------------------------------------------------------------------------
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// Thread register state manipulation for GDB support.
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// Default to a 32 bit register size for GDB register dumps.
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#ifndef CYG_HAL_GDB_REG
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#define CYG_HAL_GDB_REG CYG_WORD32
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#endif
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// Register layout expected by GDB
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typedef struct
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{
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    CYG_HAL_OPENRISC_REG    r[32];          // GPR regs
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    CYG_HAL_OPENRISC_REG    pc;             // Program Counter
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    CYG_HAL_OPENRISC_REG    sr;             // Supervisor/Status Reg
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} GDB_Registers;
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// Copy a set of registers from a HAL_SavedRegisters structure into a
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// GDB_Registers structure.
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#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ )              \
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    CYG_MACRO_START                                             \
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    GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_);        \
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    int _i_;                                                    \
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                                                                \
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    for( _i_ = 0; _i_ <  32; _i_++ ) {                          \
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        _gdb_->r[_i_] = (_regs_)->r[_i_];                       \
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    }                                                           \
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                                                                \
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    _gdb_->pc = (_regs_)->pc;                                   \
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    _gdb_->sr = (_regs_)->sr;                                   \
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    CYG_MACRO_END
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// Copy a set of registers from a GDB_Registers structure into a
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// HAL_SavedRegisters structure.
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#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ )             \
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    CYG_MACRO_START                                             \
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    GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_);        \
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    int _i_;                                                    \
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                                                                \
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    for( _i_ = 0; _i_ <  32; _i_++ )                            \
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        (_regs_)->r[_i_] = _gdb_->r[_i_];                       \
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                                                                \
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    (_regs_)->pc = _gdb_->pc;                                   \
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    (_regs_)->sr = _gdb_->sr;                                   \
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    CYG_MACRO_END
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//--------------------------------------------------------------------------
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// HAL setjmp
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// Note: These definitions are repeated in context.S. If changes are
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// required remember to update both sets.
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#define CYGARC_JMP_BUF_R1        0
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#define CYGARC_JMP_BUF_R2        1
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#define CYGARC_JMP_BUF_R9        2
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#define CYGARC_JMP_BUF_R10       3
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#define CYGARC_JMP_BUF_R12       4
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#define CYGARC_JMP_BUF_R14       5
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#define CYGARC_JMP_BUF_R16       6
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#define CYGARC_JMP_BUF_R18       7
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#define CYGARC_JMP_BUF_R20       8
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#define CYGARC_JMP_BUF_R22       9
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#define CYGARC_JMP_BUF_R24      10
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#define CYGARC_JMP_BUF_R26      11
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#define CYGARC_JMP_BUF_R28      12
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#define CYGARC_JMP_BUF_R30      13
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279
#define CYGARC_JMP_BUF_SIZE     14
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281
typedef CYG_HAL_OPENRISC_REG hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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283
externC int hal_setjmp(hal_jmp_buf env);
284
externC void hal_longjmp(hal_jmp_buf env, int val);
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286
//-------------------------------------------------------------------------
287
// Idle thread code.
288
// This macro is called in the idle thread loop, and gives the HAL the
289
// chance to run code when no threads are runnable. Typical idle
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// thread behaviour might be to halt the processor.
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292
externC void hal_idle_thread_action(cyg_uint32 loop_count);
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294
#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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296
//--------------------------------------------------------------------------
297
// Minimal and sensible stack sizes: the intention is that applications
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// will use these to provide a stack size in the first instance prior to
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// proper analysis.  Idle thread stack should be this big.
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301
// *** THESE ARE NOT INTENDED TO BE GUARANTEED SUFFICIENT STACK SIZES ***
302
// They are, however, enough to start programming.
303
// You might, for example, need to make your stacks larger if you have
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// large "auto" variables.
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306
// This is not a config option because it should not be adjusted except
307
// under "enough rope to hang yourself" sort of disclaimers.
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309
// Typical case stack frame size: return link + 10 caller-saved temporaries + 4 locals.
310
#define CYGNUM_HAL_STACK_FRAME_SIZE (15 * CYG_HAL_OPENRISC_REG_SIZE)
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312
// Stack needed for a context switch:
313
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (38 * 4)  // sizeof(HAL_SavedRegisters)
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315
// Interrupt + call to ISR, interrupt_end() and the DSR
316
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2*CYGNUM_HAL_STACK_FRAME_SIZE) 
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318
// We define a minimum stack size as the minimum any thread could ever
319
// legitimately get away with. We can throw asserts if users ask for less
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// than this. Allow enough for three interrupt sources - clock, serial and
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// one other
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323
// If interrupts are segregated onto their own stack...
324
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK 
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326
// An interrupt stack which is large enough for all possible interrupt
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// conditions (and only used for that purpose) exists.  "User" stacks
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// can therefore be much smaller
329
// NOTE - interrupt stack sizes can be smaller if we don't allow interrupts
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//         to nest.
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332
# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
333
         ((3 * 5)*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE)
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335
#else
336
 
337
// No separate interrupt stack exists.  Make sure all threads contain
338
// a stack sufficiently large
339
# define CYGNUM_HAL_STACK_SIZE_MINIMUM                  \
340
        (( 3*CYGNUM_HAL_STACK_INTERRUPT_SIZE) +         \
341
         (25*CYGNUM_HAL_STACK_FRAME_SIZE))
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#endif
343
 
344
// Now make a reasonable choice for a typical thread size. Pluck figures
345
// from thin air and say 40 call frames
346
#define CYGNUM_HAL_STACK_SIZE_TYPICAL                \
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        (CYGNUM_HAL_STACK_SIZE_MINIMUM +             \
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         40 * (CYGNUM_HAL_STACK_FRAME_SIZE))
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350
#endif /* __ASSEMBLER__ */
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352
//--------------------------------------------------------------------------
353
// Macros for switching context between two eCos instances (jump from
354
// code in ROM to code in RAM or vice versa).
355
// These are NOP's in the case of OpenRISC.
356
#define CYGARC_HAL_SAVE_GP()
357
#define CYGARC_HAL_RESTORE_GP()
358
 
359
//--------------------------------------------------------------------------
360
// Macro for finding return address of current function
361
#define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \
362
  asm volatile ( "l.ori %0,r9,0;" : "=r" (_x_) )
363
 
364
#define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_)
365
 
366
//--------------------------------------------------------------------------
367
#endif // CYGONCE_HAL_HAL_ARCH_H
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// End of hal_arch.h

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