| 1 |
786 |
skrzyp |
#ifndef CYGONCE_HAL_CACHE_H
|
| 2 |
|
|
#define CYGONCE_HAL_CACHE_H
|
| 3 |
|
|
|
| 4 |
|
|
//=============================================================================
|
| 5 |
|
|
//
|
| 6 |
|
|
// hal_cache.h
|
| 7 |
|
|
//
|
| 8 |
|
|
// HAL cache control API
|
| 9 |
|
|
//
|
| 10 |
|
|
//=============================================================================
|
| 11 |
|
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
| 12 |
|
|
// -------------------------------------------
|
| 13 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 14 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
| 15 |
|
|
//
|
| 16 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 17 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 18 |
|
|
// Software Foundation; either version 2 or (at your option) any later
|
| 19 |
|
|
// version.
|
| 20 |
|
|
//
|
| 21 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
| 22 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 23 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 24 |
|
|
// for more details.
|
| 25 |
|
|
//
|
| 26 |
|
|
// You should have received a copy of the GNU General Public License
|
| 27 |
|
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 28 |
|
|
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 29 |
|
|
//
|
| 30 |
|
|
// As a special exception, if other files instantiate templates or use
|
| 31 |
|
|
// macros or inline functions from this file, or you compile this file
|
| 32 |
|
|
// and link it with other works to produce a work based on this file,
|
| 33 |
|
|
// this file does not by itself cause the resulting work to be covered by
|
| 34 |
|
|
// the GNU General Public License. However the source code for this file
|
| 35 |
|
|
// must still be made available in accordance with section (3) of the GNU
|
| 36 |
|
|
// General Public License v2.
|
| 37 |
|
|
//
|
| 38 |
|
|
// This exception does not invalidate any other reasons why a work based
|
| 39 |
|
|
// on this file might be covered by the GNU General Public License.
|
| 40 |
|
|
// -------------------------------------------
|
| 41 |
|
|
// ####ECOSGPLCOPYRIGHTEND####
|
| 42 |
|
|
//=============================================================================
|
| 43 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 44 |
|
|
//
|
| 45 |
|
|
// Author(s): Scott Furman
|
| 46 |
|
|
// Contributors:
|
| 47 |
|
|
// Date: 2003-02-08
|
| 48 |
|
|
// Purpose: Cache control API
|
| 49 |
|
|
// Description: The macros defined here provide the HAL APIs for handling
|
| 50 |
|
|
// cache control operations.
|
| 51 |
|
|
// Usage:
|
| 52 |
|
|
// #include <cyg/hal/hal_cache.h>
|
| 53 |
|
|
// ...
|
| 54 |
|
|
//
|
| 55 |
|
|
//
|
| 56 |
|
|
//####DESCRIPTIONEND####
|
| 57 |
|
|
//
|
| 58 |
|
|
//=============================================================================
|
| 59 |
|
|
|
| 60 |
|
|
//-----------------------------------------------------------------------------
|
| 61 |
|
|
// Cache dimensions.
|
| 62 |
|
|
// These really should be defined in var_cache.h. If they are not, then provide
|
| 63 |
|
|
// a set of numbers that are typical of many variants.
|
| 64 |
|
|
|
| 65 |
|
|
#ifndef HAL_DCACHE_SIZE
|
| 66 |
|
|
|
| 67 |
|
|
// Data cache
|
| 68 |
|
|
#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
|
| 69 |
|
|
#define HAL_DCACHE_LINE_SIZE 16 // Bytes in a data cache line
|
| 70 |
|
|
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
|
| 71 |
|
|
|
| 72 |
|
|
// Instruction cache
|
| 73 |
|
|
#define HAL_ICACHE_SIZE 8192 // Size of cache in bytes
|
| 74 |
|
|
#define HAL_ICACHE_LINE_SIZE 16 // Bytes in a cache line
|
| 75 |
|
|
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
|
| 76 |
|
|
|
| 77 |
|
|
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
|
| 78 |
|
|
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
|
| 79 |
|
|
|
| 80 |
|
|
#endif
|
| 81 |
|
|
|
| 82 |
|
|
#ifndef __ASSEMBLER__
|
| 83 |
|
|
|
| 84 |
|
|
#include <cyg/hal/hal_arch.h>
|
| 85 |
|
|
|
| 86 |
|
|
//-----------------------------------------------------------------------------
|
| 87 |
|
|
// Global control of data cache
|
| 88 |
|
|
|
| 89 |
|
|
// Enable the data cache
|
| 90 |
|
|
#define HAL_DCACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_DCE)
|
| 91 |
|
|
|
| 92 |
|
|
// Disable the data cache
|
| 93 |
|
|
#define HAL_DCACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_DCE)
|
| 94 |
|
|
|
| 95 |
|
|
// Enable or disable the data cache, depending on argument, which is required
|
| 96 |
|
|
// to be 0 or 1.
|
| 97 |
|
|
#define HAL_SET_DCACHE_ENABLED(enable) \
|
| 98 |
|
|
MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_DCE & -(enable)))
|
| 99 |
|
|
|
| 100 |
|
|
// Invalidate the entire data cache
|
| 101 |
|
|
#define HAL_DCACHE_INVALIDATE_ALL() \
|
| 102 |
|
|
CYG_MACRO_START \
|
| 103 |
|
|
int cache_enabled, addr; \
|
| 104 |
|
|
\
|
| 105 |
|
|
/* Save current cache mode (disabled/enabled) */ \
|
| 106 |
|
|
HAL_DCACHE_IS_ENABLED(cache_enabled); \
|
| 107 |
|
|
\
|
| 108 |
|
|
/* Disable cache, so that invalidation ignores cache tags */\
|
| 109 |
|
|
HAL_DCACHE_DISABLE(); \
|
| 110 |
|
|
addr = HAL_DCACHE_SIZE; \
|
| 111 |
|
|
do { \
|
| 112 |
|
|
MTSPR(SPR_DCBIR, addr); \
|
| 113 |
|
|
addr -= HAL_DCACHE_LINE_SIZE; \
|
| 114 |
|
|
} while (addr > 0); \
|
| 115 |
|
|
\
|
| 116 |
|
|
/* Re-enable cache if it was enabled on entry */ \
|
| 117 |
|
|
HAL_SET_DCACHE_ENABLED(cache_enabled); \
|
| 118 |
|
|
CYG_MACRO_END
|
| 119 |
|
|
|
| 120 |
|
|
// Synchronize the contents of the cache with memory.
|
| 121 |
|
|
// (Unnecessary on OR12K, since cache is write-through.)
|
| 122 |
|
|
#define HAL_DCACHE_SYNC() \
|
| 123 |
|
|
CYG_MACRO_START \
|
| 124 |
|
|
CYG_MACRO_END
|
| 125 |
|
|
|
| 126 |
|
|
// Query the state (enabled/disabled) of the data cache
|
| 127 |
|
|
#define HAL_DCACHE_IS_ENABLED(_state_) \
|
| 128 |
|
|
CYG_MACRO_START \
|
| 129 |
|
|
(_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_DCE)); \
|
| 130 |
|
|
CYG_MACRO_END
|
| 131 |
|
|
|
| 132 |
|
|
// Load the contents of the given address range into the data cache
|
| 133 |
|
|
// and then lock the cache so that it stays there.
|
| 134 |
|
|
|
| 135 |
|
|
// The OpenRISC architecture defines these operations, but no
|
| 136 |
|
|
// implementation supports them yet.
|
| 137 |
|
|
|
| 138 |
|
|
//#define HAL_DCACHE_LOCK(_base_, _size_)
|
| 139 |
|
|
|
| 140 |
|
|
// Undo a previous lock operation
|
| 141 |
|
|
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
|
| 142 |
|
|
|
| 143 |
|
|
// Unlock entire cache
|
| 144 |
|
|
//#define HAL_DCACHE_UNLOCK_ALL()
|
| 145 |
|
|
|
| 146 |
|
|
|
| 147 |
|
|
//-----------------------------------------------------------------------------
|
| 148 |
|
|
// Data cache line control
|
| 149 |
|
|
|
| 150 |
|
|
// Write dirty cache lines to memory and invalidate the cache entries
|
| 151 |
|
|
// for the given address range.
|
| 152 |
|
|
// OR12k has write-through cache, so no flushing of writes to memory
|
| 153 |
|
|
// are necessary.
|
| 154 |
|
|
#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
|
| 155 |
|
|
HAL_DCACHE_INVALIDATE(_base_, _size_)
|
| 156 |
|
|
|
| 157 |
|
|
// Invalidate cache lines in the given range without writing to memory.
|
| 158 |
|
|
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
|
| 159 |
|
|
CYG_MACRO_START \
|
| 160 |
|
|
int addr; \
|
| 161 |
|
|
int end = _base_ + _size_; \
|
| 162 |
|
|
for (addr = end; addr >= _base_; addr -= HAL_DCACHE_LINE_SIZE) { \
|
| 163 |
|
|
MTSPR(SPR_DCBIR, addr); \
|
| 164 |
|
|
} \
|
| 165 |
|
|
CYG_MACRO_END
|
| 166 |
|
|
|
| 167 |
|
|
// Write dirty cache lines to memory for the given address range.
|
| 168 |
|
|
// OR12k has write-through cache, so this is a NOP
|
| 169 |
|
|
#define HAL_DCACHE_STORE( _base_ , _size_ )
|
| 170 |
|
|
|
| 171 |
|
|
// Preread the given range into the cache with the intention of reading
|
| 172 |
|
|
// from it later.
|
| 173 |
|
|
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
|
| 174 |
|
|
|
| 175 |
|
|
// Preread the given range into the cache with the intention of writing
|
| 176 |
|
|
// to it later.
|
| 177 |
|
|
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
|
| 178 |
|
|
|
| 179 |
|
|
// Allocate and zero the cache lines associated with the given range.
|
| 180 |
|
|
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
|
| 181 |
|
|
|
| 182 |
|
|
//-----------------------------------------------------------------------------
|
| 183 |
|
|
// Global control of Instruction cache
|
| 184 |
|
|
|
| 185 |
|
|
// Enable the instruction cache
|
| 186 |
|
|
#define HAL_ICACHE_ENABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) | SPR_SR_ICE)
|
| 187 |
|
|
|
| 188 |
|
|
// Disable the instruction cache
|
| 189 |
|
|
#define HAL_ICACHE_DISABLE() MTSPR(SPR_SR, MFSPR(SPR_SR) & ~SPR_SR_ICE)
|
| 190 |
|
|
|
| 191 |
|
|
// Enable or disable the data cache, depending on argument, which must
|
| 192 |
|
|
// be 0 or 1.
|
| 193 |
|
|
#define HAL_SET_ICACHE_ENABLED(enable) \
|
| 194 |
|
|
MTSPR(SPR_SR, MFSPR(SPR_SR) | (SPR_SR_ICE & -(enable)))
|
| 195 |
|
|
|
| 196 |
|
|
// Invalidate the entire instruction cache
|
| 197 |
|
|
#define HAL_ICACHE_INVALIDATE_ALL() \
|
| 198 |
|
|
CYG_MACRO_START \
|
| 199 |
|
|
int cache_enabled, addr; \
|
| 200 |
|
|
\
|
| 201 |
|
|
/* Save current cache mode (disabled/enabled) */ \
|
| 202 |
|
|
HAL_ICACHE_IS_ENABLED(cache_enabled); \
|
| 203 |
|
|
\
|
| 204 |
|
|
/* Disable cache, so that invalidation ignores cache tags */\
|
| 205 |
|
|
HAL_ICACHE_DISABLE(); \
|
| 206 |
|
|
addr = HAL_ICACHE_SIZE; \
|
| 207 |
|
|
do { \
|
| 208 |
|
|
MTSPR(SPR_ICBIR, addr); \
|
| 209 |
|
|
addr -= HAL_ICACHE_LINE_SIZE; \
|
| 210 |
|
|
} while (addr > 0); \
|
| 211 |
|
|
\
|
| 212 |
|
|
/* Re-enable cache if it was enabled on entry */ \
|
| 213 |
|
|
HAL_SET_ICACHE_ENABLED(cache_enabled); \
|
| 214 |
|
|
CYG_MACRO_END
|
| 215 |
|
|
|
| 216 |
|
|
// Synchronize the contents of the cache with memory.
|
| 217 |
|
|
#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
|
| 218 |
|
|
|
| 219 |
|
|
// Query the state of the instruction cache
|
| 220 |
|
|
#define HAL_ICACHE_IS_ENABLED(_state_) \
|
| 221 |
|
|
CYG_MACRO_START \
|
| 222 |
|
|
(_state_) = (1 - !(MFSPR(SPR_SR) & SPR_SR_ICE)); \
|
| 223 |
|
|
CYG_MACRO_END
|
| 224 |
|
|
|
| 225 |
|
|
|
| 226 |
|
|
// Load the contents of the given address range into the instruction cache
|
| 227 |
|
|
// and then lock the cache so that it stays there.
|
| 228 |
|
|
|
| 229 |
|
|
// The OpenRISC architecture defines these operations, but no
|
| 230 |
|
|
// implementation supports them yet.
|
| 231 |
|
|
|
| 232 |
|
|
//#define HAL_ICACHE_LOCK(_base_, _size_)
|
| 233 |
|
|
|
| 234 |
|
|
// Undo a previous lock operation
|
| 235 |
|
|
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
|
| 236 |
|
|
|
| 237 |
|
|
// Unlock entire cache
|
| 238 |
|
|
//#define HAL_ICACHE_UNLOCK_ALL()
|
| 239 |
|
|
|
| 240 |
|
|
#endif /* __ASSEMBLER__ */
|
| 241 |
|
|
|
| 242 |
|
|
#endif // ifndef CYGONCE_HAL_CACHE_H
|
| 243 |
|
|
// End of hal_cache.h
|
