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786 |
skrzyp |
# ====================================================================
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#
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# hal_openrisc_orpsoc.cdl
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#
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# OpenRISC Reference Platform (ORP) HAL package configuration data
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#
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# ====================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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# ====================================================================
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######DESCRIPTIONBEGIN####
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#
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# Author(s): sfurman
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# Contributors:
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# Date: 2003-01-20
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#
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#####DESCRIPTIONEND####
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#
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# ====================================================================
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cdl_package CYGPKG_HAL_OPENRISC_ORPSOC {
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display "OpenRISC System-on-Chip"
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parent CYGPKG_HAL_OPENRISC
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include_dir cyg/hal
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hardware
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description "
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The ORPSoC HAL package should be used when targetting the
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OpenRISC Reference Platform."
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compile hal_diag.c hal_aux.c
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implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
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791 |
skrzyp |
implements CYGINT_HAL_DEBUG_GDB_STUBS
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implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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786 |
skrzyp |
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define_proc {
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puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H "
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puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "
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}
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791 |
skrzyp |
cdl_component CYG_HAL_STARTUP {
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display "Startup type"
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flavor data
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legal_values {"RAM" "ROM" "JTAG"}
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default_value {"JTAG"}
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no_define
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define -file system.h CYG_HAL_STARTUP
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description "
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Selects whether code initially runs from ROM or RAM. In the case of ROM startup,
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it's possible for the code to be copied into RAM and executed there."
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}
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cdl_component CYGHWR_MEMORY_LAYOUT {
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display "Memory layout"
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flavor data
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no_define
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calculated { CYG_HAL_STARTUP == "ROM" ? "openrisc_orpsoc_rom" : \
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"openrisc_orpsoc_ram" }
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cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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display "Memory layout linker script fragment"
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flavor data
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no_define
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define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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calculated { CYG_HAL_STARTUP == "ROM" ? "" : \
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"" }
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}
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cdl_option CYGHWR_MEMORY_LAYOUT_H {
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display "Memory layout header file"
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flavor data
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no_define
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define -file system.h CYGHWR_MEMORY_LAYOUT_H
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calculated { CYG_HAL_STARTUP == "ROM" ? "" : \
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"" }
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}
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}
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# Real-time clock/counter specifics
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cdl_component CYGNUM_HAL_RTC_CONSTANTS {
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display "Real-time clock constants."
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flavor none
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cdl_option CYGNUM_HAL_RTC_NUMERATOR {
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display "Real-time clock numerator"
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flavor data
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default_value 1000000000
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}
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cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
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display "Real-time clock denominator"
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flavor data
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default_value 100
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}
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cdl_option CYGNUM_HAL_RTC_PERIOD {
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display "Real-time clock period"
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flavor data
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default_value {CYGHWR_HAL_OPENRISC_CPU_FREQ * 1000000 / CYGNUM_HAL_RTC_DENOMINATOR}
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description "
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The tick timer facility is used
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to drive the eCos kernel RTC. The count register
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increments at the CPU clock speed. By default, 100 Hz"
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}
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}
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cdl_component CYGBLD_GLOBAL_OPTIONS {
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display "Global build options"
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flavor none
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description "
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Global build options including control over
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compiler flags, linker flags and choice of toolchain."
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parent CYGPKG_NONE
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cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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display "Global command prefix"
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flavor data
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no_define
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default_value { "or32-elf" }
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description "
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This option specifies the command prefix used when
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invoking the build tools."
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}
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cdl_option CYGBLD_GLOBAL_CFLAGS {
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display "Global compiler flags"
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flavor data
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no_define
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default_value { CYGBLD_GLOBAL_WARNFLAGS .
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"-g -O2 -fno-omit-frame-pointer -fno-rtti -fno-exceptions " .
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(CYGHWR_MUL_IMPLEMENTED ? "-mhard-mul " : "-msoft-mul ") .
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(CYGHWR_DIV_IMPLEMENTED ? "-mhard-div " : "-msoft-div ") .
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838 |
skrzyp |
(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") .
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(CYGHWR_BRANCH_SLOT_IMPLEMENTED ? "" : "-mno-branch-delay " ) }
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791 |
skrzyp |
description "
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This option controls the global compiler flags which
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are used to compile all packages by
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default. Individual packages may define
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options which override these global flags."
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}
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cdl_option CYGBLD_GLOBAL_LDFLAGS {
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display "Global linker flags"
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flavor data
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no_define
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default_value { "-g -O2 -nostdlib -Wl,--gc-sections -Wl,-static " .
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(CYGHWR_MUL_IMPLEMENTED ? "-mhard-mul " : "-msoft-mul ") .
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(CYGHWR_DIV_IMPLEMENTED ? "-mhard-div " : "-msoft-div ") .
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839 |
skrzyp |
(CYGHWR_FPU_IMPLEMENTED ? "-mhard-float " : "-msoft-float ") .
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(CYGHWR_BRANCH_SLOT_IMPLEMENTED ? "" : "-mno-branch-delay " ) }
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791 |
skrzyp |
description "
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This option controls the global linker flags. Individual
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packages may define options which override these global flags."
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}
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}
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cdl_option CYGBLD_BUILD_GDB_STUBS {
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display "Build GDB stub ROM image"
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default_value 0
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parent CYGBLD_GLOBAL_OPTIONS
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requires { CYG_HAL_STARTUP == "ROM" }
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requires CYGSEM_HAL_ROM_MONITOR
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requires CYGBLD_BUILD_COMMON_GDB_STUBS
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requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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no_define
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description "
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This option enables the building of the GDB stubs for the
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board. The common HAL controls takes care of most of the
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build process, but the final conversion from ELF image to
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binary data is handled by the platform CDL, allowing
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relocation of the data if necessary."
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make -priority 320 {
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/bin/gdb_module.bin : /bin/gdb_module.img
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$(OBJCOPY) -O binary $< $@
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}
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}
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cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
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display "Number of breakpoints supported by the HAL."
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flavor data
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default_value 25
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description "
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This option determines the number of breakpoints supported by the HAL."
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}
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cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
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display "Work with a ROM monitor"
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flavor bool
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default_value { CYG_HAL_STARTUP == "RAM" ? 1 : 0 }
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parent CYGPKG_HAL_ROM_MONITOR
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requires { CYG_HAL_STARTUP == "RAM" }
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description "
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Allow coexistence with ROM monitor (CygMon or GDB stubs) by
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only initializing interrupt vectors on startup, thus leaving
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exception handling to the ROM monitor."
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}
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cdl_option CYGSEM_HAL_ROM_MONITOR {
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display "Behave as a ROM monitor"
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flavor bool
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default_value 0
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parent CYGPKG_HAL_ROM_MONITOR
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requires { CYG_HAL_STARTUP == "ROM" }
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description "
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Enable this option if this program is to be used as a ROM monitor,
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i.e. applications will be loaded into RAM on the board, and this
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ROM monitor may process exceptions or interrupts generated from the
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application. This enables features such as utilizing a separate
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interrupt stack when exceptions are generated."
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}
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| 247 |
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| 248 |
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cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
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display "Redboot HAL options"
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flavor none
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no_define
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parent CYGPKG_REDBOOT
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active_if CYGPKG_REDBOOT
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description "
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| 255 |
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This option lists the target's requirements for a valid Redboot
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configuration."
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cdl_option CYGBLD_BUILD_REDBOOT_BIN {
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| 259 |
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display "Build Redboot ROM binary image"
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| 260 |
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active_if CYGBLD_BUILD_REDBOOT
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default_value 1
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| 262 |
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no_define
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| 263 |
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description "This option enables the conversion of the Redboot ELF
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| 264 |
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image to a binary image suitable for ROM programming."
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| 265 |
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| 266 |
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compile -library=libextras.a
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| 267 |
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make -priority 325 {
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/bin/redboot.srec : /bin/redboot.elf
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| 270 |
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$(OBJCOPY) --strip-all $< $(@:.srec=.img)
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| 271 |
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$(OBJCOPY) -O srec $< $@
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| 272 |
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}
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| 273 |
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}
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| 274 |
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}
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| 275 |
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| 276 |
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cdl_option CYGHWR_HAL_OPENRISC_CPU_FREQ {
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| 277 |
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display "CPU frequency"
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| 278 |
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flavor data
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| 279 |
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legal_values 0 to 1000000
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| 280 |
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default_value 50
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| 281 |
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description "
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| 282 |
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This option contains the frequency of the CPU in MegaHertz.
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| 283 |
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Choose the frequency to match the processor you have. This
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may affect thing like serial device, interval clock and
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memory access speed settings."
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| 286 |
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}
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| 287 |
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|
| 288 |
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cdl_option CYGHWR_MUL_IMPLEMENTED {
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| 289 |
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display "Hardware multiplier implemented"
|
| 290 |
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flavor bool
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| 291 |
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default_value 1
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| 292 |
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description "
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| 293 |
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Select this option only if hardware multiplier is
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implemented."
|
| 295 |
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}
|
| 296 |
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| 297 |
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cdl_option CYGHWR_DIV_IMPLEMENTED {
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| 298 |
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display "Hardware divisor implemented"
|
| 299 |
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flavor bool
|
| 300 |
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default_value 1
|
| 301 |
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description "
|
| 302 |
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Select this option only if hardware division is
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| 303 |
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implemented."
|
| 304 |
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}
|
| 305 |
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|
| 306 |
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cdl_option CYGHWR_FPU_IMPLEMENTED {
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| 307 |
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display "Hardware FPU implemented"
|
| 308 |
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flavor bool
|
| 309 |
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default_value 0
|
| 310 |
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description "
|
| 311 |
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Select this option only if FPU is implemented."
|
| 312 |
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}
|
| 313 |
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|
| 314 |
838 |
skrzyp |
cdl_option CYGHWR_BRANCH_SLOT_IMPLEMENTED {
|
| 315 |
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display "Branch slot implemented"
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| 316 |
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flavor bool
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| 317 |
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default_value 1
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| 318 |
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description "
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| 319 |
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Select this option if your implementation of OpenRISC
|
| 320 |
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has branch slot."
|
| 321 |
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}
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| 322 |
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| 323 |
791 |
skrzyp |
cdl_component CYGHWR_ICACHE_IMPLEMENTED {
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| 324 |
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display "Instruction cache implemented"
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| 325 |
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flavor bool
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| 326 |
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default_value 1
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| 327 |
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description "
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| 328 |
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Select this option only if instruction cache is
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| 329 |
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implemented."
|
| 330 |
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| 331 |
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cdl_option CYGHWR_ICACHE_SIZE {
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| 332 |
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display "Size of instruction cache"
|
| 333 |
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flavor data
|
| 334 |
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legal_values 0x1000 0x2000 0x4000 0x8000
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| 335 |
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default_value 0x2000
|
| 336 |
|
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description "
|
| 337 |
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Size of the instruction cache. Default is 8kB."
|
| 338 |
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}
|
| 339 |
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}
|
| 340 |
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|
| 341 |
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cdl_component CYGHWR_DCACHE_IMPLEMENTED {
|
| 342 |
|
|
display "Data cache implemented"
|
| 343 |
|
|
flavor bool
|
| 344 |
|
|
default_value 1
|
| 345 |
|
|
description "
|
| 346 |
|
|
Select this option only if data cache is
|
| 347 |
|
|
implemented."
|
| 348 |
|
|
|
| 349 |
|
|
cdl_option CYGHWR_DCACHE_SIZE {
|
| 350 |
|
|
display "Size of data cache"
|
| 351 |
|
|
active_if CYGHWR_DCACHE_IMPLEMENTED
|
| 352 |
|
|
flavor data
|
| 353 |
|
|
legal_values 0x200 0x1000 0x2000 0x4000 0x8000
|
| 354 |
|
|
default_value 0x1000
|
| 355 |
|
|
description "
|
| 356 |
|
|
Size of the data cache. Default is 4kB."
|
| 357 |
|
|
}
|
| 358 |
|
|
|
| 359 |
|
|
cdl_option CYGHWR_DCACHE_MODE {
|
| 360 |
|
|
display "DATA cache mode"
|
| 361 |
|
|
flavor data
|
| 362 |
|
|
legal_values { "WRITETHROUGH" "WRITEBACK" }
|
| 363 |
|
|
default_value { "WRITETHROUGH" }
|
| 364 |
|
|
description "
|
| 365 |
|
|
Speficy synthesized cache."
|
| 366 |
|
|
}
|
| 367 |
|
|
}
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
|
|
|
| 371 |
|
|
cdl_option CYGHWR_RAM_SIZE {
|
| 372 |
|
|
display "Size of RAM memory"
|
| 373 |
|
|
flavor data
|
| 374 |
|
|
default_value 0x2000000
|
| 375 |
|
|
description "
|
| 376 |
|
|
Size of RAM memory. This value is used to generate linker script.
|
| 377 |
|
|
Default is 32MB."
|
| 378 |
|
|
}
|
| 379 |
|
|
|
| 380 |
|
|
cdl_option CYGHWR_ROM_SIZE {
|
| 381 |
|
|
display "Size of ROM memory"
|
| 382 |
|
|
flavor data
|
| 383 |
|
|
default_value 0x40000
|
| 384 |
|
|
description "
|
| 385 |
|
|
Size of ROM memory. This value is used to generate linker script.
|
| 386 |
|
|
Default is 256kB."
|
| 387 |
|
|
}
|
| 388 |
|
|
|
| 389 |
786 |
skrzyp |
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
|
| 390 |
|
|
display "Diagnostic serial port baud rate"
|
| 391 |
|
|
flavor data
|
| 392 |
|
|
legal_values 9600 19200 38400 57600 115200 230400 460800 921600
|
| 393 |
|
|
default_value 115200
|
| 394 |
|
|
description "
|
| 395 |
|
|
This option selects the baud rate used for the diagnostic console.
|
| 396 |
|
|
Note: this should match the value chosen for the GDB port if the
|
| 397 |
|
|
diagnostic and GDB port are the same.
|
| 398 |
|
|
Note: very high baud rates are useful during simulation."
|
| 399 |
|
|
}
|
| 400 |
|
|
|
| 401 |
|
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
|
| 402 |
|
|
display "GDB serial port baud rate"
|
| 403 |
|
|
flavor data
|
| 404 |
|
|
legal_values 9600 19200 38400 57600 115200 230400 460800 921600
|
| 405 |
|
|
default_value 115200
|
| 406 |
|
|
description "
|
| 407 |
|
|
This option controls the baud rate used for the GDB connection.
|
| 408 |
|
|
Note: very high baud rates are useful during simulation."
|
| 409 |
|
|
}
|
| 410 |
|
|
|
| 411 |
|
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
|
| 412 |
|
|
display "Number of communication channels on the board"
|
| 413 |
|
|
flavor data
|
| 414 |
|
|
default_value 1
|
| 415 |
|
|
}
|
| 416 |
|
|
|
| 417 |
|
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
|
| 418 |
|
|
display "Debug serial port"
|
| 419 |
|
|
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
|
| 420 |
|
|
flavor data
|
| 421 |
|
|
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
|
| 422 |
|
|
default_value 0
|
| 423 |
|
|
description "
|
| 424 |
|
|
The ORP platform has at least one serial port, but it can potentially have several.
|
| 425 |
|
|
This option chooses which port will be used to connect to a host
|
| 426 |
|
|
running GDB."
|
| 427 |
|
|
}
|
| 428 |
|
|
|
| 429 |
|
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
|
| 430 |
|
|
display "Diagnostic serial port"
|
| 431 |
|
|
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
|
| 432 |
|
|
flavor data
|
| 433 |
|
|
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
|
| 434 |
|
|
default_value 0
|
| 435 |
|
|
description "
|
| 436 |
|
|
The ORP platform has at least one serial port, but it can potentially have several.
|
| 437 |
|
|
This option chooses which port will be used for diagnostic output."
|
| 438 |
|
|
}
|
| 439 |
|
|
|
| 440 |
|
|
define_proc {
|
| 441 |
|
|
puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE 0"
|
| 442 |
|
|
puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE 0xF00"
|
| 443 |
|
|
}
|
| 444 |
|
|
}
|
| 445 |
|
|
|
| 446 |
|
|
# EOF hal_openrisc_orpsoc.cdl
|
