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skrzyp |
#ifndef CYGONCE_HAL_INTR_H
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#define CYGONCE_HAL_INTR_H
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//==========================================================================
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//
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// hal_intr.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jskov,
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// jlarmour
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// Date: 1999-02-19
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock.
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//
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// Usage:
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// #include <cyg/hal/hal_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h> // types
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#include <cyg/hal/ppc_regs.h> // register definitions
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#include <cyg/hal/var_intr.h> // variant extensions
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//--------------------------------------------------------------------------
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// PowerPC exception vectors. These correspond to VSRs and are the values
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// to use for HAL_VSR_GET/SET
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#define CYGNUM_HAL_VECTOR_RESERVED_0 0
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#define CYGNUM_HAL_VECTOR_RESET 1
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#define CYGNUM_HAL_VECTOR_MACHINE_CHECK 2
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#define CYGNUM_HAL_VECTOR_DSI 3
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#define CYGNUM_HAL_VECTOR_ISI 4
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#define CYGNUM_HAL_VECTOR_INTERRUPT 5
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#define CYGNUM_HAL_VECTOR_ALIGNMENT 6
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#define CYGNUM_HAL_VECTOR_PROGRAM 7
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#define CYGNUM_HAL_VECTOR_FP_UNAVAILABLE 8
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#define CYGNUM_HAL_VECTOR_DECREMENTER 9
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#define CYGNUM_HAL_VECTOR_RESERVED_A 10
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#define CYGNUM_HAL_VECTOR_RESERVED_B 11
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#define CYGNUM_HAL_VECTOR_SYSTEM_CALL 12
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#define CYGNUM_HAL_VECTOR_TRACE 13
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#define CYGNUM_HAL_VECTOR_FP_ASSIST 14
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#ifdef CYGHWR_HAL_POWERPC_BOOK_E
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// Additional exceptions on Book E CPUs. The numbers here do not
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// necessarily correspond to the IVOR register number for the
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// exception, but they must correspond to the table position in the
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// rom_vectors table defined in vectors.S.
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#define CYGNUM_HAL_VECTOR_RESERVED_F 15
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#define CYGNUM_HAL_VECTOR_CRITICAL_INPUT 16
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#define CYGNUM_HAL_VECTOR_AP_UNAVAILABLE 17
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#define CYGNUM_HAL_VECTOR_FIT 18
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#define CYGNUM_HAL_VECTOR_WATCHDOG 19
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#define CYGNUM_HAL_VECTOR_DTLB_MISS 20
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#define CYGNUM_HAL_VECTOR_ITLB_MISS 21
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#define CYGNUM_HAL_VECTOR_DEBUG 22
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#define CYGNUM_HAL_VECTOR_SPE_UNAVAILABLE 23
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#define CYGNUM_HAL_VECTOR_SPE_FP_DATA 24
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#define CYGNUM_HAL_VECTOR_SPE_FP_ROUND 25
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#ifndef CYGNUM_HAL_VSR_MAX
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#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_SPE_FP_ROUND
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#endif
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#endif
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#define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_RESERVED_0
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#ifndef CYGNUM_HAL_VSR_MAX
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# define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_FP_ASSIST
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#endif
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#define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 )
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#ifndef CYG_VECTOR_IS_INTERRUPT
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# define CYG_VECTOR_IS_INTERRUPT(v) \
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(CYGNUM_HAL_VECTOR_INTERRUPT == (v) \
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|| CYGNUM_HAL_VECTOR_DECREMENTER == (v))
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#endif
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// The decoded interrupts.
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// Define decrementer as the first interrupt since it is guaranteed to
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// be defined on all PowerPCs. External may expand into several interrupts
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// depending on interrupt controller capabilities.
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#ifndef CYGHWR_HAL_POWERPC_BOOK_E
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#define CYGNUM_HAL_INTERRUPT_DECREMENTER 0
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL 1
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#else
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// For Book E processors, in addition the the decrementer, there are
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// also a fixed interval timer and a watchdog which can generate
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// asynchronous interrupts.
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#define CYGNUM_HAL_INTERRUPT_DECREMENTER 0
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#define CYGNUM_HAL_INTERRUPT_INTERVAL 1
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#define CYGNUM_HAL_INTERRUPT_WATCHDOG 2
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#define CYGNUM_HAL_INTERRUPT_EXTERNAL 3
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#endif
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#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER
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#ifndef CYGNUM_HAL_ISR_MAX
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTERNAL
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#endif
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#define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX + 1 )
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#ifndef CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
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// Exception vectors. These are the values used when passed out to an
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// external exception handler using cyg_hal_deliver_exception()
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#define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
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#define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK
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#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI
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#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI
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#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_ALIGNMENT
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#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
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#define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A
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#define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B
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#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
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#define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE
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#define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST
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#ifdef CYGHWR_HAL_POWERPC_BOOK_E
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#define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F
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#define CYGNUM_HAL_EXCEPTION_CRITICAL_INPUT CYGNUM_HAL_VECTOR_CRITICAL_INPUT
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#define CYGNUM_HAL_EXCEPTION_AP_UNAVAILABLE CYGNUM_HAL_VECTOR_AP_UNAVAILABLE
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#define CYGNUM_HAL_EXCEPTION_FIT CYGNUM_HAL_VECTOR_FIT
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#define CYGNUM_HAL_EXCEPTION_WATCHDOG CYGNUM_HAL_VECTOR_WATCHDOG
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#define CYGNUM_HAL_EXCEPTION_DTLB_MISS CYGNUM_HAL_VECTOR_DTLB_MISS
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#define CYGNUM_HAL_EXCEPTION_ITLB_MISS CYGNUM_HAL_VECTOR_ITLB_MISS
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#define CYGNUM_HAL_EXCEPTION_DEBUG CYGNUM_HAL_VECTOR_DEBUG
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#define CYGNUM_HAL_EXCEPTION_SPE_UNAVAILABLE CYGNUM_HAL_VECTOR_SPE_UNAVAILABLE
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#define CYGNUM_HAL_EXCEPTION_SPE_FP_DATA CYGNUM_HAL_VECTOR_SPE_FP_DATA
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#define CYGNUM_HAL_EXCEPTION_SPE_FP_ROUND CYGNUM_HAL_VECTOR_SPE_FP_ROUND
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#endif
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0
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#ifndef CYGNUM_HAL_EXCEPTION_MAX
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#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
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#endif
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#define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
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#endif // CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
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#ifndef CYGHWR_HAL_POWERPC_BOOK_E
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// FIXME: This is still rather ugly. Should probably be made variant
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// specific using a decode_hal_exception macro or somesuch.
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// decoded exception vectors
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#define CYGNUM_HAL_EXCEPTION_TRAP (-1)
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#define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION (-2)
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#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION (-3)
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#define CYGNUM_HAL_EXCEPTION_FPU (-4)
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#undef CYGNUM_HAL_EXCEPTION_MIN
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_FPU
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#endif
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#define CYGNUM_HAL_EXCEPTION_COUNT \
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( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
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//--------------------------------------------------------------------------
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// Static data used by HAL
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// ISR tables
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externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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// VSR table
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externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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//--------------------------------------------------------------------------
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// Default ISRs
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// The #define is used to test whether this routine exists, and to allow
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// us to call it.
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externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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externC cyg_uint32 hal_default_decrementer_isr(CYG_ADDRWORD vector,
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CYG_ADDRWORD data);
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#define HAL_DEFAULT_ISR hal_default_isr
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//--------------------------------------------------------------------------
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// Interrupt state storage
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typedef cyg_uint32 CYG_INTERRUPT_STATE;
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//--------------------------------------------------------------------------
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// Interrupt control macros
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#if !defined(CYGHWR_HAL_POWERPC_BOOK_E)
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#define CYGARC_REG_MSR_INTBITS CYGARC_REG_MSR_EE
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#else
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#define CYGARC_REG_MSR_INTBITS (CYGARC_REG_MSR_EE|CYGARC_REG_MSR_CE)
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#endif
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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cyg_uint32 tmp1 = ~CYGARC_REG_MSR_INTBITS; \
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cyg_uint32 tmp2; \
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asm volatile ( \
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"mfmsr %0;" \
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"mr %2,%0;" \
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"and %2,%2,%1;" \
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"mtmsr %2;" \
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: "=r"(_old_), "+r" (tmp1), "=r" (tmp2)); \
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CYG_MACRO_END
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#define HAL_ENABLE_INTERRUPTS() \
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CYG_MACRO_START \
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cyg_uint32 tmp1; \
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cyg_uint32 tmp2 = CYGARC_REG_MSR_INTBITS; \
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asm volatile ( \
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"mfmsr %0;" \
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"or %0,%0,%1;" \
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"mtmsr %0;" \
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: "=r" (tmp1), "+r" (tmp2)); \
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CYG_MACRO_END
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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cyg_uint32 tmp1; \
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cyg_uint32 tmp2 = ~CYGARC_REG_MSR_INTBITS; \
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asm volatile ( \
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"mfmsr %0;" \
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"and %0,%0,%1;" \
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"not %1,%1;" \
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"and %1,%1,%2;" \
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"or %0,%0,%1;" \
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"mtmsr %0;" \
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: "=&r" (tmp1), "+r" (tmp2) \
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: "r" (_old_)); \
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CYG_MACRO_END
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#define HAL_QUERY_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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cyg_uint32 tmp = CYGARC_REG_MSR_INTBITS; \
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asm volatile ( \
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"mfmsr %0;" \
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"and %0,%0,%1;" \
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: "=&r"(_old_) \
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: "r" (tmp)); \
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CYG_MACRO_END
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//--------------------------------------------------------------------------
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// Machine check manipulation
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#define HAL_DISABLE_MACHINE_CHECK(_old_) \
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CYG_MACRO_START \
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cyg_uint32 tmp1, tmp2; \
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asm volatile ( \
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"mfmsr %0;" \
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| 304 |
|
|
"mr %2,%0;" \
|
| 305 |
|
|
"li %1,0;" \
|
| 306 |
|
|
"rlwimi %2,%1,0,19,19;" \
|
| 307 |
|
|
"mtmsr %2;" \
|
| 308 |
|
|
: "=r"(_old_), "=r" (tmp1), "=r" (tmp2)); \
|
| 309 |
|
|
CYG_MACRO_END
|
| 310 |
|
|
|
| 311 |
|
|
#define HAL_ENABLE_MACHINE_CHECK() \
|
| 312 |
|
|
CYG_MACRO_START \
|
| 313 |
|
|
cyg_uint32 tmp1, tmp2; \
|
| 314 |
|
|
asm volatile ( \
|
| 315 |
|
|
"mfmsr %0;" \
|
| 316 |
|
|
"lis %1,%1,0x0001;" \
|
| 317 |
|
|
"rlwimi %0,%1,0,19,19;" \
|
| 318 |
|
|
"mtmsr %0;" \
|
| 319 |
|
|
: "=r" (tmp1), "=r" (tmp2)); \
|
| 320 |
|
|
CYG_MACRO_END
|
| 321 |
|
|
|
| 322 |
|
|
#define HAL_QUERY_MACHINE_CHECK(_old_) \
|
| 323 |
|
|
CYG_MACRO_START \
|
| 324 |
|
|
cyg_uint32 tmp; \
|
| 325 |
|
|
asm volatile ( \
|
| 326 |
|
|
"mfmsr %0;" \
|
| 327 |
|
|
"lis %1,0x0001;" \
|
| 328 |
|
|
"and %0,%0,%1;" \
|
| 329 |
|
|
: "=&r"(_old_), "=r" (tmp)); \
|
| 330 |
|
|
CYG_MACRO_END
|
| 331 |
|
|
|
| 332 |
|
|
//--------------------------------------------------------------------------
|
| 333 |
|
|
// Vector translation.
|
| 334 |
|
|
|
| 335 |
|
|
#ifndef HAL_TRANSLATE_VECTOR
|
| 336 |
|
|
// Basic PowerPC configuration only has two vectors; decrementer and
|
| 337 |
|
|
// external. Isr tables/chaining use same vector decoder.
|
| 338 |
|
|
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
|
| 339 |
|
|
(_index_) = (_vector_)
|
| 340 |
|
|
#endif
|
| 341 |
|
|
|
| 342 |
|
|
//--------------------------------------------------------------------------
|
| 343 |
|
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
|
| 344 |
|
|
|
| 345 |
|
|
externC void hal_interrupt_stack_call_pending_DSRs(void);
|
| 346 |
|
|
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
|
| 347 |
|
|
hal_interrupt_stack_call_pending_DSRs()
|
| 348 |
|
|
|
| 349 |
|
|
// these are offered solely for stack usage testing
|
| 350 |
|
|
// if they are not defined, then there is no interrupt stack.
|
| 351 |
|
|
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
|
| 352 |
|
|
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
|
| 353 |
|
|
// use them to declare these extern however you want:
|
| 354 |
|
|
// extern char HAL_INTERRUPT_STACK_BASE[];
|
| 355 |
|
|
// extern char HAL_INTERRUPT_STACK_TOP[];
|
| 356 |
|
|
// is recommended
|
| 357 |
|
|
#endif
|
| 358 |
|
|
|
| 359 |
|
|
//--------------------------------------------------------------------------
|
| 360 |
|
|
// Interrupt and VSR attachment macros
|
| 361 |
|
|
|
| 362 |
|
|
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
|
| 363 |
|
|
CYG_MACRO_START \
|
| 364 |
|
|
cyg_uint32 _index_; \
|
| 365 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 366 |
|
|
\
|
| 367 |
|
|
if((hal_interrupt_handlers[_index_] \
|
| 368 |
|
|
== (CYG_ADDRESS)hal_default_decrementer_isr) \
|
| 369 |
|
|
|| (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \
|
| 370 |
|
|
(_state_) = 0; \
|
| 371 |
|
|
else \
|
| 372 |
|
|
(_state_) = 1; \
|
| 373 |
|
|
CYG_MACRO_END
|
| 374 |
|
|
|
| 375 |
|
|
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
|
| 376 |
|
|
CYG_MACRO_START \
|
| 377 |
|
|
cyg_uint32 _index_; \
|
| 378 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 379 |
|
|
\
|
| 380 |
|
|
if((hal_interrupt_handlers[_index_] \
|
| 381 |
|
|
== (CYG_ADDRESS)hal_default_decrementer_isr) \
|
| 382 |
|
|
|| (hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr)) \
|
| 383 |
|
|
{ \
|
| 384 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
|
| 385 |
|
|
hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
|
| 386 |
|
|
hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
|
| 387 |
|
|
} \
|
| 388 |
|
|
CYG_MACRO_END
|
| 389 |
|
|
|
| 390 |
|
|
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
|
| 391 |
|
|
CYG_MACRO_START \
|
| 392 |
|
|
cyg_uint32 _index_; \
|
| 393 |
|
|
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
|
| 394 |
|
|
\
|
| 395 |
|
|
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
|
| 396 |
|
|
{ \
|
| 397 |
|
|
if (CYGNUM_HAL_INTERRUPT_DECREMENTER == (_vector_)) \
|
| 398 |
|
|
hal_interrupt_handlers[_index_] = \
|
| 399 |
|
|
(CYG_ADDRESS)hal_default_decrementer_isr; \
|
| 400 |
|
|
else \
|
| 401 |
|
|
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
|
| 402 |
|
|
hal_interrupt_data[_index_] = 0; \
|
| 403 |
|
|
hal_interrupt_objects[_index_] = 0; \
|
| 404 |
|
|
} \
|
| 405 |
|
|
CYG_MACRO_END
|
| 406 |
|
|
|
| 407 |
|
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
|
| 408 |
|
|
*(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
|
| 409 |
|
|
|
| 410 |
|
|
|
| 411 |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
|
| 412 |
|
|
CYG_MACRO_START \
|
| 413 |
|
|
if( _poldvsr_ != NULL ) \
|
| 414 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
|
| 415 |
|
|
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
|
| 416 |
|
|
CYG_MACRO_END
|
| 417 |
|
|
|
| 418 |
|
|
// This is an ugly name, but what it means is: grab the VSR back to eCos
|
| 419 |
|
|
// internal handling, or if you like, the default handler. But if
|
| 420 |
|
|
// cooperating with GDB and CygMon, the default behaviour is to pass most
|
| 421 |
|
|
// exceptions to CygMon. This macro undoes that so that eCos handles the
|
| 422 |
|
|
// exception. So use it with care.
|
| 423 |
|
|
externC void cyg_hal_default_interrupt_vsr( void );
|
| 424 |
|
|
externC void cyg_hal_default_exception_vsr( void );
|
| 425 |
|
|
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \
|
| 426 |
|
|
CYG_MACRO_START \
|
| 427 |
|
|
if( (void*)_poldvsr_ != (void*)NULL ) \
|
| 428 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
|
| 429 |
|
|
hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
|
| 430 |
|
|
? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
|
| 431 |
|
|
: (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
|
| 432 |
|
|
CYG_MACRO_END
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
|
| 436 |
|
|
|
| 437 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ )
|
| 438 |
|
|
|
| 439 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ )
|
| 440 |
|
|
|
| 441 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
|
| 442 |
|
|
|
| 443 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
|
| 444 |
|
|
|
| 445 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
|
| 446 |
|
|
|
| 447 |
|
|
#endif
|
| 448 |
|
|
|
| 449 |
|
|
//--------------------------------------------------------------------------
|
| 450 |
|
|
// Clock control
|
| 451 |
|
|
|
| 452 |
|
|
#ifndef CYGHWR_HAL_CLOCK_DEFINED
|
| 453 |
|
|
// Note: variant or platform allowed to override these definitions
|
| 454 |
|
|
|
| 455 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
| 456 |
|
|
CYG_MACRO_START \
|
| 457 |
|
|
asm volatile ( \
|
| 458 |
|
|
"mtdec %0;" \
|
| 459 |
|
|
: \
|
| 460 |
|
|
: "r"(_period_) \
|
| 461 |
|
|
); \
|
| 462 |
|
|
CYG_MACRO_END
|
| 463 |
|
|
|
| 464 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
|
| 465 |
|
|
CYG_MACRO_START \
|
| 466 |
|
|
cyg_uint32 tmp; \
|
| 467 |
|
|
asm volatile ( \
|
| 468 |
|
|
"mfdec %0;" \
|
| 469 |
|
|
"add. %0,%0,%1;" \
|
| 470 |
|
|
"bgt 1f;" \
|
| 471 |
|
|
"mr %0,%1;" \
|
| 472 |
|
|
"1: mtdec %0;" \
|
| 473 |
|
|
: "=&r" (tmp) \
|
| 474 |
|
|
: "r"(_period_) \
|
| 475 |
|
|
: "cc" \
|
| 476 |
|
|
); \
|
| 477 |
|
|
CYG_MACRO_END
|
| 478 |
|
|
|
| 479 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
| 480 |
|
|
CYG_MACRO_START \
|
| 481 |
|
|
register cyg_uint32 result; \
|
| 482 |
|
|
asm volatile( \
|
| 483 |
|
|
"mfdec %0;" \
|
| 484 |
|
|
: "=r"(result) \
|
| 485 |
|
|
); \
|
| 486 |
|
|
*(_pvalue_) = CYGNUM_HAL_RTC_PERIOD-result; \
|
| 487 |
|
|
CYG_MACRO_END
|
| 488 |
|
|
|
| 489 |
|
|
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
|
| 490 |
|
|
#define HAL_CLOCK_LATENCY( _pvalue_ ) \
|
| 491 |
|
|
CYG_MACRO_START \
|
| 492 |
|
|
register cyg_int32 result; \
|
| 493 |
|
|
asm volatile( \
|
| 494 |
|
|
"mfdec %0;" \
|
| 495 |
|
|
: "=r"(result) \
|
| 496 |
|
|
); \
|
| 497 |
|
|
/* Pending DEC interrupts cannot be discarded. If dec is */ \
|
| 498 |
|
|
/* positive it''s because a DEC interrupt occured while */ \
|
| 499 |
|
|
/* eCos was getting ready to run. Just return 0 in that */ \
|
| 500 |
|
|
/* case. */ \
|
| 501 |
|
|
if (result > 0) \
|
| 502 |
|
|
result = 0; \
|
| 503 |
|
|
*(_pvalue_) = -result; \
|
| 504 |
|
|
CYG_MACRO_END
|
| 505 |
|
|
#endif
|
| 506 |
|
|
|
| 507 |
|
|
#ifndef HAL_DELAY_US
|
| 508 |
|
|
externC void hal_delay_us(int);
|
| 509 |
|
|
#define HAL_DELAY_US(n) hal_delay_us(n)
|
| 510 |
|
|
#endif
|
| 511 |
|
|
|
| 512 |
|
|
// The vector used by the Real time clock
|
| 513 |
|
|
#ifndef CYGNUM_HAL_INTERRUPT_RTC
|
| 514 |
|
|
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_DECREMENTER
|
| 515 |
|
|
#endif // CYGNUM_HAL_INTERRUPT_RTC
|
| 516 |
|
|
|
| 517 |
|
|
#endif // CYGHWR_HAL_CLOCK_DEFINED
|
| 518 |
|
|
|
| 519 |
|
|
//--------------------------------------------------------------------------
|
| 520 |
|
|
// Variant functions
|
| 521 |
|
|
externC void hal_variant_IRQ_init(void);
|
| 522 |
|
|
|
| 523 |
|
|
//--------------------------------------------------------------------------
|
| 524 |
|
|
#endif // ifndef CYGONCE_HAL_INTR_H
|
| 525 |
|
|
// End of hal_intr.h
|
