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##=============================================================================
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##
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## cme555.S
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##
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## CME555 board hardware setup
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): Bob Koninckx
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## Contributors:Bob Koninckx
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## Date: 2001-12-15
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## Purpose: cme555 board hardware setup
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## Description: This file contains any code needed to initialize the
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## hardware on a cme555 mpc555 board.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#include
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#------------------------------------------------------------------------------
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.globl hal_hardware_init
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hal_hardware_init:
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#if defined(CYGPKG_HAL_POWERPC_CME555) && defined(CYGPKG_HAL_POWERPC_MPC5xx)
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lwi r3, CYGARC_REG_IMM_BASE # Base address of control registers
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// Configure external interrupt pins as General purpose I/O. They do not
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// have pull-up resistors on the CME555. Add to that that IRQ0 triggers
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// a non-maskable reset of the board ... This one gave me nightmares ...
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lwi r4, 0x00000800
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stw r4, (CYGARC_REG_IMM_SIUMCR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0xff88
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stw r4, (CYGARC_REG_IMM_SYPCR-CYGARC_REG_IMM_BASE)(r3)
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// Memory map
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// CS0 configuration
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// Base address 0x400000, no burst support, 32 bit wide data port
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// Valid addresses till 0x43FFFF, no wait states
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lwi r4, 0x00400003
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stw r4, (CYGARC_REG_IMM_BR0-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0xfff80002
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stw r4, (CYGARC_REG_IMM_OR0-CYGARC_REG_IMM_BASE)(r3)
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// CS1 configuration
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// Base address 0x800000, no burst support, 32 bit wide data port
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// Valid adresses till 0x87FFFF, three wait states for access time 70ns
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lwi r4, 0x00800003
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stw r4, (CYGARC_REG_IMM_BR1-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0xfff80032
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stw r4, (CYGARC_REG_IMM_OR1-CYGARC_REG_IMM_BASE)(r3)
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// CS2 configuration
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// Base address 0xc00000, no burst support, 32 bit wide data port
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// Valid adresses till 0xc7FFFF, maximum wait states
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lwi r4, 0x00c00003
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stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0xfff800f2
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stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
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// CS3 configuration
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// works for keypad/LCD
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// maximum wait states
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lwi r4, 0x01000403
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stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0xfffe0ff1
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stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
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// And some other configuration registers
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#if defined(CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP)
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lwi r4, 1
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#else
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lwi r4, 0
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#endif
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stw r4, (CYGARC_REG_IMM_DMBR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0
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stw r4, (CYGARC_REG_IMM_DMOR-CYGARC_REG_IMM_BASE)(r3)
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// Limb mode enable, TMBCLK = BUS/16, RTCCLK = Crystal / 16
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// generate 40 MHz bus clock
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lwi r4, 0x3010000
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stw r4, (CYGARC_REG_IMM_SCCR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0x900000
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stw r4, (CYGARC_REG_IMM_PLPRCR-CYGARC_REG_IMM_BASE)(r3)
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// Enable the time base and set the freeze flag
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lwi r4, 0x03
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sth r4, (CYGARC_REG_IMM_TBSCR-CYGARC_REG_IMM_BASE)(r3)
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// Unlock the RTC register set
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lwi r4, 0x55ccaa33
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stw r4, (CYGARC_REG_IMM_RTCSCK-CYGARC_REG_IMM_BASE)(r3)
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// RTC is clocked by 4MHz crystal, set the freeze flag
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lwi r4, 0x12
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sth r4, (CYGARC_REG_IMM_RTCSC-CYGARC_REG_IMM_BASE)(r3)
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// Set the freeze flag for the Periodic interrupt timer
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lwi r4, 0x02
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sth r4, (CYGARC_REG_IMM_PISCR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0x00
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lwi r5, (CYGARC_REG_IMM_DPTMCR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r4, 0xffa0
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lwi r5, (CYGARC_REG_IMM_RAMBAR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r4, 0x00
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lwi r5, (CYGARC_REG_IMM_PORTQS-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r4, 0x00
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lwi r5, (CYGARC_REG_IMM_PQSPAR_DDRQST-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_MPIOSMDR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_MPIOSMDDR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_MIOS1TPCR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_SRAMMCR_A-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r4, 0x00000000
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lwi r5, (CYGARC_REG_IMM_SGPIODT1-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_SGPIODT2-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_SGPIOCR-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_EMCR-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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// Enable 32 interrupt priorities on the IMB3 unit
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lwi r4, 0x60000000
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lwi r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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#endif
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sync
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blr
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#------------------------------------------------------------------------------
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# end of cme555.S
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