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//=============================================================================
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//
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// hal_aux.c
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//
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// HAL auxiliary objects and code; per platform
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt
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// Contributors:hmt, gthomas
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// Date: 1999-06-08
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// Purpose: HAL aux objects: startup tables.
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// Description: Tables for per-platform initialization
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <pkgconf/io_pci.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/diag.h>
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#include <cyg/hal/hal_mem.h> // HAL memory definitions
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#include <cyg/hal/ppc_regs.h> // Platform registers
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#include <cyg/hal/hal_if.h> // hal_if_init
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#include <cyg/hal/hal_intr.h> // interrupt definitions
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#include <cyg/hal/hal_cache.h>
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/io/pci.h>
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#include <cyg/hal/hal_io.h> // I/O macros
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#include CYGHWR_MEMORY_LAYOUT_H
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// Functions defined in this module
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void _csb281_fs6377_init(int mode);
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static void _csb281_i2c_init(void);
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// The memory map is weakly defined, allowing the application to redefine
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// it if necessary. The regions defined below are the minimum requirements.
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CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
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// Mapping for the Cogent CSB281 development boards
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CYGARC_MEMDESC_NOCACHE( 0x70000000, 0x10000000 ), // FLASH region, LCD, PS/2
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CYGARC_MEMDESC_NOCACHE( 0xf0000000, 0x10000000 ), // PCI space, LEDS, control
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CYGARC_MEMDESC_CACHE( CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory
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// Main memory, mapped non-cacheable for PCI use
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CYGARC_MEMDESC_NOCACHE_PA(CYGMEM_SECTION_pci_window,
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CYGARC_PHYSICAL_ADDRESS(CYGMEM_SECTION_pci_window),
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CYGMEM_SECTION_pci_window_SIZE),
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CYGARC_MEMDESC_TABLE_END
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};
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//--------------------------------------------------------------------------
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// Platform init code.
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void
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hal_platform_init(void)
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{
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cyg_uint32 bcsr, gcr, frr, eicr, iack;
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int vec;
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// Initialize I/O interfaces
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hal_if_init();
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// Reset interrupt controller/state
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HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
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HAL_READ_UINT32LE(_CSB281_EPIC_FRR, frr);
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HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_R);
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do {
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HAL_READ_UINT32LE(_CSB281_EPIC_GCR, gcr);
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} while ((gcr & _CSB281_EPIC_GCR_R) != 0);
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HAL_WRITE_UINT32LE(_CSB281_EPIC_GCR, gcr | _CSB281_EPIC_GCR_M);
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HAL_READ_UINT32LE(_CSB281_EPIC_EICR, eicr); // Force direct interrupts
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eicr &= ~_CSB281_EPIC_EICR_SIE;
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HAL_WRITE_UINT32LE(_CSB281_EPIC_EICR, eicr);
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for (vec = CYGNUM_HAL_INTERRUPT_IRQ0; vec <= CYGNUM_HAL_ISR_MAX; vec++) {
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HAL_INTERRUPT_CONFIGURE(vec, 0, 0); // Default to low-edge
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HAL_INTERRUPT_SET_LEVEL(vec, 0x0F); // Priority
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}
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vec = (frr & 0x0FFF0000) >> 16; // Number of interrupt sources
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while (vec-- > 0) {
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HAL_READ_UINT32LE(_CSB281_EPIC_IACK, iack);
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HAL_WRITE_UINT32LE(_CSB281_EPIC_EOI, 0);
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}
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HAL_WRITE_UINT32LE(_CSB281_EPIC_PCTPR, 1); // Enables interrupts
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#ifndef CYGSEM_HAL_USE_ROM_MONITOR
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// Reset peripherals
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HAL_READ_UINT32(_CSB281_BCSR, bcsr);
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HAL_WRITE_UINT32(_CSB281_BCSR, _zero_bit(bcsr, _CSB281_BCSR_PRESET));
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HAL_WRITE_UINT32(_CSB281_BCSR, _one_bit(bcsr, _CSB281_BCSR_PRESET));
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_csb281_i2c_init();
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_csb281_fs6377_init(0);
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#endif
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#ifdef CYGSEM_CSB281_LCD_COMM
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lcd_comm_init();
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#endif
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_csb281_pci_init();
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}
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//--------------------------------------------------------------------------
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// Interrupt support
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CYG_ADDRWORD _pvrs[] = {
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_CSB281_EPIC_IVPR0, // CYGNUM_HAL_INTERRUPT_IRQ0 0x02
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_CSB281_EPIC_IVPR1, // CYGNUM_HAL_INTERRUPT_IRQ1 0x03
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_CSB281_EPIC_IVPR2, // CYGNUM_HAL_INTERRUPT_IRQ2 0x04
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_CSB281_EPIC_IVPR3, // CYGNUM_HAL_INTERRUPT_IRQ3 0x05
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_CSB281_EPIC_IVPR4, // CYGNUM_HAL_INTERRUPT_IRQ4 0x06
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_CSB281_EPIC_UART0VPR, // CYGNUM_HAL_INTERRUPT_UART0 0x07
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_CSB281_EPIC_UART1VPR, // CYGNUM_HAL_INTERRUPT_UART1 0x08
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_CSB281_EPIC_GTVPR0, // CYGNUM_HAL_INTERRUPT_TIMER0 0x09
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_CSB281_EPIC_GTVPR1, // CYGNUM_HAL_INTERRUPT_TIMER1 0x0A
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_CSB281_EPIC_GTVPR2, // CYGNUM_HAL_INTERRUPT_TIMER2 0x0B
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_CSB281_EPIC_GTVPR3, // CYGNUM_HAL_INTERRUPT_TIMER3 0x0C
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_CSB281_EPIC_I2CVPR, // CYGNUM_HAL_INTERRUPT_I2C 0x0D
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_CSB281_EPIC_DMA0VPR, // CYGNUM_HAL_INTERRUPT_DMA0 0x0E
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_CSB281_EPIC_DMA1VPR, // CYGNUM_HAL_INTERRUPT_DMA1 0x0F
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_CSB281_EPIC_MSGVPR, // CYGNUM_HAL_INTERRUPT_MSG 0x10
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};
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void
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hal_interrupt_mask(int vector)
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{
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cyg_uint32 pvr;
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CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
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CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
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if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
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// Can't do much with non-external interrupts
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return;
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}
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HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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pvr |= _CSB281_EPIC_PVR_M;
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HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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// diag_printf("%s(%d)\n", __FUNCTION__, vector);
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}
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void
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hal_interrupt_unmask(int vector)
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{
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cyg_uint32 pvr;
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CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
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CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
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if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
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// Can't do much with non-external interrupts
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return;
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}
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HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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pvr &= ~_CSB281_EPIC_PVR_M;
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HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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// diag_printf("%s(%d)\n", __FUNCTION__, vector);
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}
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void
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hal_interrupt_acknowledge(int vector)
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{
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}
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void
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hal_interrupt_configure(int vector, int level, int up)
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{
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cyg_uint32 pvr;
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CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
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CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
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if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
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// Can't do much with non-external interrupts
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return;
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}
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// diag_printf("%s(%d, %d, %d)\n", __FUNCTION__, vector, level, up);
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HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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pvr &= _CSB281_EPIC_PVR_M; // Preserve mask
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pvr |= vector;
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if (level) {
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pvr |= _CSB281_EPIC_PVR_S;
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} else {
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pvr &= ~_CSB281_EPIC_PVR_S;
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}
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if (up) {
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pvr |= _CSB281_EPIC_PVR_P;
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} else {
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pvr &= ~_CSB281_EPIC_PVR_P;
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}
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HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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}
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void
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hal_interrupt_set_level(int vector, int level)
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{
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cyg_uint32 pvr;
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CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
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CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
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if (vector < CYGNUM_HAL_INTERRUPT_IRQ0) {
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// Can't do much with non-external interrupts
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return;
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}
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HAL_READ_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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pvr &= ~(_CSB281_EPIC_PVR_PRIO_MASK<<_CSB281_EPIC_PVR_PRIO_SHIFT);
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pvr |= (level<<_CSB281_EPIC_PVR_PRIO_SHIFT);
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HAL_WRITE_UINT32LE(_pvrs[vector-CYGNUM_HAL_INTERRUPT_IRQ0], pvr);
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}
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//--------------------------------------------------------------------------
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// PCI support
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externC void
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_csb281_pci_init(void)
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{
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static int _init = 0;
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cyg_uint8 next_bus;
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cyg_uint32 cmd_state;
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if (_init) return;
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_init = 1;
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// Initialize PCI support
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cyg_pci_init();
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// Setup for bus mastering
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HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_COMMAND, cmd_state);
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if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
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// Force PCI-side window to 0
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HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_BAR_0, 0x01);
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// Enable bus mastering from host
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HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_COMMAND,
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CYG_PCI_CFG_COMMAND_MEMORY |
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CYG_PCI_CFG_COMMAND_MASTER |
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CYG_PCI_CFG_COMMAND_PARITY |
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CYG_PCI_CFG_COMMAND_SERR);
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267 |
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// Setup latency timer field
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HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_LATENCY_TIMER, 32);
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271 |
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// Configure PCI bus.
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next_bus = 1;
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274 |
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cyg_pci_configure_bus(0, &next_bus);
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}
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276 |
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277 |
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if (0){
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278 |
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cyg_uint8 devfn;
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279 |
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cyg_pci_device_id devid;
|
280 |
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cyg_pci_device dev_info;
|
281 |
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int i;
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282 |
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283 |
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devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
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284 |
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while (cyg_pci_find_next(devid, &devid)) {
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devfn = CYG_PCI_DEV_GET_DEVFN(devid);
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cyg_pci_get_device_info(devid, &dev_info);
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diag_printf("\n");
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diag_printf("Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid));
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diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
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diag_printf("PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn));
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diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
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diag_printf("Device Id : 0x%08X\n", dev_info.device);
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for (i = 0; i < dev_info.num_bars; i++) {
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295 |
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diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
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diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
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297 |
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dev_info.base_size[i], dev_info.base_map[i]);
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298 |
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}
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299 |
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}
|
300 |
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}
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301 |
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302 |
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// Configure interrupts (high level)?
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303 |
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HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
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304 |
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HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
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305 |
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HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
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306 |
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}
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307 |
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|
|
308 |
|
|
externC void
|
309 |
|
|
_csb281_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
|
310 |
|
|
{
|
311 |
|
|
cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);
|
312 |
|
|
|
313 |
|
|
// Purely slot based
|
314 |
|
|
if (dev >= CYG_PCI_MIN_DEV) {
|
315 |
|
|
CYG_ADDRWORD __translation[] = {
|
316 |
|
|
CYGNUM_HAL_INTERRUPT_PCI0,
|
317 |
|
|
CYGNUM_HAL_INTERRUPT_PCI1,
|
318 |
|
|
CYGNUM_HAL_INTERRUPT_LAN
|
319 |
|
|
};
|
320 |
|
|
*vec = __translation[dev-CYG_PCI_MIN_DEV];
|
321 |
|
|
*valid = true;
|
322 |
|
|
} else {
|
323 |
|
|
*valid = false;
|
324 |
|
|
}
|
325 |
|
|
#if 0
|
326 |
|
|
diag_printf("Int - dev: %d, vector: %d [%s]\n",
|
327 |
|
|
dev, *vec, *valid ? "OK" : "BAD");
|
328 |
|
|
#endif
|
329 |
|
|
}
|
330 |
|
|
|
331 |
|
|
// PCI configuration space access
|
332 |
|
|
#define _EXT_ENABLE 0x80000000
|
333 |
|
|
|
334 |
|
|
//
|
335 |
|
|
// Prepare for a config cycle on the PCI bus
|
336 |
|
|
//
|
337 |
|
|
static __inline__ cyg_uint32
|
338 |
|
|
_cfg_sel(int bus, int devfn, int offset)
|
339 |
|
|
{
|
340 |
|
|
cyg_uint32 cfg_addr, addr;
|
341 |
|
|
cyg_uint32 bcsr;
|
342 |
|
|
|
343 |
|
|
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
|
344 |
|
|
bcsr = (bcsr & ~0x07) | (1<<(CYG_PCI_DEV_GET_DEV(devfn)-CYG_PCI_MIN_DEV));
|
345 |
|
|
HAL_WRITE_UINT32(_CSB281_BCSR, bcsr);
|
346 |
|
|
cfg_addr = _EXT_ENABLE |
|
347 |
|
|
(bus << 16) |
|
348 |
|
|
(CYG_PCI_DEV_GET_DEV(devfn) << 11) |
|
349 |
|
|
(CYG_PCI_DEV_GET_FN(devfn) << 8) |
|
350 |
|
|
((offset & 0xFF) << 0);
|
351 |
|
|
HAL_WRITE_UINT32LE(_CSB281_PCI_CONFIG_ADDR, cfg_addr);
|
352 |
|
|
addr = _CSB281_PCI_CONFIG_DATA + (offset & 0x03);
|
353 |
|
|
return addr;
|
354 |
|
|
}
|
355 |
|
|
|
356 |
|
|
externC cyg_uint8
|
357 |
|
|
_csb281_pci_cfg_read_uint8(int bus, int devfn, int offset)
|
358 |
|
|
{
|
359 |
|
|
cyg_uint32 addr;
|
360 |
|
|
cyg_uint8 cfg_val = (cyg_uint8)0xFF;
|
361 |
|
|
|
362 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
363 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
364 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
365 |
|
|
addr = _cfg_sel(bus, devfn, offset);
|
366 |
|
|
HAL_READ_UINT8LE(addr, cfg_val);
|
367 |
|
|
#if 0
|
368 |
|
|
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
|
369 |
|
|
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
|
370 |
|
|
// Cycle failed - clean up and get out
|
371 |
|
|
cfg_val = (cyg_uint8)0xFF;
|
372 |
|
|
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
|
373 |
|
|
}
|
374 |
|
|
#endif
|
375 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
376 |
|
|
diag_printf("%x\n", cfg_val);
|
377 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
378 |
|
|
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
|
379 |
|
|
return cfg_val;
|
380 |
|
|
}
|
381 |
|
|
|
382 |
|
|
externC cyg_uint16
|
383 |
|
|
_csb281_pci_cfg_read_uint16(int bus, int devfn, int offset)
|
384 |
|
|
{
|
385 |
|
|
cyg_uint32 addr;
|
386 |
|
|
cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;
|
387 |
|
|
|
388 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
389 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
390 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
391 |
|
|
addr = _cfg_sel(bus, devfn, offset);
|
392 |
|
|
HAL_READ_UINT16LE(addr, cfg_val);
|
393 |
|
|
#if 0
|
394 |
|
|
HAL_READ_UINT16LE(_CSB281_PCI_STAT_CMD, status);
|
395 |
|
|
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
|
396 |
|
|
// Cycle failed - clean up and get out
|
397 |
|
|
cfg_val = (cyg_uint16)0xFFFF;
|
398 |
|
|
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
|
399 |
|
|
}
|
400 |
|
|
#endif
|
401 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
402 |
|
|
diag_printf("%x\n", cfg_val);
|
403 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
404 |
|
|
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
|
405 |
|
|
return cfg_val;
|
406 |
|
|
}
|
407 |
|
|
|
408 |
|
|
externC cyg_uint32
|
409 |
|
|
_csb281_pci_cfg_read_uint32(int bus, int devfn, int offset)
|
410 |
|
|
{
|
411 |
|
|
cyg_uint32 addr;
|
412 |
|
|
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
|
413 |
|
|
|
414 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
415 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
416 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
417 |
|
|
addr = _cfg_sel(bus, devfn, offset);
|
418 |
|
|
HAL_READ_UINT32LE(addr, cfg_val);
|
419 |
|
|
#if 0
|
420 |
|
|
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
|
421 |
|
|
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
|
422 |
|
|
// Cycle failed - clean up and get out
|
423 |
|
|
cfg_val = (cyg_uint32)0xFFFFFFFF;
|
424 |
|
|
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
|
425 |
|
|
}
|
426 |
|
|
#endif
|
427 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
428 |
|
|
diag_printf("%x\n", cfg_val);
|
429 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
430 |
|
|
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
|
431 |
|
|
return cfg_val;
|
432 |
|
|
}
|
433 |
|
|
|
434 |
|
|
externC void
|
435 |
|
|
_csb281_pci_cfg_write_uint8(int bus, int devfn, int offset, cyg_uint8 cfg_val)
|
436 |
|
|
{
|
437 |
|
|
cyg_uint32 addr;
|
438 |
|
|
|
439 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
440 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
441 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
442 |
|
|
addr = _cfg_sel(bus, devfn, offset);
|
443 |
|
|
HAL_WRITE_UINT8LE(addr, cfg_val);
|
444 |
|
|
#if 0
|
445 |
|
|
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
|
446 |
|
|
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
|
447 |
|
|
// Cycle failed - clean up and get out
|
448 |
|
|
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
|
449 |
|
|
}
|
450 |
|
|
#endif
|
451 |
|
|
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
|
452 |
|
|
}
|
453 |
|
|
|
454 |
|
|
externC void
|
455 |
|
|
_csb281_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
|
456 |
|
|
{
|
457 |
|
|
cyg_uint32 addr;
|
458 |
|
|
|
459 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
460 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
461 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
462 |
|
|
addr = _cfg_sel(bus, devfn, offset);
|
463 |
|
|
HAL_WRITE_UINT16LE(addr, cfg_val);
|
464 |
|
|
#if 0
|
465 |
|
|
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
|
466 |
|
|
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
|
467 |
|
|
// Cycle failed - clean up and get out
|
468 |
|
|
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
|
469 |
|
|
}
|
470 |
|
|
#endif
|
471 |
|
|
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
|
472 |
|
|
}
|
473 |
|
|
|
474 |
|
|
externC void
|
475 |
|
|
_csb281_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
|
476 |
|
|
{
|
477 |
|
|
cyg_uint32 addr;
|
478 |
|
|
|
479 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
480 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
481 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
482 |
|
|
addr = _cfg_sel(bus, devfn, offset);
|
483 |
|
|
HAL_WRITE_UINT32LE(addr, cfg_val);
|
484 |
|
|
#if 0
|
485 |
|
|
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
|
486 |
|
|
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
|
487 |
|
|
// Cycle failed - clean up and get out
|
488 |
|
|
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
|
489 |
|
|
}
|
490 |
|
|
#endif
|
491 |
|
|
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
|
492 |
|
|
}
|
493 |
|
|
|
494 |
|
|
//--------------------------------------------------------------------------
|
495 |
|
|
// I2C support
|
496 |
|
|
static void
|
497 |
|
|
_csb281_i2c_init(void)
|
498 |
|
|
{
|
499 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_ALL); // SDA=1, SCL=1
|
500 |
|
|
}
|
501 |
|
|
|
502 |
|
|
static void
|
503 |
|
|
_csb281_i2c_delay(void)
|
504 |
|
|
{
|
505 |
|
|
int ctr;
|
506 |
|
|
|
507 |
|
|
for (ctr = 0; ctr < 100*10; ctr++);
|
508 |
|
|
}
|
509 |
|
|
|
510 |
|
|
// Issue start sequence which is SDA(1->0) with SCL(1)
|
511 |
|
|
static void
|
512 |
|
|
_csb281_i2c_start(void)
|
513 |
|
|
{
|
514 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA); // SDA=1, SCL=?
|
515 |
|
|
_csb281_i2c_delay();
|
516 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL); // SDA=1, SCL=1
|
517 |
|
|
_csb281_i2c_delay();
|
518 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SDA); // SDA=0, SCL=1
|
519 |
|
|
_csb281_i2c_delay();
|
520 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL); // SDA=0, SCL=0
|
521 |
|
|
_csb281_i2c_delay();
|
522 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA); // SDA=1, SCL=1
|
523 |
|
|
_csb281_i2c_delay();
|
524 |
|
|
}
|
525 |
|
|
|
526 |
|
|
// Issue stop sequence which is SDA(0->1) with SCL(1)
|
527 |
|
|
static void
|
528 |
|
|
_csb281_i2c_stop(void)
|
529 |
|
|
{
|
530 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SDA); // SDA=0, SCL=?
|
531 |
|
|
_csb281_i2c_delay();
|
532 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL); // SDA=1, SCL=1
|
533 |
|
|
_csb281_i2c_delay();
|
534 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA); // SDA=1, SCL=1
|
535 |
|
|
_csb281_i2c_delay();
|
536 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL); // SDA=0, SCL=0
|
537 |
|
|
_csb281_i2c_delay();
|
538 |
|
|
}
|
539 |
|
|
|
540 |
|
|
// Send an 8-bit value, MSB first, SCL(1->0) clocks the data
|
541 |
|
|
static int
|
542 |
|
|
_csb281_i2c_put(unsigned char val)
|
543 |
|
|
{
|
544 |
|
|
int bit, csr;
|
545 |
|
|
|
546 |
|
|
for (bit = 7; bit >= 0; bit--) {
|
547 |
|
|
if ((val & (1 << bit))) {
|
548 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA); // SDA=1, SCL=?
|
549 |
|
|
} else {
|
550 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SDA); // SDA=0, SCL=?
|
551 |
|
|
}
|
552 |
|
|
_csb281_i2c_delay();
|
553 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL); // SDA=?, SCL=1
|
554 |
|
|
_csb281_i2c_delay();
|
555 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL); // SDA=?, SCL=0
|
556 |
|
|
}
|
557 |
|
|
// Now wait for ACK
|
558 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SDA); // SDA=1, SCL=0
|
559 |
|
|
_csb281_i2c_delay();
|
560 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL); // SDA=1, SCL=1
|
561 |
|
|
_csb281_i2c_delay();
|
562 |
|
|
HAL_READ_UINT32(_CSB281_2WCSR, csr); // Read current state
|
563 |
|
|
if ((csr & _CSB281_2WCSR_GET_SDA)) {
|
564 |
|
|
// No ACK!
|
565 |
|
|
return -1;
|
566 |
|
|
}
|
567 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL); // SDA=?, SCL=0
|
568 |
|
|
_csb281_i2c_delay();
|
569 |
|
|
return 0;
|
570 |
|
|
}
|
571 |
|
|
|
572 |
|
|
static unsigned char
|
573 |
|
|
_csb281_i2c_get(void)
|
574 |
|
|
{
|
575 |
|
|
unsigned char val = 0;
|
576 |
|
|
int bit, csr;
|
577 |
|
|
|
578 |
|
|
for (bit = 7; bit >= 0; bit--) {
|
579 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL); // SDA=?, SCL=1
|
580 |
|
|
_csb281_i2c_delay();
|
581 |
|
|
HAL_READ_UINT32(_CSB281_2WCSR, csr); // Read current state
|
582 |
|
|
if ((csr & _CSB281_2WCSR_GET_SDA)) {
|
583 |
|
|
val |= (1 << bit);
|
584 |
|
|
}
|
585 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL); // SDA=?, SCL=0
|
586 |
|
|
_csb281_i2c_delay();
|
587 |
|
|
}
|
588 |
|
|
// Need extra transition (for ACK time slot)
|
589 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_SET_SCL); // SDA=?, SCL=0
|
590 |
|
|
_csb281_i2c_delay();
|
591 |
|
|
HAL_WRITE_UINT32(_CSB281_2WCSR, _CSB281_2WCSR_CLR_SCL); // SDA=?, SCL=0
|
592 |
|
|
_csb281_i2c_delay();
|
593 |
|
|
return val;
|
594 |
|
|
}
|
595 |
|
|
|
596 |
|
|
int
|
597 |
|
|
_csb281_i2c_write_reg(int addr, int reg, unsigned char val)
|
598 |
|
|
{
|
599 |
|
|
_csb281_i2c_start();
|
600 |
|
|
if (_csb281_i2c_put(addr << 1) < 0) {
|
601 |
|
|
return -1;
|
602 |
|
|
}
|
603 |
|
|
if (_csb281_i2c_put(reg) < 0) {
|
604 |
|
|
return -1;
|
605 |
|
|
}
|
606 |
|
|
if (_csb281_i2c_put(val) < 0) {
|
607 |
|
|
return -1;
|
608 |
|
|
}
|
609 |
|
|
_csb281_i2c_stop();
|
610 |
|
|
return 0;
|
611 |
|
|
}
|
612 |
|
|
|
613 |
|
|
int
|
614 |
|
|
_csb281_i2c_read_reg(int addr, int reg)
|
615 |
|
|
{
|
616 |
|
|
unsigned char val;
|
617 |
|
|
_csb281_i2c_start();
|
618 |
|
|
if (_csb281_i2c_put(addr << 1) < 0) {
|
619 |
|
|
return -1;
|
620 |
|
|
}
|
621 |
|
|
if (_csb281_i2c_put(reg) < 0) {
|
622 |
|
|
return -1;
|
623 |
|
|
}
|
624 |
|
|
_csb281_i2c_start();
|
625 |
|
|
if (_csb281_i2c_put((addr << 1) | 0x01) < 0) {
|
626 |
|
|
return -1;
|
627 |
|
|
}
|
628 |
|
|
val = _csb281_i2c_get();
|
629 |
|
|
_csb281_i2c_stop();
|
630 |
|
|
return val;
|
631 |
|
|
}
|
632 |
|
|
|
633 |
|
|
//--------------------------------------------------------------------------
|
634 |
|
|
// FS6377 Clock generator support
|
635 |
|
|
|
636 |
|
|
static unsigned char _fs6377_init_data[] = {
|
637 |
|
|
0x28, 0xEF, 0x53, 0x03, 0x4B, 0x80, 0x32, 0x80,
|
638 |
|
|
0x94, 0x32, 0x80, 0xD4, 0x56, 0xF6, 0xF6, 0xE0
|
639 |
|
|
};
|
640 |
|
|
|
641 |
|
|
// Setup for CRT mode 640x480 @75Hz
|
642 |
|
|
static unsigned char _fs6377_init_data_CRT[] = {
|
643 |
|
|
0x10, 0x3b, 0x49, 0x03, 0x4B, 0x80, 0x32, 0x80,
|
644 |
|
|
0x94, 0x32, 0x80, 0xD4, 0x66, 0xF6, 0xF6, 0xE0
|
645 |
|
|
};
|
646 |
|
|
|
647 |
|
|
void
|
648 |
|
|
_csb281_fs6377_init(int mode)
|
649 |
|
|
{
|
650 |
|
|
int reg;
|
651 |
|
|
unsigned char *data;
|
652 |
|
|
|
653 |
|
|
if (mode) {
|
654 |
|
|
data = _fs6377_init_data_CRT;
|
655 |
|
|
} else {
|
656 |
|
|
data = _fs6377_init_data;
|
657 |
|
|
}
|
658 |
|
|
for (reg = 0; reg < 16; reg++) {
|
659 |
|
|
if (_csb281_i2c_write_reg(_CSB281_FS6377_DEV, reg, *data++) < 0) {
|
660 |
|
|
diag_printf("** Can't write FS6377 register %d\n", reg);
|
661 |
|
|
return;
|
662 |
|
|
}
|
663 |
|
|
}
|
664 |
|
|
}
|
665 |
|
|
|
666 |
|
|
//--------------------------------------------------------------------------
|
667 |
|
|
// Blink the value 'val' into the LEDs
|
668 |
|
|
// LED0 - clock
|
669 |
|
|
// LED1 - value
|
670 |
|
|
|
671 |
|
|
static void
|
672 |
|
|
_set_leds(int led0, int led1)
|
673 |
|
|
{
|
674 |
|
|
cyg_uint32 bcsr;
|
675 |
|
|
|
676 |
|
|
HAL_READ_UINT32(_CSB281_BCSR, bcsr);
|
677 |
|
|
bcsr = _one_bit(bcsr, (_CSB281_BCSR_LED0 | _CSB281_BCSR_LED1));
|
678 |
|
|
if (led0) bcsr = _zero_bit(bcsr, _CSB281_BCSR_LED0);
|
679 |
|
|
if (led1) bcsr = _zero_bit(bcsr, _CSB281_BCSR_LED1);
|
680 |
|
|
HAL_WRITE_UINT32(_CSB281_BCSR, bcsr);
|
681 |
|
|
}
|
682 |
|
|
|
683 |
|
|
static void
|
684 |
|
|
_led_delay(int len)
|
685 |
|
|
{
|
686 |
|
|
int ctr, limit;
|
687 |
|
|
int cache_state;
|
688 |
|
|
|
689 |
|
|
HAL_ICACHE_IS_ENABLED(cache_state);
|
690 |
|
|
limit = cache_state ? 0x100000 : 0x40000;
|
691 |
|
|
while (len--) {
|
692 |
|
|
for (ctr = 0; ctr < limit; ctr++);
|
693 |
|
|
}
|
694 |
|
|
}
|
695 |
|
|
|
696 |
|
|
void
|
697 |
|
|
_csb281_led(int val)
|
698 |
|
|
{
|
699 |
|
|
int bit, ctr;
|
700 |
|
|
|
701 |
|
|
for (ctr = 0; ctr < 8; ctr++) {
|
702 |
|
|
_set_leds(0,0);
|
703 |
|
|
_led_delay(1);
|
704 |
|
|
_set_leds(0,1);
|
705 |
|
|
_led_delay(1);
|
706 |
|
|
}
|
707 |
|
|
_set_leds(0,0);
|
708 |
|
|
_led_delay(16);
|
709 |
|
|
for (bit = 7; bit >= 0; bit--) {
|
710 |
|
|
_set_leds(1, val & (1<<bit));
|
711 |
|
|
_led_delay(8);
|
712 |
|
|
_set_leds(0, 0);
|
713 |
|
|
_led_delay(8);
|
714 |
|
|
}
|
715 |
|
|
}
|
716 |
|
|
|
717 |
|
|
// EOF hal_aux.c
|