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##=============================================================================
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##
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## ec555.S
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##
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## ec555 board hardware setup
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): Bob Koninckx
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## Contributors:Bob Koninckx
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## Date: 2002-01-01
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## Purpose: ec555 board hardware setup
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## Description: This file contains any code needed to initialize the
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## hardware on a ec555 mpc555 board.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#include
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#include
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#ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
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#include
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#endif
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## FIXME
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## The following probably belongs in the variant hal rather than the board specifics ...
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#ifdef CYGPKG_DEVICES_WATCHDOG_MPC5xx
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#include
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#define CYG_SYPCR 0x0000ff8e | (CYGNUM_DEVICES_WATCHDOG_POWERPC_MPC5XX_RELOAD << 16) | CYGDAT_DEVICES_WATCHDOG_POWERPC_MPC5XX_PRESCALE
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#else
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#define CYG_SYPCR 0x0000ff88
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#endif
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#define ADDRESS_MASK_1MB 0xfff00000
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#define ADDRESS_MASK_2MB 0xffe00000
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#define ADDRESS_MASK_4MB 0xffc00000
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#define ADDRESS_MASK_8MB 0xff800000
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#define ADDRESS_MASK_16MB 0xff000000
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#define EC555_RAM_BASE_ADDRESS 0x01000000
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#define EC555_FLASH_BASE_ADDRESS 0x02000000
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#define EC555_CS2_BASE_ADDRESS 0x04000000
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#define EC555_CS3_BASE_ADDRESS 0x08000000
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#if defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F02_S01)
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#define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_1MB
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#define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_2MB
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#elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F04_S02)
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#define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_2MB
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#define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_4MB
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#elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F08_S04)
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#define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_4MB
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#define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_8MB
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#elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F08_S08)
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#define EC555_RAM_ADDRESS_MASK ADDRESS_MASK_8MB
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#define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_16MB
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#else
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#error "EC555 Board variant unspecified"
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#endif
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#define EC555_CS2_ADDRESS_MASK 0xffff8000
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#define EC555_CS3_ADDRESS_MASK 0xffff8000
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#------------------------------------------------------------------------------
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.globl hal_hardware_init
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hal_hardware_init:
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#if defined(CYGPKG_HAL_POWERPC_EC555) && defined(CYGPKG_HAL_POWERPC_MPC5xx)
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lwi r3, CYGARC_REG_IMM_BASE # Base address of control registers
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#if defined(CYG_HAL_STARTUP_ROM)
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// Burst enable
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lwi r0, 0x00002000
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mtspr 560, r0
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// FIXME
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// The following probably belongs in the variant hal rather than the board specifics ...
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// Disable / enable the Watchdog
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lwi r4, CYG_SYPCR
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stw r4, (CYGARC_REG_IMM_SYPCR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0x00000000
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stw r4, (CYGARC_REG_IMM_SIUMCR-CYGARC_REG_IMM_BASE)(r3)
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// Unlock locked registers
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lwi r4, 0x55ccaa33
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stw r4, (CYGARC_REG_IMM_TBSCRK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_TBREF0K-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_TBREF1K-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_TBK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_RTCSCK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_RTCK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_RTSECK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_RTCALK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_PISCRK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_PITCK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_SCCRK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_PLPRCRK-CYGARC_REG_IMM_BASE)(r3)
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stw r4, (CYGARC_REG_IMM_RSRK-CYGARC_REG_IMM_BASE)(r3)
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// Either Redboot or BDM will have already done it otherwise
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// Boost the clock to 40MHz
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lwi r4, 0x03000000
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stw r4, (CYGARC_REG_IMM_SCCR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0x009150c0
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stw r4, (CYGARC_REG_IMM_PLPRCR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0x0080
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sth r4, (CYGARC_REG_IMM_COLIR-CYGARC_REG_IMM_BASE)(r3)
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// Set up the memory map
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// Do NOT write protect the flash memory, flash drivers won't work
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// if we do
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// flash banks
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lwi r4, (EC555_FLASH_BASE_ADDRESS | 0x00000003)
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stw r4, (CYGARC_REG_IMM_BR0-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, (EC555_FLASH_ADDRESS_MASK | 0x00000530)
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stw r4, (CYGARC_REG_IMM_OR0-CYGARC_REG_IMM_BASE)(r3)
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// ram banks
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lwi r4, (EC555_RAM_BASE_ADDRESS | 0x00000011)
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stw r4, (CYGARC_REG_IMM_BR1-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, (EC555_RAM_ADDRESS_MASK | 0x00000000)
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stw r4, (CYGARC_REG_IMM_OR1-CYGARC_REG_IMM_BASE)(r3)
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#endif
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#ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
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#if (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 2)
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lwi r4, (EC555_CS2_BASE_ADDRESS | 0x00000803)
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stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0xffff8ca0
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stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, EC555_CS3_BASE_ADDRESS
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stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, EC555_CS3_ADDRESS_MASK
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stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
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#elif (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 3)
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lwi r4, EC555_CS2_BASE_ADDRESS
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stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, EC555_CS2_ADDRESS_MASK
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stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, (EC555_CS3_BASE_ADDRESS | 0x00000803)
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stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0xffff8ca0
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stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
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#else
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#error "Invalid chip select for ethernet card specified"
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#endif
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#else
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lwi r4, EC555_CS2_BASE_ADDRESS
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stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, EC555_CS2_ADDRESS_MASK
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stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, EC555_CS3_BASE_ADDRESS
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stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, EC555_CS3_ADDRESS_MASK
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stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
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#endif
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#if defined(CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP)
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lwi r4, 1
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#else
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lwi r4, 0
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#endif
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stw r4, (CYGARC_REG_IMM_DMBR-CYGARC_REG_IMM_BASE)(r3)
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lwi r4, 0
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stw r4, (CYGARC_REG_IMM_DMOR-CYGARC_REG_IMM_BASE)(r3)
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// Enable the time base, but do _not_ set the freeze flag
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lwi r4, 0xc1
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sth r4, (CYGARC_REG_IMM_TBSCR-CYGARC_REG_IMM_BASE)(r3)
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// RTC is clocked by 4MHz crystal, set the freeze flag
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lwi r4, 0xd2
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sth r4, (CYGARC_REG_IMM_RTCSC-CYGARC_REG_IMM_BASE)(r3)
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// Set the freeze flag for the Periodic interrupt timer
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lwi r4, 0x82
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sth r4, (CYGARC_REG_IMM_PISCR-CYGARC_REG_IMM_BASE)(r3)
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// USIU rest.
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lwi r4, 0x00000000
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lwi r5, (CYGARC_REG_IMM_SGPIODT1-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_SGPIODT2-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_SGPIOCR-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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lwi r4, 0x00000ac6
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lwi r5, (CYGARC_REG_IMM_EMCR-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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// Dual ported TPU RAM
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lwi r4, 0x0000
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lwi r5, (CYGARC_REG_IMM_DPTMCR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r4, 0xffa0
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lwi r5, (CYGARC_REG_IMM_RAMBAR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r4, 0x00
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lwi r5, (CYGARC_REG_IMM_PORTQS-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r4, 0x00
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lwi r5, (CYGARC_REG_IMM_PQSPAR_DDRQST-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_MPIOSMDR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_MPIOSMDDR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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lwi r5, (CYGARC_REG_IMM_SRAMMCR_A-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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// They are assigned OCD functionality on this board
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// Change the following to anything else and BDM will not work anymore
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// on the ec555. This is not true for all MPC555 based boards, eg. cme555
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// does not have this requirement
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lwi r4, 0x3
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lwi r5, (CYGARC_REG_IMM_MIOS1TPCR-CYGARC_REG_IMM_BASE)
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sthx r4, r3, r5
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// Enable 32 interrupt priorities on the IMB3 unit
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lwi r4, 0x60000000
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lwi r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE)
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stwx r4, r3, r5
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#endif
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sync
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blr
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#------------------------------------------------------------------------------
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# end of ec555.S
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