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#ifndef CYGONCE_PLF_IO_H
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#define CYGONCE_PLF_IO_H
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//=============================================================================
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//
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// plf_io.h
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//
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// Platform specific IO support
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt, jskov
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// Contributors: hmt, jskov, gthomas
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// Date: 2002-07-23
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// Purpose: TAMS MOAB (PowerPC 405GPr) PCI IO support macros
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// Description:
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// Usage: #include <cyg/hal/plf_io.h>
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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//-----------------------------------------------------------------------------
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//
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// PCI support
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//
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#define CYGARC_PHYSICAL_ADDRESS(x) ((unsigned long)(x) & 0x7FFFFFFF)
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#define CYGARC_VIRTUAL_ADDRESS(x) ((unsigned long)(x) & 0x7FFFFFFF)
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// Restrict device [slot] space
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#define CYG_PCI_MAX_BUS 1 // Only one BUS
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#define CYG_PCI_MIN_DEV 1 // Slots start at 11
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#define CYG_PCI_MAX_DEV 22 // ... and end at 31
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#define _IRQ1 CYGNUM_HAL_INTERRUPT_IRQ1
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#define _IRQ2 CYGNUM_HAL_INTERRUPT_IRQ2
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#define _IRQ3 CYGNUM_HAL_INTERRUPT_IRQ3
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#define _IRQ4 CYGNUM_HAL_INTERRUPT_IRQ4
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#define CYG_PCI_IRQ_MAP \
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/* \
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* This mapping comes from this table, based on how the backplane is wired \
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* IRQ assignments (Acrosser): \
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* \
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* CPU Slot1 Slot2 Slot3 Slot4 \
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* IRQ1 PCI INTD INTB INTA INTD na \
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* IRQ2 PCI INTC INTA INTD INTC na \
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* IRQ3 PCI INTB INTD INTC INTB na \
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* IRQ4 PCI INTA INTC INTB INTA na \
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* \
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* PCI IDSEL/INTPIN->INTLINE \
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* A B C D \
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*/ \
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{ \
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{_IRQ1, _IRQ4, _IRQ3, _IRQ2}, /* IDSEL 1 - 2nd LAN */ \
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{_IRQ3, _IRQ3, _IRQ3, _IRQ3}, /* IDSEL 2 - USB */ \
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{ -1, -1, -1, -1}, /* IDSEL 3 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 4 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 5 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 6 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 7 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 8 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 9 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 10 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 11 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 12 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 13 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 14 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 15 - unavailable */ \
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{ -1, -1, -1, -1}, /* IDSEL 16 - unavailable */ \
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{_IRQ1, _IRQ4, _IRQ3, _IRQ2}, /* IDSEL 17 - PCI slot 2 */ \
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{_IRQ4, _IRQ3, _IRQ2, _IRQ1}, /* IDSEL 18 - PCI slot 3 */ \
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{_IRQ1, _IRQ4, _IRQ3, _IRQ2}, /* IDSEL 19 - PCI slot 2 */ \
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{_IRQ2, _IRQ1, _IRQ4, _IRQ3}, /* IDSEL 20 - PCI slot 1 */ \
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}
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//-----------------------------------------------------------------------------
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// Resources
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// Map PCI device resources starting from these addresses in PCI space.
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#define HAL_PCI_ALLOC_BASE_MEMORY 0x00000000
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#define HAL_PCI_ALLOC_BASE_IO 0x00800000
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// This is where the PCI spaces are mapped in the CPU's address space.
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#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xA0000000
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#define HAL_PCI_PHYSICAL_IO_BASE 0xE8000000
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#if 1 // This is an old-school idea about how to handle PCI devices
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// These seem to be defined multiple ways?
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#define CYGMEM_SECTION_pci_window 0x03F00000
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#define CYGMEM_SECTION_pci_window_SIZE 0x00100000
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#endif
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// IDE support
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#define HAL_IDE_NUM_CONTROLLERS 2 // One card, two controllers
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externC cyg_uint8 cyg_hal_plf_ide_read_uint8(int ctlr, cyg_uint32 reg);
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externC void cyg_hal_plf_ide_write_uint8(int ctlr, cyg_uint32 reg, cyg_uint8 val);
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externC cyg_uint16 cyg_hal_plf_ide_read_uint16(int ctlr, cyg_uint32 reg);
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externC void cyg_hal_plf_ide_write_uint16(int ctlr, cyg_uint32 reg, cyg_uint16 val);
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externC void cyg_hal_plf_ide_write_control(int ctlr, cyg_uint8 val);
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externC int cyg_hal_plf_ide_init(void);
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#define HAL_IDE_READ_UINT8( __ctlr, __reg, __val) \
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__val = cyg_hal_plf_ide_read_uint8((__ctlr), (__reg))
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#define HAL_IDE_READ_UINT16( __ctlr, __reg, __val) \
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__val = cyg_hal_plf_ide_read_uint16((__ctlr), (__reg))
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#define HAL_IDE_WRITE_UINT8( __ctlr, __reg, __val) \
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cyg_hal_plf_ide_write_uint8((__ctlr), (__reg), (__val))
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#define HAL_IDE_WRITE_UINT16( __ctlr, __reg, __val) \
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cyg_hal_plf_ide_write_uint16((__ctlr), (__reg), (__val))
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#define HAL_IDE_WRITE_CONTROL( __ctlr, __val) \
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cyg_hal_plf_ide_write_control((__ctlr), (__val))
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#define HAL_IDE_INIT() cyg_hal_plf_ide_init()
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//-----------------------------------------------------------------------------
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// end of plf_io.h
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#endif // CYGONCE_PLF_IO_H
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