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##=============================================================================
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##
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## moab.S
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##
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## MOAB board hardware setup
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): gthomas
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## Contributors:hmt
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## Date: 2002-07-22
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## Purpose: MOAB board hardware setup
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## Description: This file contains any code needed to initialize the
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## hardware on a TAMS MOAB (PowerPC 405GPr) board.
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include /* register symbols et al */
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#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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#include /* on-chip resource layout, special */
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#------------------------------------------------------------------------------
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// No useable LEDs
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#define LED(x)
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//
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// Various setup values - based on board revision &/or xtal speed
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//
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#if defined(CYG_HAL_MOAB_BOARD_REVISION_1_0)
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#define MOAB_DCR_SDRAM0_RTR 0x05F00000
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#define MOAB_DCR_SDRAM0_B1CR 0x00062001
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#define MOAB_DCR_SDRAM0_B0CR 0x02062001
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#define MOAB_DCR_SDRAM0_CFG 0x80800000
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#elif defined(CYG_HAL_MOAB_BOARD_REVISION_1_1)
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#define MOAB_DCR_SDRAM0_RTR 0x07F00000
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#define MOAB_DCR_SDRAM0_B1CR 0x00084001
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#define MOAB_DCR_SDRAM0_B0CR 0x00000000
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#define MOAB_DCR_SDRAM0_CFG 0x80800000
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#else
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#error "Illegal board revision"
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#endif
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#if CYGHWR_HAL_POWERPC_CPU_SPEED == 250
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#define MOAB_DCR_CPC0_CR0 0x09F8502A
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#define MOAB_DCR_EBC0_B1AP 0x03840000
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#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 333
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#define MOAB_DCR_CPC0_CR0 0x09F8503A
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#define MOAB_DCR_EBC0_B1AP 0x05840000
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#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 300
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#define MOAB_DCR_CPC0_CR0 0x0FF85034
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#define MOAB_DCR_EBC0_B1AP 0x0A840000
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#elif CYGHWR_HAL_POWERPC_CPU_SPEED == 400
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#define MOAB_DCR_CPC0_CR0 0x0FF8503C
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#define MOAB_DCR_EBC0_B1AP 0x0C840000
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#else
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#error "Illegal CPU speed"
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#endif
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#------------------------------------------------------------------------------
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FUNC_START( hal_hardware_init )
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mflr r30 // Save return address
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#ifndef CYG_HAL_STARTUP_RAM
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// Basic chip configuration
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lwi r3,MOAB_DCR_CPC0_CR0
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mtdcr DCR_CPC0_CR0,r3
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li r3,0x00000000
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mtdcr DCR_CPC0_CR1,r3
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lwi r3,0x60606000 // Edge conditioning register
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mtdcr DCR_CPC0_ECR,r3
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// Boot ROM access
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li r3,DCR_EBC0_B0AP // BOOT FLASH at 0xFFExxxxx, R/W
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lwi r4,0x05010480
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mtdcr DCR_EBC0_CFGADDR,r3
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mtdcr DCR_EBC0_CFGDATA,r4
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li r3,DCR_EBC0_B0CR
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lwi r4,0xFFE38000
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mtdcr DCR_EBC0_CFGADDR,r3
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mtdcr DCR_EBC0_CFGDATA,r4
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// GPIO
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// GPIO 13 - I - media present
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// GPIO 14 - O - main flash ALE
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// GPIO 15 - O - main flash CLE
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// GPIO 16 - O/x - watchdog
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// GPIO 17 - O - NAND CE
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// GPIO 24 - O - heartbeat LED
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lwi r4,GPIO_OR // Leave NAND not-selected, heartbeat off
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lwi r3,0x00004080
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stw r3,0(r4)
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lwi r4,GPIO_TCR // Tri-state control - enables outputs
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lwi r3,0x0003C080 // ... with watchdog enabled
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stw r3,0(r4)
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li r3,DCR_SDRAM0_CFG // See if SDRAM already configured
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mtdcr DCR_SDRAM0_CFGADDR,r3
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mfdcr r4,DCR_SDRAM0_CFGDATA
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lwi r3,MOAB_DCR_SDRAM0_CFG
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and r4,r4,r3
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cmpw r3,r4
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beq sdram_ok
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li r3,0x00000000 // Make sure nothing is cacheable
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mticcr r3
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mtdccr r3
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// Force data caches to be totally clean
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lwi r3,0
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lwi r4,0x8000
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10: dcbf 0,r3
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dccci 0,r3
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addi r3,r3,16
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cmpw r3,r4
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bne 10b
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// DRAM controller
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li r3,DCR_SDRAM0_CFG // Turn off controller to allow changes
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lwi r4,0x00000000
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mtdcr DCR_SDRAM0_CFGADDR,r3
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mtdcr DCR_SDRAM0_CFGDATA,r4
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li r3,DCR_SDRAM0_TR
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lwi r4,0x010A800E
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mtdcr DCR_SDRAM0_CFGADDR,r3
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mtdcr DCR_SDRAM0_CFGDATA,r4
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li r3,DCR_SDRAM0_RTR // Refresh timing
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lwi r4,MOAB_DCR_SDRAM0_RTR
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mtdcr DCR_SDRAM0_CFGADDR,r3
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mtdcr DCR_SDRAM0_CFGDATA,r4
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li r3,DCR_SDRAM0_B1CR // Note: non-ascending addresses because
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// the low 1/2 of memory fails on some boards
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lwi r4,MOAB_DCR_SDRAM0_B1CR
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mtdcr DCR_SDRAM0_CFGADDR,r3
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mtdcr DCR_SDRAM0_CFGDATA,r4
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li r3,DCR_SDRAM0_B0CR
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lwi r4,MOAB_DCR_SDRAM0_B0CR
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mtdcr DCR_SDRAM0_CFGADDR,r3
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mtdcr DCR_SDRAM0_CFGDATA,r4
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lwi r4,GPIO_OR // Turn heartbeat LED on
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lwi r3,0x00004000
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stw r3,0(r4)
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lwi r3,0xA000 // Pause for at least 200us
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mtctr r3
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13: nop
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bdnz 13b
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li r3,DCR_SDRAM0_CFG // Enable controller
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lwi r4,MOAB_DCR_SDRAM0_CFG
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mtdcr DCR_SDRAM0_CFGADDR,r3
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mtdcr DCR_SDRAM0_CFGDATA,r4
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sdram_ok:
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// Bus controller
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li r3,DCR_EBC0_B1AP // MAIN FLASH at 0xCxxxxxxx, R/W
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lwi r4,MOAB_DCR_EBC0_B1AP
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mtdcr DCR_EBC0_CFGADDR,r3
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mtdcr DCR_EBC0_CFGDATA,r4
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li r3,DCR_EBC0_B1CR
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lwi r4,0xC0018000 // 1MB, 8bits [actually only 1 byte!]
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mtdcr DCR_EBC0_CFGADDR,r3
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mtdcr DCR_EBC0_CFGDATA,r4
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// On-chip memory
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lwi r4,0xD0000000 // Instruction/Data at 0xD0XXXXXX..0xD7XXXXXX
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lwi r3,0x80000000
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mtdcr DCR_OCM0_ISARC,r4
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mtdcr DCR_OCM0_DSARC,r4
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mtdcr DCR_OCM0_ISCNTL,r3
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mtdcr DCR_OCM0_DSCNTL,r3
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lwi r4,GPIO_OR // Turn heartbeat LED off
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lwi r3,0x0000C080
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stw r3,0(r4)
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lwi r4,GPIO_TCR // Tri-state control - enables outputs
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lwi r3,0x00034080 // ... with watchdog disabled
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stw r3,0(r4)
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#endif // ROM or ROMRAM startup
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lwi r3,0x80000001 // DRAM can be cached - instructions only
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iccci 0,r3
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mticcr r3
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lwi r3,0x00000000
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mtdccr r3
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#ifdef CYG_HAL_STARTUP_ROMRAM
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// Copy image from ROM to RAM
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mr r6,r30
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lwi r7,0xFFF80000
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and r6,r6,r7
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subi r6,r6,4
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lwi r7,0-4 // where to copy to
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lwi r8,__ram_data_end
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10: lwzu r5,4(r6)
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stwu r5,4(r7)
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cmplw r7,r8
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bne 10b
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lwi r30,_hal_hardware_init_done
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#endif
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lwi r4,GPIO_OR // Turn heartbeat LED on
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lwi r3,0x00004000
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stw r3,0(r4)
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mtlr r30 // Restore return address
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blr
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FUNC_END( hal_hardware_init )
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.globl _hang
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_hang: nop
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b _hang
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blr
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#if 0
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.text
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.globl _get_cache_contents
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_get_cache_contents:
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subi r3,r3,4
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li r4,256
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mtctr r4
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li r4,0 // Address
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lwi r7,0xFFFFFFE0
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mfspr r5,SPR_CCR0
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10: and r5,r5,r7 // CIS=0,CWS=0 => DATA, WAY A
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mtspr SPR_CCR0,r5
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sync
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isync
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| 267 |
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dcread r6,0,r4
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| 268 |
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stwu r6,4(r3)
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| 269 |
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and r5,r5,r7 // CIS=0,CWS=1 => DATA, WAY B
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| 270 |
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ori r5,r5,0x01
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| 271 |
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mtspr SPR_CCR0,r5
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| 272 |
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sync
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isync
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mfspr r5,SPR_CCR0
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| 275 |
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dcread r6,0,r4
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| 276 |
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stwu r6,4(r3)
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| 277 |
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and r5,r5,r7 // CIS=1,CWS=0 => TAG, WAY A
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| 278 |
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ori r5,r5,0x10
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| 279 |
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mtspr SPR_CCR0,r5
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| 280 |
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sync
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| 281 |
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isync
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| 282 |
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dcread r6,0,r4
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| 283 |
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stwu r6,4(r3)
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| 284 |
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and r5,r5,r7 // CIS=1,CWS=1 => TAG, WAY B
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| 285 |
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ori r5,r5,0x11
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| 286 |
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mtspr SPR_CCR0,r5
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| 287 |
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sync
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| 288 |
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isync
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| 289 |
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dcread r6,0,r4
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| 290 |
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stwu r6,4(r3)
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| 291 |
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addi r4,r4,32
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| 292 |
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bdnz 10b
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| 293 |
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blr
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| 294 |
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#endif
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| 295 |
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| 296 |
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#ifndef CYG_HAL_STARTUP_RAM
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| 297 |
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.section ".reset_vector","ax"
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| 298 |
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ba 0xFFF80100
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.previous
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#endif
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| 301 |
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| 302 |
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#------------------------------------------------------------------------------
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# end of moab.S
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