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skrzyp |
#ifndef CYGONCE_HAL_VARIANT_INC
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#define CYGONCE_HAL_VARIANT_INC
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##=============================================================================
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##
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## variant.inc
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##
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## MPC8260 family assembler header file
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): pfine
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## Contributors:jskov
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## Date: 2001-12-12
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## Purpose: MPC8260 family definitions.
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## Description: This file contains various definitions and macros that are
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## useful for writing assembly code for the MPC8260 CPU family.
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## Usage:
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## #include
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## ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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##-----------------------------------------------------------------------------
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#ifndef SPRG0
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#define SPRG0 272 # Counter Register
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#endif
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#ifndef SPRG1
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#define SPRG1 273 # Counter Register
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#endif
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#ifndef SPRG2
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#define SPRG2 274 # Counter Register
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#endif
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#ifndef SPRG3
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#define SPRG3 275 # Counter Register
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#endif
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##-----------------------------------------------------------------------------
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## MPC8260 defined vectors
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.macro mpc8260_vector name
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.p2align 8
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.globl __exception_\name
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__exception_\name:
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#-------------------------------------------#
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# save off registers used in vector routine #
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#-------------------------------------------#
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mtspr SPRG3,r3 # save r3
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mfspr r3,8
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mtspr SPRG2,r3 # save LR
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#-----------------------------------------------------------------------
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# Load the vector offset value in SPRG0 for handler shifted down 8 bits.
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#-----------------------------------------------------------------------
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#addi r3,r0,0x0010
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addi r3,r0,__exception_\name@l #load low 16 bits of exception vector
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srawi r3,r3,8 #shift right by 8
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mtspr SPRG0,r3
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#---------------------------------------------------------
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# load link register in order to jump to physical address
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#---------------------------------------------------------
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addis r3,0,handler@h
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ori r3,r3,handler@l
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mtspr 8,r3
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bclr 20,0 # jump unconditionally to address in Link
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# Register (LR)
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.endm
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.macro infinite_loop_vector name
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.p2align 8
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.globl __exception_\name
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__exception_\name:
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mflr r0
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lwi r1,0x04700010
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lwi r2,0x12345678
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stw r0,0(r1)
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lwi r3,__exception_\name
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stw r3,4(r1)
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stw r2,8(r1)
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1:
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nop
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nop
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nop
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b 1b
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.endm
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.macro hal_reserved_vector_00000
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infinite_loop_vector reserved
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.endm
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#define CYG_HAL_RESERVED_VECTOR_00000
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.macro hal_extra_vectors
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infinite_loop_vector itbl_miss
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infinite_loop_vector dltlb_miss
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infinite_loop_vector dstlb_miss
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infinite_loop_vector iaddr_brkpt
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infinite_loop_vector sys_mngmnt_intrpt
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#if 0
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exception_vector reserved_01500
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exception_vector reserved_01600
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exception_vector reserved_01700
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exception_vector reserved_01800
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exception_vector reserved_01900
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exception_vector reserved_01a00
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exception_vector reserved_01b00
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exception_vector reserved_01c00
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exception_vector reserved_01d00
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exception_vector reserved_01e00
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exception_vector reserved_01f00
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exception_vector reserved_02000
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exception_vector reserved_02100
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exception_vector reserved_02200
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exception_vector reserved_02300
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exception_vector reserved_02400
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exception_vector reserved_02500
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exception_vector reserved_02600
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exception_vector reserved_02700
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exception_vector reserved_02800
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exception_vector reserved_02900
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exception_vector reserved_02a00
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exception_vector reserved_02b00
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exception_vector reserved_02c00
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exception_vector reserved_02d00
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exception_vector reserved_02e00
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exception_vector reserved_02f00
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#endif
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.endm
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#if 0
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## MPC8260 defined vectors
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# infinite_loop_vector macro
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.macro infinite_loop_vector name
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.p2align 8
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.globl __exception_\name
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__exception_\name:
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nop
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nop
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nop
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b __exception_\name
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.endm
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.macro hal_extra_vectors
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# MPC8260 vectors
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mpc8260_vector instruction_tlb_miss
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mpc8260_vector data_load_tlb_miss
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mpc8260_vector data_store_tlb_miss
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mpc8260_vector instruction_addr_brkpt
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mpc8260_vector system_mngmnt_intrpt
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.endm
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#endif
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##-----------------------------------------------------------------------------
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## MPC8260 CPU initialization
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##
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## Initialize CPU to a post-reset state, ensuring the ground doesn''t
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## shift under us while we try to set things up.
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.macro hal_cpu_init
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# Set up MSR (disable MMU for now)
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lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
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sync
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mtmsr r3
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sync
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.endm
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##-----------------------------------------------------------------------------
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## MPC8260 monitor initialization
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#ifndef CYGPKG_HAL_PPC_MON_DEFINED
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#if defined(CYG_HAL_STARTUP_ROM) || \
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( defined(CYG_HAL_STARTUP_RAM) && \
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!defined(CYGSEM_HAL_USE_ROM_MONITOR))
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.macro hal_mon_init
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#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
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# If we are starting up from ROM and want vectors in RAM
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# or we are starting in RAM and NOT using a ROM monitor,
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# copy exception handler code to 0.
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lwi r3,rom_vectors # r3 = rom start
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lwi r4,0 # r4 = ram start
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lwi r5,rom_vectors_end # r5 = rom end
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cmplw r3,r5 # skip if no vectors
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beq 2f
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subi r3,r3,4
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subi r4,r4,4
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subi r5,r5,4
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1:
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lwzu r0,4(r3) # get word from ROM
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stwu r0,4(r4) # store in RAM
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cmplw r3,r5 # compare
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blt 1b # loop if not yet done
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2:
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# Next initialize the VSR table. This happens whether the
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# vectors were copied to RAM or not.
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# First fill with exception handlers
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lwi r3,cyg_hal_default_exception_vsr
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lwi r4,hal_vsr_table
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subi r4,r4,4
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li r5,CYGNUM_HAL_VSR_COUNT
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1: stwu r3,4(r4)
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subi r5,r5,1
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cmpwi r5,0
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bne 1b
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#endif
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# Then fill in the special vectors
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lwi r3,cyg_hal_default_interrupt_vsr
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lwi r4,hal_vsr_table
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stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
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stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
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.endm
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#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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# Initialize the VSR table entries
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# We only take control of the interrupt vectors,
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# the rest are left to the ROM for now...
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.macro hal_mon_init
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lwi r3,cyg_hal_default_interrupt_vsr
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lwi r4,hal_vsr_table
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stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
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stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
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.endm
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#else
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.macro hal_mon_init
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.endm
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#endif
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#define CYGPKG_HAL_PPC_MON_DEFINED
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#endif // CYGPKG_HAL_PPC_MON_DEFINED
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##-----------------------------------------------------------------------------
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## MPC8260 exception state handling
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.macro hal_variant_save regs
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.endm
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.macro hal_variant_load regs
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.endm
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##-----------------------------------------------------------------------------
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## Indicate that the ISR tables are defined in variant.S
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#define CYG_HAL_PPC_ISR_TABLES_DEFINED
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##-----------------------------------------------------------------------------
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## MPC8260 interrupt handling.
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#ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED
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## First level decoding of MPC8xx SIU interrupt controller.
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# decode the interrupt
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.macro hal_intc_decode dreg,state
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#if 0
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lis r24,0x0471 # load register base
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lbz r24,CYGARC_REG_IMM_SIVEC(r24) # if
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//lwi \dreg,0x00ffff1c
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//stw r24,0(\dreg)
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stw r24,0(0)
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#endif
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lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
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rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21
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//stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
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//slwi \dreg,\dreg,2 # convert to byte offset.
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#if 1
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beq 0f # done if decrementer (vec 0)
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lis \dreg,0x0471 # load register base
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lbz \dreg,CYGARC_REG_IMM_SIVEC(\dreg) # if external, get SIU vector
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srwi \dreg,\dreg,2 # shift SIVEC value by 2
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//addi \dreg,\dreg,1 # Skip decrementer vector
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0: stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
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slwi \dreg,\dreg,2 # convert to byte offset.
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#endif
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.endm
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#define CYGPKG_HAL_POWERPC_INTC_DEFINED
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#endif // CYGPKG_HAL_POWERPC_INTC_DEFINED
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#------------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_VARIANT_INC
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# end of variant.inc
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