OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [powerpc/] [mpc8260/] [current/] [src/] [var_misc.c] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
//==========================================================================
2
//
3
//      var_misc.c
4
//
5
//      HAL implementation miscellaneous functions
6
//
7
//==========================================================================
8
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
9
// -------------------------------------------                              
10
// This file is part of eCos, the Embedded Configurable Operating System.   
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under    
14
// the terms of the GNU General Public License as published by the Free     
15
// Software Foundation; either version 2 or (at your option) any later      
16
// version.                                                                 
17
//
18
// eCos is distributed in the hope that it will be useful, but WITHOUT      
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
21
// for more details.                                                        
22
//
23
// You should have received a copy of the GNU General Public License        
24
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
25
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
26
//
27
// As a special exception, if other files instantiate templates or use      
28
// macros or inline functions from this file, or you compile this file      
29
// and link it with other works to produce a work based on this file,       
30
// this file does not by itself cause the resulting work to be covered by   
31
// the GNU General Public License. However the source code for this file    
32
// must still be made available in accordance with section (3) of the GNU   
33
// General Public License v2.                                               
34
//
35
// This exception does not invalidate any other reasons why a work based    
36
// on this file might be covered by the GNU General Public License.         
37
// -------------------------------------------                              
38
// ####ECOSGPLCOPYRIGHTEND####                                              
39
//==========================================================================
40
//#####DESCRIPTIONBEGIN####
41
//
42
// Author(s):    pfine
43
// Contributors: jskov
44
// Date:         2001-12-12
45
// Purpose:      HAL miscellaneous functions
46
// Description:  This file contains miscellaneous functions provided by the
47
//               HAL.
48
//
49
//####DESCRIPTIONEND####
50
//
51
//==========================================================================
52
 
53
#include <pkgconf/hal.h>
54
 
55
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
56
#include <cyg/hal/ppc_regs.h>
57
#include <cyg/infra/cyg_type.h>
58
 
59
#include <cyg/hal/hal_mem.h>
60
 
61
//--------------------------------------------------------------------------
62
void hal_variant_init(void)
63
{
64
}
65
 
66
 
67
//--------------------------------------------------------------------------
68
// Variant specific idle thread action.
69
bool
70
hal_variant_idle_thread_action( cyg_uint32 count )
71
{
72
    // Let architecture idle thread action run
73
    return true;
74
}
75
 
76
//---------------------------------------------------------------------------
77
// Use MMU resources to map memory regions.  
78
// Takes and returns an int used to ID the MMU resource to use. This ID
79
// is increased as resources are used and should be used for subsequent
80
// invocations.
81
int
82
cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys,
83
                    cyg_int32 size, cyg_uint8 flags)
84
{
85
    // Use BATs to map the memory.
86
    cyg_uint32 ubat, lbat;
87
 
88
    ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP;
89
    lbat = (phys & LBAT_BRPNMASK);
90
    if (flags & CYGARC_MEMDESC_CI)
91
        lbat |= LBAT_I;
92
    if (flags & CYGARC_MEMDESC_GUARDED)
93
        lbat |= LBAT_G;
94
#define IWASPATRICK
95
#ifdef IWASPATRICK
96
    lbat |= LBAT_PP_RW; // Always enable for Read-Write
97
#else
98
    if (flags & CYGARC_MEMDESC_RO) // Memory is Read Only
99
        lbat |= LBAT_PP_RO;
100
    if (flags & CYGARC_MEMDESC_RW) // Memory is RW 
101
        lbat |= LBAT_PP_RW;
102
#endif
103
    // There are 4 BATs, size is programmable.
104
    while (id < 4 && size > 0) {
105
        cyg_uint32 blk_size = 128*1024;
106
        cyg_uint32 bl = 0;
107
        while (blk_size < 256*1024*1024 && blk_size < size) {
108
            blk_size *= 2;
109
            bl = (bl << 1) | 1;
110
        }
111
        ubat = (ubat & ~UBAT_BLMASK) | (bl << 2);
112
 
113
        switch (id) {
114
        case 0:
115
            CYGARC_MTSPR (IBAT0U, ubat);
116
            CYGARC_MTSPR (IBAT0L, lbat);
117
            CYGARC_MTSPR (DBAT0U, ubat);
118
            CYGARC_MTSPR (DBAT0L, lbat);
119
            break;
120
        case 1:
121
            CYGARC_MTSPR (IBAT1U, ubat);
122
            CYGARC_MTSPR (IBAT1L, lbat);
123
            CYGARC_MTSPR (DBAT1U, ubat);
124
            CYGARC_MTSPR (DBAT1L, lbat);
125
            break;
126
        case 2:
127
            CYGARC_MTSPR (IBAT2U, ubat);
128
            CYGARC_MTSPR (IBAT2L, lbat);
129
            CYGARC_MTSPR (DBAT2U, ubat);
130
            CYGARC_MTSPR (DBAT2L, lbat);
131
            break;
132
        case 3:
133
            CYGARC_MTSPR (IBAT3U, ubat);
134
            CYGARC_MTSPR (IBAT3L, lbat);
135
            CYGARC_MTSPR (DBAT3U, ubat);
136
            CYGARC_MTSPR (DBAT3L, lbat);
137
            break;
138
        }
139
 
140
        size -= blk_size;
141
        id++;
142
    }
143
 
144
    return id;
145
}
146
 
147
 
148
// Initialize MMU to a sane (NOP) state.
149
void
150
cyg_hal_clear_MMU (void)
151
{
152
    cyg_uint32 ubat, lbat;
153
 
154
    // Initialize BATs with 0 -- VS&VP are unset, making all matches fail
155
    ubat = 0;
156
    lbat = 0;
157
 
158
    CYGARC_MTSPR (IBAT0U, ubat);
159
    CYGARC_MTSPR (IBAT0L, lbat);
160
    CYGARC_MTSPR (DBAT0U, ubat);
161
    CYGARC_MTSPR (DBAT0L, lbat);
162
    CYGARC_MTSPR (IBAT1U, ubat);
163
    CYGARC_MTSPR (IBAT1L, lbat);
164
    CYGARC_MTSPR (DBAT1U, ubat);
165
    CYGARC_MTSPR (DBAT1L, lbat);
166
    CYGARC_MTSPR (IBAT2U, ubat);
167
    CYGARC_MTSPR (IBAT2L, lbat);
168
    CYGARC_MTSPR (DBAT2U, ubat);
169
    CYGARC_MTSPR (DBAT2L, lbat);
170
    CYGARC_MTSPR (IBAT3U, ubat);
171
    CYGARC_MTSPR (IBAT3L, lbat);
172
    CYGARC_MTSPR (DBAT3U, ubat);
173
    CYGARC_MTSPR (DBAT3L, lbat);
174
}
175
 
176
//--------------------------------------------------------------------------
177
// End of var_misc.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.