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#ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
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#define CYGONCE_HAL_PPC_QUICC2_MPC8260_H
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//==========================================================================
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//
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// mpc8260.h
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//
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// PowerPC QUICC2 register definitions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Red Hat
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// Contributors: hmt, gthomas
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// Date: 1999-06-08
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// Purpose: PowerPC QUICC2 definitions
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// Description: PowerPC QUICC2 definitions
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// Usage: THIS IS NOT AN EXTERNAL API
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// This file is in the include dir to share it between
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// QUICCII serial code and MPC8260 initialization code.
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// #include <cyg/hal/mpc8260.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <cyg/hal/plf_regs.h> // For IMM base
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#define DPRAM_SMC1_OFFSET 0x2000
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#define DPRAM_SMC2_OFFSET 0x2100
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#define DPRAM_BD_OFFSET 0x2200
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#define _Packed
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#define _PackedType __attribute__((packed))
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/******************************************************************************
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*
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* PARAMETER RAM (PRAM) FOR EACH PERIPHERAL
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*
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* Each subsection contains protocol-specific PRAM for each peripheral,
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* followed by the PRAM common to all protocols for that peripheral. These
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* structs are used as needed in the main MPC8260 memory map structure. Note
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* that different modes of operation will require the use of different PRAM
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* structs, and that certain structs may overlay and conflict with the use of
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* other PRAM areas. Consult the MPC8260 User Manual for details as to what
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* is unavailable when certain protocols are run on certain peripherals.
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*
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******************************************************************************/
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/*---------------------------------------------------------------------------*/
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/* SERIAL COMMUNICATION CONTROLLER (SCC) */
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/*---------------------------------------------------------------------------*/
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/*----------*/
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/* SCC HDLC */
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/*----------*/
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typedef _Packed struct
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{
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CYG_BYTE reserved1[4]; /* Reserved area */
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CYG_WORD c_mask; /* CRC constant */
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CYG_WORD c_pres; /* CRC preset */
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CYG_WORD16 disfc; /* discarded frame counter */
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CYG_WORD16 crcec; /* CRC error counter */
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CYG_WORD16 abtsc; /* abort sequence counter */
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CYG_WORD16 nmarc; /* nonmatching address rx cnt */
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CYG_WORD16 retrc; /* frame transmission counter. */
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/* For FCC this area is reserved.*/
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CYG_WORD16 mflr; /* maximum frame length reg */
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CYG_WORD16 max_cnt; /* maximum length counter */
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CYG_WORD16 rfthr; /* received frames threshold */
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CYG_WORD16 rfcnt; /* received frames count */
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CYG_WORD16 hmask; /* user defined frm addr mask */
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CYG_WORD16 haddr1; /* user defined frm address 1 */
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CYG_WORD16 haddr2; /* user defined frm address 2 */
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CYG_WORD16 haddr3; /* user defined frm address 3 */
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CYG_WORD16 haddr4; /* user defined frm address 4 */
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CYG_WORD16 tmp; /* temp */
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CYG_WORD16 tmp_mb; /* temp */
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} _PackedType t_HdlcScc_Pram;
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/*--------------*/
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/* SCC Ethernet */
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/*--------------*/
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typedef _Packed struct
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{
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CYG_WORD c_pres; /* CRC preset */
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CYG_WORD c_mask; /* CRC constant mask*/
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CYG_WORD crcec; /* CRC error counter */
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CYG_WORD alec; /* alignment error counter */
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CYG_WORD disfc; /* discarded frame counter */
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CYG_WORD16 pads; /* Short frame pad character. */
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CYG_WORD16 ret_lim; /* Retry limit threshold. */
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CYG_WORD16 ret_cnt; /* Retry limit counter. */
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CYG_WORD16 mflr; /* maximum frame length reg */
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CYG_WORD16 minflr; /* minimum frame length reg */
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CYG_WORD16 maxd1; /* max DMA1 length register. */
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CYG_WORD16 maxd2; /* max DMA2 length register. */
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CYG_WORD16 maxd; /* Rx max DMA. */
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CYG_WORD16 dma_cnt; /* Rx DMA counter. */
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CYG_WORD16 max_b; /* max buffer descriptor byte count. */
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CYG_WORD16 gaddr1; /* group address filter */
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CYG_WORD16 gaddr2; /* group address filter */
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CYG_WORD16 gaddr3; /* group address filter */
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CYG_WORD16 gaddr4; /* group address filter */
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CYG_WORD tbuf0_data0; /* Saved area 0, current frame. */
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CYG_WORD tbuf0_data1; /* Saved area 1, current frame. */
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CYG_WORD tbuf0_rba0;
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CYG_WORD tbuf0_crc;
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CYG_WORD16 tbuf0_bcnt;
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CYG_WORD16 paddr1_h; /* physical address (MSB) */
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CYG_WORD16 paddr1_m; /* physical address */
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CYG_WORD16 paddr1_l; /* physical address (LSB) */
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CYG_WORD16 p_per; /* persistence */
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CYG_WORD16 rfbd_ptr; /* Rx first BD pointer. */
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CYG_WORD16 tfbd_ptr; /* Tx first BD pointer. */
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CYG_WORD16 tlbd_ptr; /* Tx last BD pointer. */
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CYG_WORD tbuf1_data0; /* Saved area 0, next frame. */
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CYG_WORD tbuf1_data1; /* Saved area 1, next frame. */
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CYG_WORD tbuf1_rba0;
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CYG_WORD tbuf1_crc;
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CYG_WORD16 tbuf1_bcnt;
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CYG_WORD16 tx_len; /* tx frame length counter */
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CYG_WORD16 iaddr1; /* individual address filter. */
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CYG_WORD16 iaddr2; /* individual address filter. */
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CYG_WORD16 iaddr3; /* individual address filter. */
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CYG_WORD16 iaddr4; /* individual address filter. */
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CYG_WORD16 boff_cnt; /* back-off counter */
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CYG_WORD16 taddr_h; /* temp address (MSB) */
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CYG_WORD16 taddr_m; /* temp address */
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CYG_WORD16 taddr_l; /* temp address (LSB) */
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} _PackedType t_EnetScc_Pram;
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/*----------*/
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/* SCC UART */
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/*----------*/
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typedef _Packed struct
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{
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CYG_BYTE reserved1[8]; /* Reserved area */
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CYG_WORD16 max_idl; /* maximum idle characters */
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CYG_WORD16 idlc; /* rx idle counter (internal) */
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CYG_WORD16 brkcr; /* break count register */
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CYG_WORD16 parec; /* Rx parity error counter */
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CYG_WORD16 frmec; /* Rx framing error counter */
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CYG_WORD16 nosec; /* Rx noise counter */
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CYG_WORD16 brkec; /* Rx break character counter */
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CYG_WORD16 brkln; /* Receive break length */
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CYG_WORD16 uaddr1; /* address character 1 */
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CYG_WORD16 uaddr2; /* address character 2 */
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CYG_WORD16 rtemp; /* temp storage */
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CYG_WORD16 toseq; /* Tx out of sequence char */
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CYG_WORD16 cc[8]; /* Rx control characters */
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CYG_WORD16 rccm; /* Rx control char mask */
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CYG_WORD16 rccr; /* Rx control char register */
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CYG_WORD16 rlbc; /* Receive last break char */
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} _PackedType t_UartScc_Pram;
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/*-----------------*/
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/* SCC Transparent */
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/*-----------------*/
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typedef _Packed struct
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{
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CYG_WORD c_mask; /* CRC constant */
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CYG_WORD c_pres; /* CRC preset */
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} _PackedType t_TransScc_Pram;
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/*------------*/
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/* SCC Bisync */
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/*------------*/
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typedef _Packed struct
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{
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CYG_BYTE reserved1[4]; /* Reserved area */
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CYG_WORD crcc; /* CRC Constant Temp Value */
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CYG_WORD16 prcrc; /* Preset Receiver CRC-16/LRC */
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CYG_WORD16 ptcrc; /* Preset Transmitter CRC-16/LRC */
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CYG_WORD16 parec; /* Receive Parity Error Counter */
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CYG_WORD16 bsync; /* BISYNC SYNC Character */
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CYG_WORD16 bdle; /* BISYNC DLE Character */
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CYG_WORD16 cc[8]; /* Rx control characters */
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CYG_WORD16 rccm; /* Receive Control Character Mask */
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} _PackedType t_BisyncScc_Pram;
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/*-----------------*/
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/* SCC Common PRAM */
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/*-----------------*/
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typedef _Packed struct
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{
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CYG_WORD16 rbase; /* RX BD base address */
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CYG_WORD16 tbase; /* TX BD base address */
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CYG_BYTE rfcr; /* Rx function code */
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CYG_BYTE tfcr; /* Tx function code */
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CYG_WORD16 mrblr; /* Rx buffer length */
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CYG_WORD rstate; /* Rx internal state */
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CYG_WORD rptr; /* Rx internal data pointer */
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CYG_WORD16 rbptr; /* rb BD Pointer */
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CYG_WORD16 rcount; /* Rx internal byte count */
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CYG_WORD rtemp; /* Rx temp */
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CYG_WORD tstate; /* Tx internal state */
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CYG_WORD tptr; /* Tx internal data pointer */
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CYG_WORD16 tbptr; /* Tx BD pointer */
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CYG_WORD16 tcount; /* Tx byte count */
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CYG_WORD ttemp; /* Tx temp */
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CYG_WORD rcrc; /* temp receive CRC */
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CYG_WORD tcrc; /* temp transmit CRC */
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union
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{
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t_HdlcScc_Pram h;
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t_EnetScc_Pram e;
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t_UartScc_Pram u;
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t_TransScc_Pram t;
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t_BisyncScc_Pram b;
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} SpecificProtocol;
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volatile CYG_BYTE COMPLETE_SIZE_OF_DPRAM_PAGE[0x5c];
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} _PackedType t_Scc_Pram;
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/*---------------------------------------------------------------------------*/
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/* FAST COMMUNICATION CONTROLLER (FCC) */
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/*---------------------------------------------------------------------------*/
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/*----------*/
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/* FCC HDLC */
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/*----------*/
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typedef _Packed struct
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{
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CYG_BYTE reserved1[8]; /* Reserved area */
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CYG_WORD c_mask; /* CRC constant */
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CYG_WORD c_pres; /* CRC preset */
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CYG_WORD16 disfc; /* discarded frame counter */
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CYG_WORD16 crcec; /* CRC error counter */
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CYG_WORD16 abtsc; /* abort sequence counter */
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CYG_WORD16 nmarc; /* nonmatching address rx cnt */
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CYG_WORD max_cnt; /* maximum length counter */
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CYG_WORD16 mflr; /* maximum frame length reg */
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CYG_WORD16 rfthr; /* received frames threshold */
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CYG_WORD16 rfcnt; /* received frames count */
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CYG_WORD16 hmask; /* user defined frm addr mask */
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CYG_WORD16 haddr1; /* user defined frm address 1 */
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CYG_WORD16 haddr2; /* user defined frm address 2 */
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CYG_WORD16 haddr3; /* user defined frm address 3 */
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CYG_WORD16 haddr4; /* user defined frm address 4 */
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CYG_WORD16 tmp; /* temp */
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CYG_WORD16 tmp_mb; /* temp */
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} _PackedType t_HdlcFcc_Pram;
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/*--------------*/
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/* FCC Ethernet */
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| 296 |
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/*--------------*/
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typedef _Packed struct
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{
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CYG_WORD stat_bus; /* Internal use buffer. */
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CYG_WORD cam_ptr; /* CAM address. */
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CYG_WORD c_mask; /* CRC constant mask*/
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CYG_WORD c_pres; /* CRC preset */
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CYG_WORD crcec; /* CRC error counter */
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CYG_WORD alec; /* alignment error counter */
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CYG_WORD disfc; /* discarded frame counter */
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CYG_WORD16 ret_lim; /* Retry limit threshold. */
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CYG_WORD16 ret_cnt; /* Retry limit counter. */
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CYG_WORD16 p_per; /* persistence */
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CYG_WORD16 boff_cnt; /* back-off counter */
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CYG_WORD gaddr_h; /* group address filter, high */
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CYG_WORD gaddr_l; /* group address filter, low */
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CYG_WORD16 tfcstat; /* out of sequece Tx BD staus. */
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| 314 |
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CYG_WORD16 tfclen; /* out of sequece Tx BD length. */
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| 315 |
|
|
CYG_WORD tfcptr; /* out of sequece Tx BD data pointer. */
|
| 316 |
|
|
CYG_WORD16 mflr; /* maximum frame length reg */
|
| 317 |
|
|
CYG_WORD16 paddr1_h; /* physical address (MSB) */
|
| 318 |
|
|
CYG_WORD16 paddr1_m; /* physical address */
|
| 319 |
|
|
CYG_WORD16 paddr1_l; /* physical address (LSB) */
|
| 320 |
|
|
CYG_WORD16 ibd_cnt; /* internal BD counter. */
|
| 321 |
|
|
CYG_WORD16 ibd_start; /* internal BD start pointer. */
|
| 322 |
|
|
CYG_WORD16 ibd_end; /* internal BD end pointer. */
|
| 323 |
|
|
CYG_WORD16 tx_len; /* tx frame length counter */
|
| 324 |
|
|
CYG_BYTE ibd_base[0x20]; /* internal micro code usage. */
|
| 325 |
|
|
CYG_WORD iaddr_h; /* individual address filter, high */
|
| 326 |
|
|
CYG_WORD iaddr_l; /* individual address filter, low */
|
| 327 |
|
|
CYG_WORD16 minflr; /* minimum frame length reg */
|
| 328 |
|
|
CYG_WORD16 taddr_h; /* temp address (MSB) */
|
| 329 |
|
|
CYG_WORD16 taddr_m; /* temp address */
|
| 330 |
|
|
CYG_WORD16 taddr_l; /* temp address (LSB) */
|
| 331 |
|
|
CYG_WORD16 pad_ptr; /* pad_ptr. */
|
| 332 |
|
|
CYG_WORD16 cf_type; /* flow control frame type coding. */
|
| 333 |
|
|
CYG_WORD16 cf_range; /* flow control frame range. */
|
| 334 |
|
|
CYG_WORD16 max_b; /* max buffer descriptor byte count. */
|
| 335 |
|
|
CYG_WORD16 maxd1; /* max DMA1 length register. */
|
| 336 |
|
|
CYG_WORD16 maxd2; /* max DMA2 length register. */
|
| 337 |
|
|
CYG_WORD16 maxd; /* Rx max DMA. */
|
| 338 |
|
|
CYG_WORD16 dma_cnt; /* Rx DMA counter. */
|
| 339 |
|
|
|
| 340 |
|
|
/* counter: */
|
| 341 |
|
|
CYG_WORD octc; /* received octets counter. */
|
| 342 |
|
|
CYG_WORD colc; /* estimated number of collisions */
|
| 343 |
|
|
CYG_WORD broc; /* received good packets of broadcast address */
|
| 344 |
|
|
CYG_WORD mulc; /* received good packets of multicast address */
|
| 345 |
|
|
CYG_WORD uspc; /* received packets shorter then 64 octets. */
|
| 346 |
|
|
CYG_WORD frgc; /* as uspc + bad packets */
|
| 347 |
|
|
CYG_WORD ospc; /* received packets longer then 1518 octets. */
|
| 348 |
|
|
CYG_WORD jbrc; /* as ospc + bad packets */
|
| 349 |
|
|
CYG_WORD p64c; /* received packets of 64 octets.. */
|
| 350 |
|
|
CYG_WORD p65c; /* received packets of 65-128 octets.. */
|
| 351 |
|
|
CYG_WORD p128c; /* received packets of 128-255 octets.. */
|
| 352 |
|
|
CYG_WORD p256c; /* received packets of 256-511 octets.. */
|
| 353 |
|
|
CYG_WORD p512c; /* received packets of 512-1023 octets.. */
|
| 354 |
|
|
CYG_WORD p1024c; /* received packets of 1024-1518 octets.. */
|
| 355 |
|
|
CYG_WORD cam_buf; /* cam respond internal buffer. */
|
| 356 |
|
|
CYG_WORD16 rfthr; /* received frames threshold */
|
| 357 |
|
|
CYG_WORD16 rfcnt; /* received frames count */
|
| 358 |
|
|
} _PackedType t_EnetFcc_Pram;
|
| 359 |
|
|
|
| 360 |
|
|
|
| 361 |
|
|
/*-----------------*/
|
| 362 |
|
|
/* FCC Common PRAM */
|
| 363 |
|
|
/*-----------------*/
|
| 364 |
|
|
|
| 365 |
|
|
typedef _Packed struct
|
| 366 |
|
|
{
|
| 367 |
|
|
CYG_WORD16 riptr; /* Rx internal temporary data pointer. */
|
| 368 |
|
|
CYG_WORD16 tiptr; /* Tx internal temporary data pointer. */
|
| 369 |
|
|
CYG_WORD16 reserved0; /* Reserved */
|
| 370 |
|
|
CYG_WORD16 mrblr; /* Rx buffer length */
|
| 371 |
|
|
CYG_WORD rstate; /* Rx internal state */
|
| 372 |
|
|
CYG_WORD rbase; /* RX BD base address */
|
| 373 |
|
|
CYG_WORD16 rbdstat; /* Rx BD status and control */
|
| 374 |
|
|
CYG_WORD16 rbdlen; /* Rx BD data length */
|
| 375 |
|
|
CYG_WORD rdptr; /* rx BD data pointer */
|
| 376 |
|
|
CYG_WORD tstate; /* Tx internal state */
|
| 377 |
|
|
CYG_WORD tbase; /* TX BD base address */
|
| 378 |
|
|
CYG_WORD16 tbdstat; /* Tx BD status and control */
|
| 379 |
|
|
CYG_WORD16 tbdlen; /* Tx BD data length */
|
| 380 |
|
|
CYG_WORD tdptr; /* Tx data pointer */
|
| 381 |
|
|
CYG_WORD rbptr; /* rx BD pointer */
|
| 382 |
|
|
CYG_WORD tbptr; /* Tx BD pointer */
|
| 383 |
|
|
CYG_WORD rcrc; /* Temp receive CRC */
|
| 384 |
|
|
CYG_WORD reserved_1[0x1];
|
| 385 |
|
|
CYG_WORD tcrc; /* Temp transmit CRC */
|
| 386 |
|
|
union /* Protocol-Specific parameter ram */
|
| 387 |
|
|
{
|
| 388 |
|
|
t_HdlcFcc_Pram h;
|
| 389 |
|
|
t_EnetFcc_Pram e;
|
| 390 |
|
|
} SpecificProtocol;
|
| 391 |
|
|
} _PackedType t_Fcc_Pram;
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
/*---------------------------------------------------------------------------*/
|
| 396 |
|
|
/* MULTICHANNEL COMMUNICATION CONTROLLER (MCC) */
|
| 397 |
|
|
/*---------------------------------------------------------------------------*/
|
| 398 |
|
|
|
| 399 |
|
|
/******************************************************************************
|
| 400 |
|
|
* Note that each MCC uses multiple logical channels. We first define the *
|
| 401 |
|
|
* PRAM for a logical channel (which can be used in either HDLC or Transparent *
|
| 402 |
|
|
* mode; wherever there are differences, it is specified), followed by the *
|
| 403 |
|
|
* PRAM for an MCC itself. *
|
| 404 |
|
|
******************************************************************************/
|
| 405 |
|
|
|
| 406 |
|
|
/*---------------------*/
|
| 407 |
|
|
/* MCC Logical Channel */
|
| 408 |
|
|
/*---------------------*/
|
| 409 |
|
|
|
| 410 |
|
|
typedef _Packed struct
|
| 411 |
|
|
{
|
| 412 |
|
|
CYG_WORD tstate; /* Tx internal state. */
|
| 413 |
|
|
CYG_WORD zistate; /* Zero insertion machine state. */
|
| 414 |
|
|
CYG_WORD zidata0; /* Zero insertion high CYG_WORD16. */
|
| 415 |
|
|
CYG_WORD zidata1; /* Zero insertion low CYG_WORD16. */
|
| 416 |
|
|
CYG_WORD16 tbdflags; /* Tx internal BD flags. */
|
| 417 |
|
|
CYG_WORD16 tbdcnt; /* Tx internal byte count . */
|
| 418 |
|
|
CYG_WORD tbdptr; /* Tx internal data pointer. */
|
| 419 |
|
|
CYG_WORD16 intmask; /* Interrupt mask flags. */
|
| 420 |
|
|
CYG_WORD16 chamr; /* channel mode register. */
|
| 421 |
|
|
CYG_WORD tcrc; /* Transparent: reserved. */
|
| 422 |
|
|
/* Hdlc: Temp receive CRC.*/
|
| 423 |
|
|
CYG_WORD rstate; /* Rx internal state. */
|
| 424 |
|
|
CYG_WORD zdstate; /* Zero deletion machine state. */
|
| 425 |
|
|
CYG_WORD zddata0; /* Zero deletion high CYG_WORD16. */
|
| 426 |
|
|
CYG_WORD zddata1; /* Zero deletion low CYG_WORD16. */
|
| 427 |
|
|
CYG_WORD16 rbdflags; /* Rx internal BD flags. */
|
| 428 |
|
|
CYG_WORD16 rbdcnt; /* Rx internal byte count . */
|
| 429 |
|
|
CYG_WORD rbdptr; /* Rx internal data pointer. */
|
| 430 |
|
|
CYG_WORD16 maxrlen; /* Transparent: Max receive buffer length. */
|
| 431 |
|
|
/* Hdlc: Max receive frame length. */
|
| 432 |
|
|
CYG_WORD16 sync_maxcnt;/* Transparent: Receive synchronization pattern*/
|
| 433 |
|
|
/* Hdlc: Max length counter. */
|
| 434 |
|
|
CYG_WORD rcrc; /* Transparent: reserved. */
|
| 435 |
|
|
/* Hdlc: Temp receive CRC.*/
|
| 436 |
|
|
} _PackedType t_Mch_Pram;
|
| 437 |
|
|
|
| 438 |
|
|
|
| 439 |
|
|
/*----------*/
|
| 440 |
|
|
/* MCC PRAM */
|
| 441 |
|
|
/*----------*/
|
| 442 |
|
|
|
| 443 |
|
|
typedef _Packed struct
|
| 444 |
|
|
{
|
| 445 |
|
|
CYG_WORD mccbase; /* A pointer to starting address of BD rings. */
|
| 446 |
|
|
CYG_WORD16 mccstate; /* Controller state. */
|
| 447 |
|
|
CYG_WORD16 mrblr; /* Maximum receive buffer length. */
|
| 448 |
|
|
CYG_WORD16 grfthr; /* Global receive frame threshold. */
|
| 449 |
|
|
CYG_WORD16 grfcnt; /* Global receive frame counter. */
|
| 450 |
|
|
CYG_WORD rinttmp; /* Temp location for receive interrupt table entry. */
|
| 451 |
|
|
CYG_WORD data0; /* Temporary location for holding data. */
|
| 452 |
|
|
CYG_WORD data1; /* Temporary location for holding data. */
|
| 453 |
|
|
CYG_WORD tintbase; /* Transmit interrupt table base address. */
|
| 454 |
|
|
CYG_WORD tintptr; /* Transmit interrupt table pointer. */
|
| 455 |
|
|
CYG_WORD tinttmp; /* Temp location for receive interrupt table entry. */
|
| 456 |
|
|
CYG_WORD16 sctpbase; /* A pointer to the super channel transmit table*/
|
| 457 |
|
|
CYG_BYTE res0[0x2]; /* Reserved area */
|
| 458 |
|
|
CYG_WORD c_mask32; /* CRC constant. */
|
| 459 |
|
|
CYG_WORD16 xtrabase; /* A pointer to the beginning of extra parameters */
|
| 460 |
|
|
CYG_WORD16 c_mask16; /* CRC constant. */
|
| 461 |
|
|
CYG_WORD rinttmp0; /* Temp location for receive interrupt table entry. */
|
| 462 |
|
|
CYG_WORD rinttmp1; /* Temp location for receive interrupt table entry. */
|
| 463 |
|
|
CYG_WORD rinttmp2; /* Temp location for receive interrupt table entry. */
|
| 464 |
|
|
CYG_WORD rinttmp3; /* Temp location for receive interrupt table entry. */
|
| 465 |
|
|
CYG_WORD rintbase0; /* Receive interrupt table base address. */
|
| 466 |
|
|
CYG_WORD rintptr0; /* Receive interrupt table pointer. */
|
| 467 |
|
|
CYG_WORD rintbase1; /* Receive interrupt table base address. */
|
| 468 |
|
|
CYG_WORD rintptr1; /* Receive interrupt table pointer. */
|
| 469 |
|
|
CYG_WORD rintbase2; /* Receive interrupt table base address. */
|
| 470 |
|
|
CYG_WORD rintptr2; /* Receive interrupt table pointer. */
|
| 471 |
|
|
CYG_WORD rintbase3; /* Receive interrupt table base address. */
|
| 472 |
|
|
CYG_WORD rintptr3; /* Receive interrupt table pointer. */
|
| 473 |
|
|
CYG_BYTE pad[0xa0];
|
| 474 |
|
|
} _PackedType t_Mcc_Pram;
|
| 475 |
|
|
|
| 476 |
|
|
|
| 477 |
|
|
|
| 478 |
|
|
/*---------------------------------------------------------------------------*/
|
| 479 |
|
|
/* ATM PARAMETER RAM */
|
| 480 |
|
|
/*---------------------------------------------------------------------------*/
|
| 481 |
|
|
|
| 482 |
|
|
|
| 483 |
|
|
/*--------------------------------------*/
|
| 484 |
|
|
/* Address Compression parameters table */
|
| 485 |
|
|
/*--------------------------------------*/
|
| 486 |
|
|
|
| 487 |
|
|
_Packed struct AddressCompressionPram
|
| 488 |
|
|
{
|
| 489 |
|
|
volatile CYG_WORD VptBase; /* VP-level addressing table base address */
|
| 490 |
|
|
volatile CYG_WORD VctBase; /* VC-level addressing table base address */
|
| 491 |
|
|
volatile CYG_WORD Vpt1Base; /* VP1-level addressing table base address */
|
| 492 |
|
|
volatile CYG_WORD Vct1Base; /* VC1-level addressing table base address */
|
| 493 |
|
|
volatile CYG_WORD16 VpMask; /* VP mask for address compression look-up */
|
| 494 |
|
|
} _PackedType;
|
| 495 |
|
|
|
| 496 |
|
|
|
| 497 |
|
|
/*-------------------------------*/
|
| 498 |
|
|
/* External CAM parameters table */
|
| 499 |
|
|
/*-------------------------------*/
|
| 500 |
|
|
|
| 501 |
|
|
_Packed struct ExtCamPram
|
| 502 |
|
|
{
|
| 503 |
|
|
volatile CYG_WORD ExtCamBase; /* Base address of the external CAM */
|
| 504 |
|
|
volatile CYG_BYTE reserved00[4]; /* Reserved */
|
| 505 |
|
|
volatile CYG_WORD ExtCam1Base; /* Base address of the external CAM1 */
|
| 506 |
|
|
volatile CYG_BYTE reserved01[6]; /* Reserved */
|
| 507 |
|
|
} _PackedType;
|
| 508 |
|
|
|
| 509 |
|
|
|
| 510 |
|
|
/*---------------------------*/
|
| 511 |
|
|
/* ATM mode parameters table */
|
| 512 |
|
|
/*---------------------------*/
|
| 513 |
|
|
|
| 514 |
|
|
typedef _Packed struct AtmPram
|
| 515 |
|
|
{
|
| 516 |
|
|
volatile CYG_BYTE reserved0[64]; /* Reserved */
|
| 517 |
|
|
volatile CYG_WORD16 RxCellTmpBase; /* Rx cell temporary base address */
|
| 518 |
|
|
volatile CYG_WORD16 TxCellTmpBase; /* Tx cell temporary base address */
|
| 519 |
|
|
volatile CYG_WORD16 UdcTmpBase; /* UDC temp base address (in UDC mode only) */
|
| 520 |
|
|
volatile CYG_WORD16 IntRctBase; /* Internal RTC base address */
|
| 521 |
|
|
volatile CYG_WORD16 IntTctBase; /* Internal TCT base address */
|
| 522 |
|
|
volatile CYG_WORD16 IntTcteBase; /* Internal ACT base address */
|
| 523 |
|
|
volatile CYG_BYTE reserved1[4]; /* reserved four bytes */
|
| 524 |
|
|
volatile CYG_WORD ExtRctBase; /* Extrnal RTC base address */
|
| 525 |
|
|
volatile CYG_WORD ExtTctBase; /* Extrnal TCT base address */
|
| 526 |
|
|
volatile CYG_WORD ExtTcteBase; /* Extrnal ACT base address */
|
| 527 |
|
|
volatile CYG_WORD16 UeadOffset; /* The offset in half-wordunits of the UEAD
|
| 528 |
|
|
entry in the UDC extra header. Should be
|
| 529 |
|
|
even address. If little-endian format is
|
| 530 |
|
|
used, the UeadOffset is of the little-endian
|
| 531 |
|
|
format. */
|
| 532 |
|
|
volatile CYG_BYTE reserved2[2]; /* Reserved */
|
| 533 |
|
|
volatile CYG_WORD16 PmtBase; /* Performance monitoring table base address */
|
| 534 |
|
|
volatile CYG_WORD16 ApcParamBase; /* APC Parameters table base address */
|
| 535 |
|
|
volatile CYG_WORD16 FbpParamBase; /* Free buffer pool parameters base address */
|
| 536 |
|
|
volatile CYG_WORD16 IntQParamBase; /* Interrupt queue parameters table base */
|
| 537 |
|
|
volatile CYG_BYTE reserved3[2];
|
| 538 |
|
|
volatile CYG_WORD16 UniStatTableBase; /* UNI statistics table base */
|
| 539 |
|
|
volatile CYG_WORD BdBaseExt; /* BD ring base address extension */
|
| 540 |
|
|
union
|
| 541 |
|
|
{
|
| 542 |
|
|
struct AddressCompressionPram AddrCompression;
|
| 543 |
|
|
struct ExtCamPram ExtCam;
|
| 544 |
|
|
} AddrMapping; /* Address look-up mechanism */
|
| 545 |
|
|
volatile CYG_WORD16 VciFiltering; /* VCI filtering enable bits. If bit i is set,
|
| 546 |
|
|
the cell with VCI=i will be sent to the
|
| 547 |
|
|
raw cell queue. The bits 0-2 and 5 should
|
| 548 |
|
|
be zero. */
|
| 549 |
|
|
volatile CYG_WORD16 Gmode; /* Global mode */
|
| 550 |
|
|
volatile CYG_WORD16 CommInfo1; /* The information field associated with the */
|
| 551 |
|
|
volatile CYG_WORD CommInfo2; /* last host command */
|
| 552 |
|
|
volatile CYG_BYTE reserved4[4]; /* Reserved */
|
| 553 |
|
|
volatile CYG_WORD CRC32Preset; /* Preset for CRC32 */
|
| 554 |
|
|
volatile CYG_WORD CRC32Mask; /* Constant mask for CRC32 */
|
| 555 |
|
|
volatile CYG_WORD16 AAL1SnpTableBase; /* AAl1 SNP protection look-up table base */
|
| 556 |
|
|
volatile CYG_WORD16 reserved5; /* Reserved */
|
| 557 |
|
|
volatile CYG_WORD SrtsBase; /* External SRTS logic base address. For AAL1
|
| 558 |
|
|
only. Should be 16 bytes aligned */
|
| 559 |
|
|
volatile CYG_WORD16 IdleBase; /* Idle cell base address */
|
| 560 |
|
|
volatile CYG_WORD16 IdleSize; /* Idle cell size: 52, 56, 60, 64 */
|
| 561 |
|
|
volatile CYG_WORD EmptyCellPayload; /* Empty cell payload (little-indian) */
|
| 562 |
|
|
|
| 563 |
|
|
/* ABR specific only */
|
| 564 |
|
|
volatile CYG_WORD Trm; /* Upper bound on time between F-RM cells for active source */
|
| 565 |
|
|
volatile CYG_WORD16 Nrm; /* Controls the maximum data cells sent for each F-RM cell. */
|
| 566 |
|
|
volatile CYG_WORD16 Mrm; /* Controls bandwidth between F-RM, B-RM and user data cell */
|
| 567 |
|
|
volatile CYG_WORD16 Tcr; /* Tag cell rate */
|
| 568 |
|
|
volatile CYG_WORD16 AbrRxTcte; /* ABR reserved area address (2-CYG_WORD16 aligned)*/
|
| 569 |
|
|
volatile CYG_BYTE reserved7[76]; /* Reserved */
|
| 570 |
|
|
} _PackedType t_Atm_Pram;
|
| 571 |
|
|
|
| 572 |
|
|
|
| 573 |
|
|
|
| 574 |
|
|
/*---------------------------------------------------------------------------*/
|
| 575 |
|
|
/* SERIAL MANAGEMENT CHANNEL (SMC) */
|
| 576 |
|
|
/*---------------------------------------------------------------------------*/
|
| 577 |
|
|
|
| 578 |
|
|
typedef _Packed struct
|
| 579 |
|
|
{
|
| 580 |
|
|
CYG_WORD16 rbase; /* Rx BD Base Address */
|
| 581 |
|
|
CYG_WORD16 tbase; /* Tx BD Base Address */
|
| 582 |
|
|
CYG_BYTE rfcr; /* Rx function code */
|
| 583 |
|
|
CYG_BYTE tfcr; /* Tx function code */
|
| 584 |
|
|
CYG_WORD16 mrblr; /* Rx buffer length */
|
| 585 |
|
|
CYG_WORD rstate; /* Rx internal state */
|
| 586 |
|
|
CYG_WORD rptr; /* Rx internal data pointer */
|
| 587 |
|
|
CYG_WORD16 rbptr; /* rb BD Pointer */
|
| 588 |
|
|
CYG_WORD16 rcount; /* Rx internal byte count */
|
| 589 |
|
|
CYG_WORD rtemp; /* Rx temp */
|
| 590 |
|
|
CYG_WORD tstate; /* Tx internal state */
|
| 591 |
|
|
CYG_WORD tptr; /* Tx internal data pointer */
|
| 592 |
|
|
CYG_WORD16 tbptr; /* Tx BD pointer */
|
| 593 |
|
|
CYG_WORD16 tcount; /* Tx byte count */
|
| 594 |
|
|
CYG_WORD ttemp; /* Tx temp */
|
| 595 |
|
|
|
| 596 |
|
|
/* SMC UART-specific PRAM */
|
| 597 |
|
|
CYG_WORD16 max_idl; /* Maximum IDLE Characters */
|
| 598 |
|
|
CYG_WORD16 idlc; /* Temporary IDLE Counter */
|
| 599 |
|
|
CYG_WORD16 brkln; /* Last Rx Break Length */
|
| 600 |
|
|
CYG_WORD16 brkec; /* Rx Break Condition Counter */
|
| 601 |
|
|
CYG_WORD16 brkcr; /* Break Count Register (Tx) */
|
| 602 |
|
|
CYG_WORD16 r_mask; /* Temporary bit mask */
|
| 603 |
|
|
|
| 604 |
|
|
} _PackedType t_Smc_Pram;
|
| 605 |
|
|
|
| 606 |
|
|
|
| 607 |
|
|
|
| 608 |
|
|
/*---------------------------------------------------------------------------*/
|
| 609 |
|
|
/* IDMA PARAMETER RAM */
|
| 610 |
|
|
/*---------------------------------------------------------------------------*/
|
| 611 |
|
|
|
| 612 |
|
|
typedef _Packed struct
|
| 613 |
|
|
{
|
| 614 |
|
|
CYG_WORD16 ibase; /* IDMA BD Base Address */
|
| 615 |
|
|
CYG_WORD16 dcm; /* DMA channel mode register */
|
| 616 |
|
|
CYG_WORD16 ibdptr; /* next bd ptr */
|
| 617 |
|
|
CYG_WORD16 DPR_buf; /* ptr to internal 64 byte buffer */
|
| 618 |
|
|
CYG_WORD16 BUF_inv; /* The quantity of data in DPR_buf */
|
| 619 |
|
|
CYG_WORD16 SS_max; /* Steady State Max. transfer size */
|
| 620 |
|
|
CYG_WORD16 DPR_in_ptr; /* write ptr for the internal buffer */
|
| 621 |
|
|
CYG_WORD16 sts; /* Source Transfer Size */
|
| 622 |
|
|
CYG_WORD16 DPR_out_ptr; /* read ptr for the internal buffer */
|
| 623 |
|
|
CYG_WORD16 seob; /* Source end of burst */
|
| 624 |
|
|
CYG_WORD16 deob; /* Destination end of burst */
|
| 625 |
|
|
CYG_WORD16 dts; /* Destination Transfer Size */
|
| 626 |
|
|
CYG_WORD16 RetAdd; /* return address when ERM==1 */
|
| 627 |
|
|
CYG_WORD16 Reserved; /* reserved */
|
| 628 |
|
|
CYG_WORD BD_cnt; /* Internal byte count */
|
| 629 |
|
|
CYG_WORD S_ptr; /* source internal data ptr */
|
| 630 |
|
|
CYG_WORD D_ptr; /* destination internal data ptr */
|
| 631 |
|
|
CYG_WORD istate; /* Internal state */
|
| 632 |
|
|
|
| 633 |
|
|
} _PackedType t_Idma_Pram;
|
| 634 |
|
|
|
| 635 |
|
|
|
| 636 |
|
|
|
| 637 |
|
|
/*-------------------------------------------------------------------*/
|
| 638 |
|
|
/* INTER-INTEGRATED CIRCUIT (I2C) */
|
| 639 |
|
|
/*-------------------------------------------------------------------*/
|
| 640 |
|
|
|
| 641 |
|
|
typedef _Packed struct
|
| 642 |
|
|
{
|
| 643 |
|
|
CYG_WORD16 rbase; /* RX BD base address */
|
| 644 |
|
|
CYG_WORD16 tbase; /* TX BD base address */
|
| 645 |
|
|
CYG_BYTE rfcr; /* Rx function code */
|
| 646 |
|
|
CYG_BYTE tfcr; /* Tx function code */
|
| 647 |
|
|
CYG_WORD16 mrblr; /* Rx buffer length */
|
| 648 |
|
|
CYG_WORD rstate; /* Rx internal state */
|
| 649 |
|
|
CYG_WORD rptr; /* Rx internal data pointer */
|
| 650 |
|
|
CYG_WORD16 rbptr; /* rb BD Pointer */
|
| 651 |
|
|
CYG_WORD16 rcount; /* Rx internal byte count */
|
| 652 |
|
|
CYG_WORD rtemp; /* Rx temp */
|
| 653 |
|
|
CYG_WORD tstate; /* Tx internal state */
|
| 654 |
|
|
CYG_WORD tptr; /* Tx internal data pointer */
|
| 655 |
|
|
CYG_WORD16 tbptr; /* Tx BD pointer */
|
| 656 |
|
|
CYG_WORD16 tcount; /* Tx byte count */
|
| 657 |
|
|
CYG_WORD ttemp; /* Tx temp */
|
| 658 |
|
|
|
| 659 |
|
|
} _PackedType t_I2c_Pram;
|
| 660 |
|
|
|
| 661 |
|
|
|
| 662 |
|
|
|
| 663 |
|
|
/*---------------------------------------------------------------------------*/
|
| 664 |
|
|
/* SERIAL PERIPHERAL INTERFACE (SPI) */
|
| 665 |
|
|
/*---------------------------------------------------------------------------*/
|
| 666 |
|
|
|
| 667 |
|
|
typedef _Packed struct
|
| 668 |
|
|
{
|
| 669 |
|
|
CYG_WORD16 rbase; /* Rx BD Base Address */
|
| 670 |
|
|
CYG_WORD16 tbase; /* Tx BD Base Address */
|
| 671 |
|
|
CYG_BYTE rfcr; /* Rx function code */
|
| 672 |
|
|
CYG_BYTE tfcr; /* Tx function code */
|
| 673 |
|
|
CYG_WORD16 mrblr; /* Rx buffer length */
|
| 674 |
|
|
CYG_WORD rstate; /* Rx internal state */
|
| 675 |
|
|
CYG_WORD rptr; /* Rx internal data pointer */
|
| 676 |
|
|
CYG_WORD16 rbptr; /* Rx BD Pointer */
|
| 677 |
|
|
CYG_WORD16 rcount; /* Rx internal byte count */
|
| 678 |
|
|
CYG_WORD rtemp; /* Rx temp */
|
| 679 |
|
|
CYG_WORD tstate; /* Tx internal state */
|
| 680 |
|
|
CYG_WORD tptr; /* Tx internal data pointer */
|
| 681 |
|
|
CYG_WORD16 tbptr; /* Tx BD pointer */
|
| 682 |
|
|
CYG_WORD16 tcount; /* Tx byte count */
|
| 683 |
|
|
CYG_WORD ttemp; /* Tx temp */
|
| 684 |
|
|
CYG_BYTE reserved[8];
|
| 685 |
|
|
|
| 686 |
|
|
} _PackedType t_Spi_Pram;
|
| 687 |
|
|
|
| 688 |
|
|
|
| 689 |
|
|
|
| 690 |
|
|
/*---------------------------------------------------------------------------*/
|
| 691 |
|
|
/* RISC TIMER PARAMETER RAM */
|
| 692 |
|
|
/*---------------------------------------------------------------------------*/
|
| 693 |
|
|
|
| 694 |
|
|
typedef _Packed struct
|
| 695 |
|
|
{
|
| 696 |
|
|
|
| 697 |
|
|
CYG_WORD16 tm_base; /* RISC timer table base adr */
|
| 698 |
|
|
CYG_WORD16 tm_ptr; /* RISC timer table pointer */
|
| 699 |
|
|
CYG_WORD16 r_tmr; /* RISC timer mode register */
|
| 700 |
|
|
CYG_WORD16 r_tmv; /* RISC timer valid register */
|
| 701 |
|
|
CYG_WORD tm_cmd; /* RISC timer cmd register */
|
| 702 |
|
|
CYG_WORD tm_cnt; /* RISC timer internal cnt */
|
| 703 |
|
|
} _PackedType t_timer_pram;
|
| 704 |
|
|
|
| 705 |
|
|
|
| 706 |
|
|
|
| 707 |
|
|
/*--------------------------------------------------------------------------*/
|
| 708 |
|
|
/* ROM MICROCODE PARAMETER RAM AREA */
|
| 709 |
|
|
/*--------------------------------------------------------------------------*/
|
| 710 |
|
|
|
| 711 |
|
|
typedef _Packed struct
|
| 712 |
|
|
{
|
| 713 |
|
|
CYG_WORD16 rev_num; /* Ucode Revision Number */
|
| 714 |
|
|
CYG_WORD16 d_ptr; /* MISC Dump area pointer */
|
| 715 |
|
|
} _PackedType t_ucode_pram;
|
| 716 |
|
|
|
| 717 |
|
|
/*--------------------------------------------------------------------------*/
|
| 718 |
|
|
/* MAIN DEFINITION OF MPC8260 INTERNAL MEMORY MAP */
|
| 719 |
|
|
/*--------------------------------------------------------------------------*/
|
| 720 |
|
|
|
| 721 |
|
|
typedef _Packed struct
|
| 722 |
|
|
{
|
| 723 |
|
|
|
| 724 |
|
|
/* cpm_ram */
|
| 725 |
|
|
t_Mch_Pram mch_pram[256]; /* MCC logical channels parameter ram */
|
| 726 |
|
|
volatile CYG_BYTE reserved0[0x4000]; /* Reserved area */
|
| 727 |
|
|
|
| 728 |
|
|
/* DPR_BASE+0x8000*/
|
| 729 |
|
|
union
|
| 730 |
|
|
{
|
| 731 |
|
|
|
| 732 |
|
|
/*for access to the PRAM structs for SCCs, FCCs, and MCCs */
|
| 733 |
|
|
struct serials
|
| 734 |
|
|
{
|
| 735 |
|
|
t_Scc_Pram scc_pram[4];
|
| 736 |
|
|
t_Fcc_Pram fcc_pram[3];
|
| 737 |
|
|
t_Mcc_Pram mcc_pram[2];
|
| 738 |
|
|
volatile CYG_BYTE reserved1[0x700];
|
| 739 |
|
|
} serials;
|
| 740 |
|
|
|
| 741 |
|
|
/* for access to ATM PRAM structs */
|
| 742 |
|
|
struct atm
|
| 743 |
|
|
{
|
| 744 |
|
|
volatile CYG_BYTE reserved2[0x400];
|
| 745 |
|
|
t_Atm_Pram atm_pram[2];
|
| 746 |
|
|
volatile CYG_BYTE reserved3[0xa00];
|
| 747 |
|
|
} atm;
|
| 748 |
|
|
|
| 749 |
|
|
/* for access to the memory locations holding user-defined
|
| 750 |
|
|
base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */
|
| 751 |
|
|
struct standard
|
| 752 |
|
|
{
|
| 753 |
|
|
volatile CYG_BYTE scc1[0x100];
|
| 754 |
|
|
volatile CYG_BYTE scc2[0x100];
|
| 755 |
|
|
volatile CYG_BYTE scc3[0x100];
|
| 756 |
|
|
volatile CYG_BYTE scc4[0x100];
|
| 757 |
|
|
volatile CYG_BYTE fcc1[0x100];
|
| 758 |
|
|
volatile CYG_BYTE fcc2[0x100];
|
| 759 |
|
|
volatile CYG_BYTE fcc3[0x100];
|
| 760 |
|
|
volatile CYG_BYTE mcc1[0x80];
|
| 761 |
|
|
volatile CYG_BYTE reserved_0[0x7c];
|
| 762 |
|
|
volatile CYG_WORD16 smc1; // Pointer to SMC1 DPRAM
|
| 763 |
|
|
volatile CYG_BYTE idma1[0x2];
|
| 764 |
|
|
volatile CYG_BYTE mcc2[0x80];
|
| 765 |
|
|
volatile CYG_BYTE reserved_1[0x7c];
|
| 766 |
|
|
volatile CYG_WORD16 smc2; // Pointer to SMC2 DPRAM
|
| 767 |
|
|
volatile CYG_BYTE idma2[0x2];
|
| 768 |
|
|
volatile CYG_BYTE reserved_2[0xfc];
|
| 769 |
|
|
volatile CYG_BYTE spi[0x2];
|
| 770 |
|
|
volatile CYG_BYTE idma3[0x2];
|
| 771 |
|
|
volatile CYG_BYTE reserved_3[0xe0];
|
| 772 |
|
|
volatile CYG_BYTE timers[0x10];
|
| 773 |
|
|
volatile CYG_BYTE Rev_num[0x2];
|
| 774 |
|
|
volatile CYG_BYTE D_ptr[0x2];
|
| 775 |
|
|
volatile CYG_BYTE reserved_4[0x4];
|
| 776 |
|
|
volatile CYG_BYTE rand[0x4];
|
| 777 |
|
|
volatile CYG_BYTE i2c[0x2];
|
| 778 |
|
|
volatile CYG_BYTE idma4[0x2];
|
| 779 |
|
|
volatile CYG_BYTE reserved_5[0x500];
|
| 780 |
|
|
} standard;
|
| 781 |
|
|
|
| 782 |
|
|
} pram;
|
| 783 |
|
|
|
| 784 |
|
|
volatile CYG_BYTE reserved11[0x2000]; /* Reserved area */
|
| 785 |
|
|
volatile CYG_BYTE cpm_ram_dpram_2[0x1000]; /* Internal RAM */
|
| 786 |
|
|
volatile CYG_BYTE reserved12[0x4000]; /* Reserved area */
|
| 787 |
|
|
|
| 788 |
|
|
/* siu */
|
| 789 |
|
|
volatile CYG_WORD siu_siumcr; /* SIU Module Configuration Register */
|
| 790 |
|
|
volatile CYG_WORD siu_sypcr; /* System Protection Control Register */
|
| 791 |
|
|
volatile CYG_BYTE reserved13[0x6]; /* Reserved area */
|
| 792 |
|
|
volatile CYG_WORD16 siu_swsr; /* Software Service Register */
|
| 793 |
|
|
|
| 794 |
|
|
/* buses */
|
| 795 |
|
|
volatile CYG_BYTE reserved14[0x14]; /* Reserved area */
|
| 796 |
|
|
volatile CYG_WORD bcr; /* Bus Configuration Register */
|
| 797 |
|
|
volatile CYG_BYTE ppc_acr; /* Arbiter Configuration Register */
|
| 798 |
|
|
volatile CYG_BYTE reserved15[0x3]; /* Reserved area */
|
| 799 |
|
|
volatile CYG_WORD ppc_alrh; /* Arbitration level Register (First clients)*/
|
| 800 |
|
|
volatile CYG_WORD ppc_alrl; /* Arbitration Level Register (Next clients) */
|
| 801 |
|
|
volatile CYG_BYTE lcl_acr; /* LCL Arbiter Configuration Register */
|
| 802 |
|
|
volatile CYG_BYTE reserved16[0x3]; /* Reserved area */
|
| 803 |
|
|
volatile CYG_WORD lcl_alrh; /* LCL Arbitration level Register (First clients)*/
|
| 804 |
|
|
volatile CYG_WORD lcl_alrl; /* LCL Arbitration Level Register (Next clients) */
|
| 805 |
|
|
volatile CYG_WORD tescr1; /* PPC bus transfer error status control register 1 */
|
| 806 |
|
|
volatile CYG_WORD tescr2; /* PPC bus transfer error status control register 2 */
|
| 807 |
|
|
volatile CYG_WORD ltescr1; /* Local bus transfer error status control register 1 */
|
| 808 |
|
|
volatile CYG_WORD ltescr2; /* Local bus transfer error status control register 2 */
|
| 809 |
|
|
volatile CYG_WORD pdtea; /* PPC bus DMA Transfer Error Address */
|
| 810 |
|
|
volatile CYG_BYTE pdtem; /* PPC bus DMA Transfer Error MSNUM */
|
| 811 |
|
|
volatile CYG_BYTE reserved17[0x3]; /* Reserved area */
|
| 812 |
|
|
volatile CYG_WORD ldtea; /* PPC bus DMA Transfer Error Address */
|
| 813 |
|
|
volatile CYG_BYTE ldtem; /* PPC bus DMA Transfer Error MSNUM */
|
| 814 |
|
|
volatile CYG_BYTE reserved18[0xa3]; /* Reserved area */
|
| 815 |
|
|
|
| 816 |
|
|
/* memc */
|
| 817 |
|
|
struct mem_regs
|
| 818 |
|
|
{
|
| 819 |
|
|
volatile CYG_WORD memc_br; /* Base Register */
|
| 820 |
|
|
volatile CYG_WORD memc_or; /* Option Register */
|
| 821 |
|
|
} mem_regs[12];
|
| 822 |
|
|
volatile CYG_BYTE reserved19[0x8]; /* Reserved area */
|
| 823 |
|
|
volatile CYG_WORD memc_mar; /* Memory Address Register */
|
| 824 |
|
|
volatile CYG_BYTE reserved20[0x4]; /* Reserved area */
|
| 825 |
|
|
volatile CYG_WORD memc_mamr; /* Machine A Mode Register */
|
| 826 |
|
|
volatile CYG_WORD memc_mbmr; /* Machine B Mode Register */
|
| 827 |
|
|
volatile CYG_WORD memc_mcmr; /* Machine C Mode Register */
|
| 828 |
|
|
volatile CYG_WORD memc_mdmr; /* Machine D Mode Register */
|
| 829 |
|
|
volatile CYG_BYTE reserved21[0x4]; /* Reserved area */
|
| 830 |
|
|
volatile CYG_WORD16 memc_mptpr; /* Memory Periodic Timer Prescaler */
|
| 831 |
|
|
volatile CYG_BYTE reserved22[0x2]; /* Reserved area */
|
| 832 |
|
|
volatile CYG_WORD memc_mdr; /* Memory Data Register */
|
| 833 |
|
|
volatile CYG_BYTE reserved23[0x4]; /* Reserved area */
|
| 834 |
|
|
volatile CYG_WORD memc_psdmr; /* PowerPC Bus SDRAM machine Mode Register */
|
| 835 |
|
|
volatile CYG_WORD memc_lsdmr; /* Local Bus SDRAM machine Mode Registe */
|
| 836 |
|
|
volatile CYG_BYTE memc_purt; /* PowerPC Bus assigned UPM Refresh Timer */
|
| 837 |
|
|
volatile CYG_BYTE reserved24[0x3]; /* Reserved area */
|
| 838 |
|
|
volatile CYG_BYTE memc_psrt; /* PowerPC BusBus assigned SDRAM Refresh Timer */
|
| 839 |
|
|
volatile CYG_BYTE reserved25[0x3]; /* Reserved area */
|
| 840 |
|
|
volatile CYG_BYTE memc_lurt; /* Local Bus assigned UPM Refresh Timer */
|
| 841 |
|
|
volatile CYG_BYTE reserved26[0x3]; /* Reserved area */
|
| 842 |
|
|
volatile CYG_BYTE memc_lsrt; /* Local Bus assigned SDRAM Refresh Timer */
|
| 843 |
|
|
volatile CYG_BYTE reserved27[0x3]; /* Reserved area */
|
| 844 |
|
|
volatile CYG_WORD memc_immr; /* Internal Memory Map Register */
|
| 845 |
|
|
|
| 846 |
|
|
/* pci */
|
| 847 |
|
|
volatile CYG_WORD pcibr0; /* Base address+valid for PCI window 1 */
|
| 848 |
|
|
volatile CYG_WORD pcibr1; /* Base address+valid for PCI window 2 */
|
| 849 |
|
|
volatile CYG_BYTE reserved28[0x10]; /* Reserved area */
|
| 850 |
|
|
volatile CYG_WORD pcimsk0; /* Mask for PCI window 1 */
|
| 851 |
|
|
volatile CYG_WORD pcimsk1; /* Mask for PCI window 2 */
|
| 852 |
|
|
volatile CYG_BYTE reserved29[0x54]; /* Reserved area */
|
| 853 |
|
|
|
| 854 |
|
|
/* si_timers */
|
| 855 |
|
|
volatile CYG_WORD16 si_timers_tmcntsc; /* Time Counter Status and Control Register */
|
| 856 |
|
|
volatile CYG_BYTE reserved30[0x2]; /* Reserved area */
|
| 857 |
|
|
volatile CYG_WORD si_timers_tmcnt; /* Time Counter Register */
|
| 858 |
|
|
volatile CYG_WORD si_timers_tmcntsec; /* Time Counter Seconds*/
|
| 859 |
|
|
volatile CYG_WORD si_timers_tmcntal; /* Time Counter Alarm Register */
|
| 860 |
|
|
volatile CYG_BYTE reserved31[0x10]; /* Reserved area */
|
| 861 |
|
|
volatile CYG_WORD16 si_timers_piscr; /* Periodic Interrupt Status and Control Reg. */
|
| 862 |
|
|
volatile CYG_BYTE reserved32[0x2]; /* Reserved area */
|
| 863 |
|
|
volatile CYG_WORD si_timers_pitc; /* Periodic Interrupt Count Register */
|
| 864 |
|
|
volatile CYG_WORD si_timers_pitr; /* Periodic Interrupt Timer Register */
|
| 865 |
|
|
volatile CYG_BYTE reserved33[0x54]; /* Reserved area */
|
| 866 |
|
|
|
| 867 |
|
|
/* test module registers */
|
| 868 |
|
|
volatile CYG_WORD tstmhr;
|
| 869 |
|
|
volatile CYG_WORD tstmlr;
|
| 870 |
|
|
volatile CYG_WORD16 tster;
|
| 871 |
|
|
volatile CYG_BYTE reserved34[0x156]; /* Reserved area */
|
| 872 |
|
|
|
| 873 |
|
|
/* pci, part 2 */
|
| 874 |
|
|
volatile CYG_WORD pci_pci; /* PCI Configuration space - offset 0x10400 */
|
| 875 |
|
|
volatile CYG_BYTE reserved_pci404[0x10430-0x10404];
|
| 876 |
|
|
volatile CYG_WORD pci_omisr; /* Outbound interrupt status */
|
| 877 |
|
|
volatile CYG_WORD pci_omimr; /* Outbound interrupt mask */
|
| 878 |
|
|
volatile CYG_WORD reserved_pci438;
|
| 879 |
|
|
volatile CYG_WORD reserved_pci43C;
|
| 880 |
|
|
volatile CYG_WORD pci_ifqpr; /* Inbound FIFO queue */
|
| 881 |
|
|
volatile CYG_WORD pci_ofqpr; /* Outbound FIFO queue */
|
| 882 |
|
|
volatile CYG_WORD reserved_pci448;
|
| 883 |
|
|
volatile CYG_WORD reserved_pci44C;
|
| 884 |
|
|
volatile CYG_WORD pci_imr; /* Inbound message register #0 */
|
| 885 |
|
|
volatile CYG_WORD pci_imr1; /* Inbound message register #1 */
|
| 886 |
|
|
volatile CYG_WORD pci_omr0; /* Outbound message register #0 */
|
| 887 |
|
|
volatile CYG_WORD pci_omr1; /* Outbound message register #1 */
|
| 888 |
|
|
volatile CYG_WORD pci_odr; /* Outbound doorbell */
|
| 889 |
|
|
volatile CYG_WORD reserved_pci464;
|
| 890 |
|
|
volatile CYG_WORD pci_idr; /* Inbound doorbell */
|
| 891 |
|
|
volatile CYG_BYTE reserved_pci46C[0x10480-0x1046C];
|
| 892 |
|
|
volatile CYG_WORD pci_imisr; /* Inbound message interrupt status */
|
| 893 |
|
|
volatile CYG_WORD pci_imimr; /* Inbound message interrupt mask */
|
| 894 |
|
|
volatile CYG_BYTE reserved_pci488[0x104A0-0x10488];
|
| 895 |
|
|
volatile CYG_WORD pci_ifhpr; /* Inbound free FIFO head */
|
| 896 |
|
|
volatile CYG_WORD reserved_pci4A4;
|
| 897 |
|
|
volatile CYG_WORD pci_iftpr; /* Inbound free FIFO tail */
|
| 898 |
|
|
volatile CYG_WORD reserved_pci4AC;
|
| 899 |
|
|
volatile CYG_WORD pci_iphpr; /* Inbound post FIFO head */
|
| 900 |
|
|
volatile CYG_WORD reserved_pci4B4;
|
| 901 |
|
|
volatile CYG_WORD pci_iptpr; /* Inbound post FIFO tail */
|
| 902 |
|
|
volatile CYG_WORD reserved_pci4BC;
|
| 903 |
|
|
volatile CYG_WORD pci_ofhpr; /* Outbound free FIFO head */
|
| 904 |
|
|
volatile CYG_WORD reserved_pci4C4;
|
| 905 |
|
|
volatile CYG_WORD pci_oftpr; /* Outbound free FIFO tail */
|
| 906 |
|
|
volatile CYG_WORD reserved_pci4CC;
|
| 907 |
|
|
volatile CYG_WORD pci_ophpr; /* Outbound post FIFO head */
|
| 908 |
|
|
volatile CYG_WORD reserved_pci4D4;
|
| 909 |
|
|
volatile CYG_WORD pci_optpr; /* Outbound post FIFO tail */
|
| 910 |
|
|
volatile CYG_WORD reserved_pci4DC;
|
| 911 |
|
|
volatile CYG_WORD reserved_pci4E0;
|
| 912 |
|
|
volatile CYG_WORD pci_mucr; /* Message unit control */
|
| 913 |
|
|
volatile CYG_BYTE reserved_pci4E8[0x104F0-0x104E8];
|
| 914 |
|
|
volatile CYG_WORD pci_qbar; /* Queue base address */
|
| 915 |
|
|
volatile CYG_BYTE reserved_pci4F4[0x10500-0x104F4];
|
| 916 |
|
|
volatile CYG_WORD pci_dmamr0; /* DMA #0 - mode */
|
| 917 |
|
|
volatile CYG_WORD pci_dmasr0; /* DMA #0 - status */
|
| 918 |
|
|
volatile CYG_WORD pci_dmacdar0; /* DMA #0 - current descriptor address */
|
| 919 |
|
|
volatile CYG_WORD reserved_pci50C;
|
| 920 |
|
|
volatile CYG_WORD pci_dmasar0; /* DMA #0 - source address */
|
| 921 |
|
|
volatile CYG_WORD reserved_pci514;
|
| 922 |
|
|
volatile CYG_WORD pci_dmadar0; /* DMA #0 - destination address */
|
| 923 |
|
|
volatile CYG_WORD reserved_pci51C;
|
| 924 |
|
|
volatile CYG_WORD pci_dmabcr0; /* DMA #0 - byte count */
|
| 925 |
|
|
volatile CYG_WORD pci_dmandar0; /* DMA #0 - next descriptor */
|
| 926 |
|
|
volatile CYG_BYTE reserved_pci528[0x10580-0x10528];
|
| 927 |
|
|
volatile CYG_WORD pci_dmamr1; /* DMA #1 - mode */
|
| 928 |
|
|
volatile CYG_WORD pci_dmasr1; /* DMA #1 - status */
|
| 929 |
|
|
volatile CYG_WORD pci_dmacdar1; /* DMA #1 - current descriptor address */
|
| 930 |
|
|
volatile CYG_WORD reserved_pci58C;
|
| 931 |
|
|
volatile CYG_WORD pci_dmasar1; /* DMA #1 - source address */
|
| 932 |
|
|
volatile CYG_WORD reserved_pci594;
|
| 933 |
|
|
volatile CYG_WORD pci_dmadar1; /* DMA #1 - destination address */
|
| 934 |
|
|
volatile CYG_WORD reserved_pci59C;
|
| 935 |
|
|
volatile CYG_WORD pci_dmabcr1; /* DMA #1 - byte count */
|
| 936 |
|
|
volatile CYG_WORD pci_dmandar1; /* DMA #1 - next descriptor */
|
| 937 |
|
|
volatile CYG_BYTE reserved_pci5A8[0x10600-0x105A8];
|
| 938 |
|
|
volatile CYG_WORD pci_dmamr2; /* DMA #2 - mode */
|
| 939 |
|
|
volatile CYG_WORD pci_dmasr2; /* DMA #2 - status */
|
| 940 |
|
|
volatile CYG_WORD pci_dmacdar2; /* DMA #2 - current descriptor address */
|
| 941 |
|
|
volatile CYG_WORD reserved_pci60C;
|
| 942 |
|
|
volatile CYG_WORD pci_dmasar2; /* DMA #2 - source address */
|
| 943 |
|
|
volatile CYG_WORD reserved_pci614;
|
| 944 |
|
|
volatile CYG_WORD pci_dmadar2; /* DMA #2 - destination address */
|
| 945 |
|
|
volatile CYG_WORD reserved_pci61C;
|
| 946 |
|
|
volatile CYG_WORD pci_dmabcr2; /* DMA #2 - byte count */
|
| 947 |
|
|
volatile CYG_WORD pci_dmandar2; /* DMA #2 - next descriptor */
|
| 948 |
|
|
volatile CYG_BYTE reserved_pci628[0x10680-0x10628];
|
| 949 |
|
|
volatile CYG_WORD pci_dmamr3; /* DMA #3 - mode */
|
| 950 |
|
|
volatile CYG_WORD pci_dmasr3; /* DMA #3 - status */
|
| 951 |
|
|
volatile CYG_WORD pci_dmacdar3; /* DMA #3 - current descriptor address */
|
| 952 |
|
|
volatile CYG_WORD reserved_pci68C;
|
| 953 |
|
|
volatile CYG_WORD pci_dmasar3; /* DMA #3 - source address */
|
| 954 |
|
|
volatile CYG_WORD reserved_pci694;
|
| 955 |
|
|
volatile CYG_WORD pci_dmadar3; /* DMA #3 - destination address */
|
| 956 |
|
|
volatile CYG_WORD reserved_pci69C;
|
| 957 |
|
|
volatile CYG_WORD pci_dmabcr3; /* DMA #3 - byte count */
|
| 958 |
|
|
volatile CYG_WORD pci_dmandar3; /* DMA #3 - next descriptor */
|
| 959 |
|
|
volatile CYG_BYTE reserved_pci6A8[0x10800-0x106A8];
|
| 960 |
|
|
volatile CYG_WORD pci_potar0; /* PCI outbound translation address #0 */
|
| 961 |
|
|
volatile CYG_WORD reserved_pci804;
|
| 962 |
|
|
volatile CYG_WORD pci_potbar0; /* PCI outbound base address #0 */
|
| 963 |
|
|
volatile CYG_WORD reserved_pci80C;
|
| 964 |
|
|
volatile CYG_WORD pci_pocmr0; /* PCI outbound comparison mask #0 */
|
| 965 |
|
|
volatile CYG_WORD reserved_pci814;
|
| 966 |
|
|
volatile CYG_WORD pci_potar1; /* PCI outbound translation address #1 */
|
| 967 |
|
|
volatile CYG_WORD reserved_pci81C;
|
| 968 |
|
|
volatile CYG_WORD pci_potbar1; /* PCI outbound base address #1 */
|
| 969 |
|
|
volatile CYG_WORD reserved_pci824;
|
| 970 |
|
|
volatile CYG_WORD pci_pocmr1; /* PCI outbound comparison mask #1 */
|
| 971 |
|
|
volatile CYG_WORD reserved_pci82C;
|
| 972 |
|
|
volatile CYG_WORD pci_potar2; /* PCI outbound translation address #2 */
|
| 973 |
|
|
volatile CYG_WORD reserved_pci834;
|
| 974 |
|
|
volatile CYG_WORD pci_potbar2; /* PCI outbound base address #2 */
|
| 975 |
|
|
volatile CYG_WORD reserved_pci83C;
|
| 976 |
|
|
volatile CYG_WORD pci_pocmr2; /* PCI outbound comparison mask #2 */
|
| 977 |
|
|
volatile CYG_BYTE reserved_pci844[0x10878-0x10844];
|
| 978 |
|
|
volatile CYG_WORD pci_ptcr; /* Discard timer control */
|
| 979 |
|
|
volatile CYG_WORD pci_gpcr; /* General purpose control */
|
| 980 |
|
|
volatile CYG_WORD pci_gcr; /* PCI general control */
|
| 981 |
|
|
volatile CYG_WORD pci_esr; /* Error status */
|
| 982 |
|
|
volatile CYG_WORD pci_emr; /* Error mask */
|
| 983 |
|
|
volatile CYG_WORD pci_ecr; /* Error control */
|
| 984 |
|
|
volatile CYG_WORD pci_eacr; /* Error address capture */
|
| 985 |
|
|
volatile CYG_WORD reserved_pci894;
|
| 986 |
|
|
volatile CYG_WORD pci_edcr; /* Error data capture */
|
| 987 |
|
|
volatile CYG_WORD reserved_pci89C;
|
| 988 |
|
|
volatile CYG_WORD pci_eccr; /* Error control */
|
| 989 |
|
|
volatile CYG_BYTE reserved_pci8D0[0x108D0-0x108A4];
|
| 990 |
|
|
volatile CYG_WORD pci_pitar1; /* Inbound address translation #1 */
|
| 991 |
|
|
volatile CYG_WORD reserved_pci8D8;
|
| 992 |
|
|
volatile CYG_WORD pci_pibar1; /* Inbound address base #1 */
|
| 993 |
|
|
volatile CYG_WORD reserved_pci8E0;
|
| 994 |
|
|
volatile CYG_WORD pci_picmr1; /* Inbound comparison mask #1 */
|
| 995 |
|
|
volatile CYG_WORD reserved_pci8E8;
|
| 996 |
|
|
volatile CYG_WORD pci_pitar0; /* Inbound address translation #0 */
|
| 997 |
|
|
volatile CYG_WORD reserved_pci8F0;
|
| 998 |
|
|
volatile CYG_WORD pci_pibar0; /* Inbound address base #0 */
|
| 999 |
|
|
volatile CYG_WORD reserved_pci8F8;
|
| 1000 |
|
|
volatile CYG_WORD pci_picmr0; /* Inbound comparison mask #0 */
|
| 1001 |
|
|
volatile CYG_WORD reserved_pci900;
|
| 1002 |
|
|
volatile CYG_WORD pci_cfg_addr; /* Indirect access to PCI config space - address ptr */
|
| 1003 |
|
|
volatile CYG_WORD pci_cfg_data; /* Indirect access to PCI config space - data */
|
| 1004 |
|
|
volatile CYG_WORD pci_int_ack; /* Used to acknowledge PCI interrupts */
|
| 1005 |
|
|
volatile CYG_BYTE reserved_pci0C00[0x10C00-0x1090C];
|
| 1006 |
|
|
|
| 1007 |
|
|
/* ic */
|
| 1008 |
|
|
volatile CYG_WORD16 ic_sicr; /* Interrupt Configuration Register - offset 0x10C00 */
|
| 1009 |
|
|
volatile CYG_BYTE reserved36[0x2]; /* Reserved area */
|
| 1010 |
|
|
volatile CYG_BYTE ic_sivec; /* CP Interrupt Vector Register */
|
| 1011 |
|
|
volatile CYG_BYTE reserved36a[0x3]; /* Reserved area */
|
| 1012 |
|
|
volatile CYG_WORD ic_sipnr_h; /* Interrupt Pending Register (HIGH) */
|
| 1013 |
|
|
volatile CYG_WORD ic_sipnr_l; /* Interrupt Pending Register (LOW) */
|
| 1014 |
|
|
volatile CYG_WORD ic_siprr; /* SIU Interrupt Priority Register */
|
| 1015 |
|
|
volatile CYG_WORD ic_scprr_h; /* Interrupt Priority Register (HIGH) */
|
| 1016 |
|
|
volatile CYG_WORD ic_scprr_l; /* Interrupt Priority Register (LOW) */
|
| 1017 |
|
|
volatile CYG_WORD ic_simr_h; /* Interrupt Mask Register (HIGH) */
|
| 1018 |
|
|
volatile CYG_WORD ic_simr_l; /* Interrupt Mask Register (LOW) */
|
| 1019 |
|
|
volatile CYG_WORD ic_siexr; /* External Interrupt Control Register */
|
| 1020 |
|
|
volatile CYG_BYTE reserved37[0x58]; /* Reserved area */
|
| 1021 |
|
|
|
| 1022 |
|
|
/* clocks */
|
| 1023 |
|
|
volatile CYG_WORD clocks_sccr; /* System Clock Control Register */
|
| 1024 |
|
|
volatile CYG_BYTE reserved38[0x4]; /* Reserved area */
|
| 1025 |
|
|
volatile CYG_WORD clocks_scmr; /* System Clock Mode Register */
|
| 1026 |
|
|
volatile CYG_BYTE reserved39[0x4]; /* Reserved area */
|
| 1027 |
|
|
volatile CYG_WORD clocks_rsr; /* Reset Status Register */
|
| 1028 |
|
|
volatile CYG_WORD clocks_rmr; /* Reset Mode Register */
|
| 1029 |
|
|
volatile CYG_BYTE reserved40[0x68]; /* Reserved area */
|
| 1030 |
|
|
|
| 1031 |
|
|
/* io_ports */
|
| 1032 |
|
|
struct io_regs
|
| 1033 |
|
|
{
|
| 1034 |
|
|
volatile CYG_WORD pdir; /* Port A-D Data Direction Register */
|
| 1035 |
|
|
volatile CYG_WORD ppar; /* Port A-D Pin Assignment Register */
|
| 1036 |
|
|
volatile CYG_WORD psor; /* Port A-D Special Operation Register */
|
| 1037 |
|
|
volatile CYG_WORD podr; /* Port A-D Open Drain Register */
|
| 1038 |
|
|
volatile CYG_WORD pdat; /* Port A-D Data Register */
|
| 1039 |
|
|
volatile CYG_BYTE reserved41[0xc]; /* Reserved area */
|
| 1040 |
|
|
} io_regs[4];
|
| 1041 |
|
|
|
| 1042 |
|
|
/* cpm_timers */
|
| 1043 |
|
|
volatile CYG_BYTE cpm_timers_tgcr1; /* Timer Global Configuration Register */
|
| 1044 |
|
|
volatile CYG_BYTE reserved42[0x3]; /* Reserved area */
|
| 1045 |
|
|
volatile CYG_BYTE cpm_timers_tgcr2; /* Timer Global Configuration Register */
|
| 1046 |
|
|
volatile CYG_BYTE reserved43[0xb]; /* Reserved area */
|
| 1047 |
|
|
volatile CYG_WORD16 cpm_timers_tmr1; /* Timer Mode Register */
|
| 1048 |
|
|
volatile CYG_WORD16 cpm_timers_tmr2; /* Timer Mode Register */
|
| 1049 |
|
|
volatile CYG_WORD16 cpm_timers_trr1; /* Timer Reference Register */
|
| 1050 |
|
|
volatile CYG_WORD16 cpm_timers_trr2; /* Timer Reference Register */
|
| 1051 |
|
|
volatile CYG_WORD16 cpm_timers_tcr1; /* Timer Capture Register */
|
| 1052 |
|
|
volatile CYG_WORD16 cpm_timers_tcr2; /* Timer Capture Register */
|
| 1053 |
|
|
volatile CYG_WORD16 cpm_timers_tcn1; /* Timer Counter */
|
| 1054 |
|
|
volatile CYG_WORD16 cpm_timers_tcn2; /* Timer Counter */
|
| 1055 |
|
|
volatile CYG_WORD16 cpm_timers_tmr3; /* Timer Mode Register */
|
| 1056 |
|
|
volatile CYG_WORD16 cpm_timers_tmr4; /* Timer Mode Register */
|
| 1057 |
|
|
volatile CYG_WORD16 cpm_timers_trr3; /* Timer Reference Register */
|
| 1058 |
|
|
volatile CYG_WORD16 cpm_timers_trr4; /* Timer Reference Register */
|
| 1059 |
|
|
volatile CYG_WORD16 cpm_timers_tcr3; /* Timer Capture Register */
|
| 1060 |
|
|
volatile CYG_WORD16 cpm_timers_tcr4; /* Timer Capture Register */
|
| 1061 |
|
|
volatile CYG_WORD16 cpm_timers_tcn3; /* Timer Counter */
|
| 1062 |
|
|
volatile CYG_WORD16 cpm_timers_tcn4; /* Timer Counter */
|
| 1063 |
|
|
volatile CYG_WORD16 cpm_timers_ter[4]; /* Timer Event Register */
|
| 1064 |
|
|
volatile CYG_BYTE reserved44[0x260]; /* Reserved area */
|
| 1065 |
|
|
|
| 1066 |
|
|
/* sdma general */
|
| 1067 |
|
|
volatile CYG_BYTE sdma_sdsr; /* SDMA Status Register */
|
| 1068 |
|
|
volatile CYG_BYTE reserved45[0x3]; /* Reserved area */
|
| 1069 |
|
|
volatile CYG_BYTE sdma_sdmr; /* SDMA Mask Register */
|
| 1070 |
|
|
volatile CYG_BYTE reserved46[0x3]; /* Reserved area */
|
| 1071 |
|
|
|
| 1072 |
|
|
/* idma */
|
| 1073 |
|
|
volatile CYG_BYTE idma_idsr1; /* IDMA Status Register */
|
| 1074 |
|
|
volatile CYG_BYTE reserved47[0x3]; /* Reserved area */
|
| 1075 |
|
|
volatile CYG_BYTE idma_idmr1; /* IDMA Mask Register */
|
| 1076 |
|
|
volatile CYG_BYTE reserved48[0x3]; /* Reserved area */
|
| 1077 |
|
|
volatile CYG_BYTE idma_idsr2; /* IDMA Status Register */
|
| 1078 |
|
|
volatile CYG_BYTE reserved49[0x3]; /* Reserved area */
|
| 1079 |
|
|
volatile CYG_BYTE idma_idmr2; /* IDMA Mask Register */
|
| 1080 |
|
|
volatile CYG_BYTE reserved50[0x3]; /* Reserved area */
|
| 1081 |
|
|
volatile CYG_BYTE idma_idsr3; /* IDMA Status Register */
|
| 1082 |
|
|
volatile CYG_BYTE reserved51[0x3]; /* Reserved area */
|
| 1083 |
|
|
volatile CYG_BYTE idma_idmr3; /* IDMA Mask Register */
|
| 1084 |
|
|
volatile CYG_BYTE reserved52[0x3]; /* Reserved area */
|
| 1085 |
|
|
volatile CYG_BYTE idma_idsr4; /* IDMA Status Register */
|
| 1086 |
|
|
volatile CYG_BYTE reserved53[0x3]; /* Reserved area */
|
| 1087 |
|
|
volatile CYG_BYTE idma_idmr4; /* IDMA Mask Register */
|
| 1088 |
|
|
volatile CYG_BYTE reserved54[0x2c3]; /* Reserved area */
|
| 1089 |
|
|
|
| 1090 |
|
|
/* fcc */
|
| 1091 |
|
|
struct fcc_regs
|
| 1092 |
|
|
{
|
| 1093 |
|
|
volatile CYG_WORD fcc_gfmr; /* FCC General Mode Register */
|
| 1094 |
|
|
volatile CYG_WORD fcc_psmr; /* FCC Protocol Specific Mode Register */
|
| 1095 |
|
|
volatile CYG_WORD16 fcc_todr; /* FCC Transmit On Demand Register */
|
| 1096 |
|
|
volatile CYG_BYTE reserved55[0x2]; /* Reserved area */
|
| 1097 |
|
|
volatile CYG_WORD16 fcc_dsr; /* FCC Data Sync. Register */
|
| 1098 |
|
|
volatile CYG_BYTE reserved56[0x2]; /* Reserved area */
|
| 1099 |
|
|
volatile CYG_WORD16 fcc_fcce; /* FCC Event Register */
|
| 1100 |
|
|
volatile CYG_BYTE reserved56a[0x2]; /* Reserved area */
|
| 1101 |
|
|
volatile CYG_WORD16 fcc_fccm; /* FCC Mask Register */
|
| 1102 |
|
|
volatile CYG_BYTE reserved56b[0x2]; /* Reserved area */
|
| 1103 |
|
|
volatile CYG_BYTE fcc_fccs; /* FCC Status Register */
|
| 1104 |
|
|
volatile CYG_BYTE reserved57[0x3]; /* Reserved area */
|
| 1105 |
|
|
volatile CYG_WORD fcc_ftprr; /* FCC Transmit Partial Rate Register */
|
| 1106 |
|
|
} fcc_regs[3];
|
| 1107 |
|
|
volatile CYG_BYTE reserved58[0x290]; /* Reserved area */
|
| 1108 |
|
|
|
| 1109 |
|
|
/* brgs 5 through 8 */
|
| 1110 |
|
|
volatile CYG_WORD brgs_brgc5; /* Baud Rate Generator 5 Config Register */
|
| 1111 |
|
|
volatile CYG_WORD brgs_brgc6; /* Baud Rate Generator 6 Config Register */
|
| 1112 |
|
|
volatile CYG_WORD brgs_brgc7; /* Baud Rate Generator 7 Config Register */
|
| 1113 |
|
|
volatile CYG_WORD brgs_brgc8; /* Baud Rate Generator 8 Config Register */
|
| 1114 |
|
|
volatile CYG_BYTE reserved59[0x260]; /* Reserved area */
|
| 1115 |
|
|
|
| 1116 |
|
|
/* i2c */
|
| 1117 |
|
|
volatile CYG_BYTE i2c_i2mod; /* IC Mode Register */
|
| 1118 |
|
|
volatile CYG_BYTE reserved60[0x3]; /* Reserved area */
|
| 1119 |
|
|
volatile CYG_BYTE i2c_i2add; /* IC Address Register */
|
| 1120 |
|
|
volatile CYG_BYTE reserved61[0x3]; /* Reserved area */
|
| 1121 |
|
|
volatile CYG_BYTE i2c_i2brg; /* IC BRG Register */
|
| 1122 |
|
|
volatile CYG_BYTE reserved62[0x3]; /* Reserved area */
|
| 1123 |
|
|
volatile CYG_BYTE i2c_i2com; /* IC Command Register */
|
| 1124 |
|
|
volatile CYG_BYTE reserved63[0x3]; /* Reserved area */
|
| 1125 |
|
|
volatile CYG_BYTE i2c_i2cer; /* IC Event Register */
|
| 1126 |
|
|
volatile CYG_BYTE reserved64[0x3]; /* Reserved area */
|
| 1127 |
|
|
volatile CYG_BYTE i2c_i2cmr; /* IC Mask Register */
|
| 1128 |
|
|
volatile CYG_BYTE reserved65[0x14b]; /* Reserved area */
|
| 1129 |
|
|
|
| 1130 |
|
|
/* cpm */
|
| 1131 |
|
|
volatile CYG_WORD cpm_cpcr; /* Communication Processor Command Register */
|
| 1132 |
|
|
volatile CYG_WORD cpm_rccr; /* RISC Configuration Register */
|
| 1133 |
|
|
volatile CYG_WORD cpm_rmdr; /* RISC Microcode Dev. Support Control Reg. */
|
| 1134 |
|
|
volatile CYG_WORD16 cpm_rctr1; /* RISC Controller Trap Register */
|
| 1135 |
|
|
volatile CYG_WORD16 cpm_rctr2; /* RISC Controller Trap Register */
|
| 1136 |
|
|
volatile CYG_WORD16 cpm_rctr3; /* RISC Controller Trap Register */
|
| 1137 |
|
|
volatile CYG_WORD16 cpm_rctr4; /* RISC Controller Trap Register */
|
| 1138 |
|
|
volatile CYG_BYTE reserved66[0x2]; /* Reserved area */
|
| 1139 |
|
|
volatile CYG_WORD16 cpm_rter; /* RISC Timers Event Register */
|
| 1140 |
|
|
volatile CYG_BYTE reserved67[0x2]; /* Reserved area */
|
| 1141 |
|
|
volatile CYG_WORD16 cpm_rtmr; /* RISC Timers Mask Register */
|
| 1142 |
|
|
volatile CYG_WORD16 cpm_rtscr; /* RISC Time-Stamp Timer Control Register */
|
| 1143 |
|
|
volatile CYG_WORD16 cpm_rmds; /* RISC Development Support Status Register */
|
| 1144 |
|
|
volatile CYG_WORD cpm_rtsr; /* RISC Time-Stamp Register */
|
| 1145 |
|
|
volatile CYG_BYTE reserved68[0xc]; /* Reserved area */
|
| 1146 |
|
|
|
| 1147 |
|
|
/* brgs 1 through 4 */
|
| 1148 |
|
|
volatile CYG_WORD brgs_brgc1; /* Baud Rate Generator 5 Config Register */
|
| 1149 |
|
|
volatile CYG_WORD brgs_brgc2; /* Baud Rate Generator 2 Config Register */
|
| 1150 |
|
|
volatile CYG_WORD brgs_brgc3; /* Baud Rate Generator 3 Config Register */
|
| 1151 |
|
|
volatile CYG_WORD brgs_brgc4; /* Baud Rate Generator 4 Config Register */
|
| 1152 |
|
|
|
| 1153 |
|
|
/* scc */
|
| 1154 |
|
|
struct scc_regs_8260
|
| 1155 |
|
|
{
|
| 1156 |
|
|
volatile CYG_WORD gsmr_l; /* SCC General Mode Register */
|
| 1157 |
|
|
volatile CYG_WORD gsmr_h; /* SCC General Mode Register */
|
| 1158 |
|
|
volatile CYG_WORD16 psmr; /* SCC Protocol Specific Mode Register */
|
| 1159 |
|
|
volatile CYG_BYTE reserved69[0x2]; /* Reserved area */
|
| 1160 |
|
|
volatile CYG_WORD16 todr; /* SCC Transmit-On-Demand Register */
|
| 1161 |
|
|
volatile CYG_WORD16 dsr; /* SCC Data Synchronization Register */
|
| 1162 |
|
|
volatile CYG_WORD16 scce; /* SCC Event Register */
|
| 1163 |
|
|
volatile CYG_BYTE reserved70[0x2]; /* Reserved area */
|
| 1164 |
|
|
volatile CYG_WORD16 sccm; /* SCC Mask Register */
|
| 1165 |
|
|
volatile CYG_BYTE reserved71; /* Reserved area */
|
| 1166 |
|
|
volatile CYG_BYTE sccs; /* SCC Status Register */
|
| 1167 |
|
|
volatile CYG_BYTE reserved72[0x8]; /* Reserved area */
|
| 1168 |
|
|
} scc_regs[4];
|
| 1169 |
|
|
|
| 1170 |
|
|
/* smc */
|
| 1171 |
|
|
struct smc_regs_8260
|
| 1172 |
|
|
{
|
| 1173 |
|
|
volatile CYG_BYTE reserved73[0x2]; /* Reserved area */
|
| 1174 |
|
|
volatile CYG_WORD16 smc_smcmr; /* SMC Mode Register */
|
| 1175 |
|
|
volatile CYG_BYTE reserved74[0x2]; /* Reserved area */
|
| 1176 |
|
|
volatile CYG_BYTE smc_smce; /* SMC Event Register */
|
| 1177 |
|
|
volatile CYG_BYTE reserved75[0x3]; /* Reserved area */
|
| 1178 |
|
|
volatile CYG_BYTE smc_smcm; /* SMC Mask Register */
|
| 1179 |
|
|
volatile CYG_BYTE reserved76[0x5]; /* Reserved area */
|
| 1180 |
|
|
} smc_regs[2];
|
| 1181 |
|
|
|
| 1182 |
|
|
/* spi */
|
| 1183 |
|
|
volatile CYG_WORD16 spi_spmode; /* SPI Mode Register */
|
| 1184 |
|
|
volatile CYG_BYTE reserved77[0x4]; /* Reserved area */
|
| 1185 |
|
|
volatile CYG_BYTE spi_spie; /* SPI Event Register */
|
| 1186 |
|
|
volatile CYG_BYTE reserved78[0x3]; /* Reserved area */
|
| 1187 |
|
|
volatile CYG_BYTE spi_spim; /* SPI Mask Register */
|
| 1188 |
|
|
volatile CYG_BYTE reserved79[0x2]; /* Reserved area */
|
| 1189 |
|
|
volatile CYG_BYTE spi_spcom; /* SPI Command Register */
|
| 1190 |
|
|
volatile CYG_BYTE reserved80[0x52]; /* Reserved area */
|
| 1191 |
|
|
|
| 1192 |
|
|
/* cpm_mux */
|
| 1193 |
|
|
|
| 1194 |
|
|
volatile CYG_BYTE cpm_mux_cmxsi1cr; /* CPM MUX SI Clock Route Register */
|
| 1195 |
|
|
volatile CYG_BYTE reserved81; /* Reserved area */
|
| 1196 |
|
|
volatile CYG_BYTE cpm_mux_cmxsi2cr; /* CPM MUX SI Clock Route Register */
|
| 1197 |
|
|
volatile CYG_BYTE reserved82; /* Reserved area */
|
| 1198 |
|
|
volatile CYG_WORD cpm_mux_cmxfcr; /* CPM MUX FCC Clock Route Register */
|
| 1199 |
|
|
volatile CYG_WORD cpm_mux_cmxscr; /* CPM MUX SCC Clock Route Register */
|
| 1200 |
|
|
volatile CYG_BYTE cpm_mux_cmxsmr; /* CPM MUX SMC Clock Route Register */
|
| 1201 |
|
|
volatile CYG_BYTE reserved83; /* Reserved area */
|
| 1202 |
|
|
volatile CYG_WORD16 cpm_mux_cmxuar; /* CPM MUX UTOPIA Address Register */
|
| 1203 |
|
|
volatile CYG_BYTE reserved84[0x10]; /* Reserved area */
|
| 1204 |
|
|
|
| 1205 |
|
|
/* si */
|
| 1206 |
|
|
struct si_regs
|
| 1207 |
|
|
{
|
| 1208 |
|
|
volatile CYG_WORD16 si_si1mr[4]; /* SI TDM Mode Registers */
|
| 1209 |
|
|
volatile CYG_BYTE si_si1gmr; /* SI Global Mode Register */
|
| 1210 |
|
|
volatile CYG_BYTE reserved85; /* Reserved area */
|
| 1211 |
|
|
volatile CYG_BYTE si_si1cmdr; /* SI Command Register */
|
| 1212 |
|
|
volatile CYG_BYTE reserved86; /* Reserved area */
|
| 1213 |
|
|
volatile CYG_BYTE si_si1str; /* SI Status Register */
|
| 1214 |
|
|
volatile CYG_BYTE reserved87; /* Reserved area */
|
| 1215 |
|
|
volatile CYG_WORD16 si_si1rsr; /* SI RAM Shadow Address Register */
|
| 1216 |
|
|
volatile CYG_WORD16 mcc_mcce; /* MCC Event Register */
|
| 1217 |
|
|
volatile CYG_BYTE reserved88[0x2]; /* Reserved area */
|
| 1218 |
|
|
volatile CYG_WORD16 mcc_mccm; /* MCC Mask Register */
|
| 1219 |
|
|
volatile CYG_BYTE reserved89[0x2]; /* Reserved area */
|
| 1220 |
|
|
volatile CYG_BYTE mcc_mccf; /* MCC Configuration Register */
|
| 1221 |
|
|
volatile CYG_BYTE reserved90[0x7]; /* Reserved area */
|
| 1222 |
|
|
} si_regs[2];
|
| 1223 |
|
|
volatile CYG_BYTE reserved91[0x4a0]; /* Reserved area */
|
| 1224 |
|
|
|
| 1225 |
|
|
/* si_ram */
|
| 1226 |
|
|
struct si_ram
|
| 1227 |
|
|
{
|
| 1228 |
|
|
CYG_WORD16 si1_ram_si1_tx_ram[0x100]; /* SI Transmit Routing RAM */
|
| 1229 |
|
|
volatile CYG_BYTE reserved92[0x200]; /* Reserved area */
|
| 1230 |
|
|
CYG_WORD16 si1_ram_si1_rx_ram[0x100]; /* SI Receive Routing RAM */
|
| 1231 |
|
|
volatile CYG_BYTE reserved93[0x200]; /* Reserved area */
|
| 1232 |
|
|
} si_ram[2];
|
| 1233 |
|
|
volatile CYG_BYTE reserved94[0x1000]; /* Reserved area */
|
| 1234 |
|
|
|
| 1235 |
|
|
} _PackedType t_PQ2IMM;
|
| 1236 |
|
|
|
| 1237 |
|
|
extern volatile t_PQ2IMM *IMM; /* IMM base pointer */
|
| 1238 |
|
|
|
| 1239 |
|
|
/***************************************************************************/
|
| 1240 |
|
|
/* General Global Definitions */
|
| 1241 |
|
|
/***************************************************************************/
|
| 1242 |
|
|
|
| 1243 |
|
|
#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */
|
| 1244 |
|
|
#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */
|
| 1245 |
|
|
#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */
|
| 1246 |
|
|
#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */
|
| 1247 |
|
|
|
| 1248 |
|
|
#define SCC1 0 /* SCC1 Index into SCC Regs Array */
|
| 1249 |
|
|
#define SCC2 1 /* SCC2 Index into SCC Regs Array */
|
| 1250 |
|
|
#define SCC3 2 /* SCC3 Index into SCC Regs Array */
|
| 1251 |
|
|
#define SCC4 3 /* SCC4 Index into SCC Regs Array */
|
| 1252 |
|
|
|
| 1253 |
|
|
#define SMC1 0 /* SMC1 Index into SMC Regs Array */
|
| 1254 |
|
|
#define SMC2 1 /* SMC2 Index into SMC Regs Array */
|
| 1255 |
|
|
|
| 1256 |
|
|
#define PORT_A 0 /* Parallel port A registers */
|
| 1257 |
|
|
#define PORT_B 1 /* Parallel port B registers */
|
| 1258 |
|
|
#define PORT_C 2 /* Parallel port C registers */
|
| 1259 |
|
|
#define PORT_D 3 /* Parallel port D registers */
|
| 1260 |
|
|
|
| 1261 |
|
|
/*--------------------------------*/
|
| 1262 |
|
|
/* KEEP ALIVE POWER REGISTERS KEY */
|
| 1263 |
|
|
/*--------------------------------*/
|
| 1264 |
|
|
|
| 1265 |
|
|
#define KEEP_ALIVE_KEY 0x55ccaa33
|
| 1266 |
|
|
|
| 1267 |
|
|
/*------------------------------------------*
|
| 1268 |
|
|
* CPM Command Register (CPCR) *
|
| 1269 |
|
|
*-------------------------------------------*
|
| 1270 |
|
|
* NOTE: This register is cleared by reset. *
|
| 1271 |
|
|
* See MPC8260 User's Manual. *
|
| 1272 |
|
|
*-------------------------------------------*/
|
| 1273 |
|
|
|
| 1274 |
|
|
#define CPCR_RST 0x80000000 /* Software Reset Command */
|
| 1275 |
|
|
#define CPCR_FLG 0x00010000 /* Command Semaphore Flag */
|
| 1276 |
|
|
|
| 1277 |
|
|
#define CPCR_SUBBLOCK(page,code) ((page<<26)|(code<<21))
|
| 1278 |
|
|
|
| 1279 |
|
|
/*-----------------------------------------------*/
|
| 1280 |
|
|
/* Definitions for SCC CPCR Subblock/Page codes. */
|
| 1281 |
|
|
/*-----------------------------------------------*/
|
| 1282 |
|
|
|
| 1283 |
|
|
#define SCC1_PAGE_SUBBLOCK CPCR_SUBBLOCK(0,4)
|
| 1284 |
|
|
#define SCC2_PAGE_SUBBLOCK CPCR_SUBBLOCK(1,5)
|
| 1285 |
|
|
#define SCC3_PAGE_SUBBLOCK CPCR_SUBBLOCK(2,6)
|
| 1286 |
|
|
#define SCC4_PAGE_SUBBLOCK CPCR_SUBBLOCK(3,7)
|
| 1287 |
|
|
|
| 1288 |
|
|
/*-----------------------------------------------*/
|
| 1289 |
|
|
/* Definitions for SMC CPCR Subblock/Page codes. */
|
| 1290 |
|
|
/*-----------------------------------------------*/
|
| 1291 |
|
|
|
| 1292 |
|
|
#define SMC1_PAGE_SUBBLOCK CPCR_SUBBLOCK(7,8)
|
| 1293 |
|
|
#define SMC2_PAGE_SUBBLOCK CPCR_SUBBLOCK(8,9)
|
| 1294 |
|
|
|
| 1295 |
|
|
/*-----------------------------------------------*/
|
| 1296 |
|
|
/* Definitions for FCC CPCR Subblock/Page codes. */
|
| 1297 |
|
|
/*-----------------------------------------------*/
|
| 1298 |
|
|
|
| 1299 |
|
|
#define FCC1_PAGE_SUBBLOCK CPCR_SUBBLOCK(4,0x10)
|
| 1300 |
|
|
#define FCC2_PAGE_SUBBLOCK CPCR_SUBBLOCK(5,0x11)
|
| 1301 |
|
|
#define FCC3_PAGE_SUBBLOCK CPCR_SUBBLOCK(6,0x12)
|
| 1302 |
|
|
|
| 1303 |
|
|
/*-----------------------------*/
|
| 1304 |
|
|
/* Opcode definitions for SCCs, opcodes for SMC's are the same
|
| 1305 |
|
|
* except not all codes are valid for SMC */
|
| 1306 |
|
|
/*-----------------------------*/
|
| 1307 |
|
|
|
| 1308 |
|
|
#define CPCR_INIT_TX_RX_PARAMS 0x00000000 /* Opcode 0 */
|
| 1309 |
|
|
#define CPCR_INIT_RX_PARAMS 0x00000001 /* Opcode 1 */
|
| 1310 |
|
|
#define CPCR_INIT_TX_PARAMS 0x00000002 /* Opcode 2 */
|
| 1311 |
|
|
#define CPCR_ENTER_HUNT_MODE 0x00000003 /* Opcode 3 */
|
| 1312 |
|
|
#define CPCR_STOP_TX 0x00000004 /* Opcode 4 */
|
| 1313 |
|
|
#define CPCR_GRACEFUL_STOP_TX 0x00000005 /* Opcode 5 */
|
| 1314 |
|
|
#define CPCR_RESTART_TX 0x00000006 /* Opcode 6 */
|
| 1315 |
|
|
#define CPCR_CLOSE_RX_BD 0x00000007 /* Opcode 7 */
|
| 1316 |
|
|
#define CPCR_SET_GRP_ADDR 0x00000008 /* Opcode 8 */
|
| 1317 |
|
|
#define CPCR_RESET_BCS 0x0000000A /* Opcode 10 */
|
| 1318 |
|
|
|
| 1319 |
|
|
/*-----------------------------------------------------*/
|
| 1320 |
|
|
/* General Definitions for SCC CPCR Command Operations */
|
| 1321 |
|
|
/*-----------------------------------------------------*/
|
| 1322 |
|
|
|
| 1323 |
|
|
#define READY_TO_RX_CMD 0x00000000
|
| 1324 |
|
|
|
| 1325 |
|
|
/*-------------------------*/
|
| 1326 |
|
|
/* General SCC Definitions */
|
| 1327 |
|
|
/*-------------------------*/
|
| 1328 |
|
|
|
| 1329 |
|
|
#define DISABLE_TX_RX 0xFFFFFFCF /* Clear the ENT/ENR bits in the GSMR
|
| 1330 |
|
|
Disables the transmit & Receive
|
| 1331 |
|
|
port */
|
| 1332 |
|
|
|
| 1333 |
|
|
#define GSMR_L1_ENT 0x00000010 /* ENT bit for the GSMR low register */
|
| 1334 |
|
|
#define GSMR_L1_ENR 0x00000020 /* ENR bit for the GSMR low register */
|
| 1335 |
|
|
|
| 1336 |
|
|
|
| 1337 |
|
|
#define ALL_ONES 0xFFFF
|
| 1338 |
|
|
|
| 1339 |
|
|
struct cp_bufdesc {
|
| 1340 |
|
|
volatile unsigned short ctrl; /* status/control register */
|
| 1341 |
|
|
volatile unsigned short length; /* buffer length */
|
| 1342 |
|
|
volatile char *buffer; /* buffer pointer */
|
| 1343 |
|
|
};
|
| 1344 |
|
|
|
| 1345 |
|
|
// Buffer descriptor control bits
|
| 1346 |
|
|
#define _BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx)
|
| 1347 |
|
|
#define _BD_CTL_Wrap 0x2000 // Last buffer in list
|
| 1348 |
|
|
#define _BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx)
|
| 1349 |
|
|
#define _BD_CTL_Last 0x0800 // Last buffer in a sequence
|
| 1350 |
|
|
#define _BD_CTL_MASK 0xB000 // User settable bits
|
| 1351 |
|
|
|
| 1352 |
|
|
//
|
| 1353 |
|
|
// Event masks
|
| 1354 |
|
|
//
|
| 1355 |
|
|
#define SCCE_Bsy 0x0004 // Rx error
|
| 1356 |
|
|
#define SCCE_Tx 0x0002 // Tx buffer interrupt
|
| 1357 |
|
|
#define SCCE_Rx 0x0001 // Rx buffer interrupt
|
| 1358 |
|
|
#define SMCE_Bsy 0x0004 // Rx error
|
| 1359 |
|
|
#define SMCE_Tx 0x0002 // Tx buffer interrupt
|
| 1360 |
|
|
#define SMCE_Rx 0x0001 // Rx buffer interrupt
|
| 1361 |
|
|
|
| 1362 |
|
|
//
|
| 1363 |
|
|
// Timer/counter registers
|
| 1364 |
|
|
//
|
| 1365 |
|
|
|
| 1366 |
|
|
// Timer/counter general control
|
| 1367 |
|
|
#define _TC_TGCR_CAS 0x80 // Cascade timers (1/2, 3/4)
|
| 1368 |
|
|
#define _TC_TGCR_STP2 0x20 // Stop timer 2
|
| 1369 |
|
|
#define _TC_TGCR_RST2 0x10 // Reset timer 2
|
| 1370 |
|
|
#define _TC_TGCR_GM 0x08 // Gate mode
|
| 1371 |
|
|
#define _TC_TGCR_STP1 0x02 // Stop timer 1
|
| 1372 |
|
|
#define _TC_TGCR_RST1 0x01 // Reset timer 1
|
| 1373 |
|
|
|
| 1374 |
|
|
// Timer/counter mode
|
| 1375 |
|
|
#define _TC_TMR_ORI 0x0010 // Output reference interrupt enable
|
| 1376 |
|
|
#define _TC_TMR_FRR 0x0008 // Free run
|
| 1377 |
|
|
#define _TC_TMR_ICLK_CAS 0x0000 // Input clock - cascade from other timer
|
| 1378 |
|
|
#define _TC_TMR_ICLK_BUS 0x0002 // Input clock = bus clock
|
| 1379 |
|
|
#define _TC_TMR_ICLK_BUS16 0x0004 // Input clock = bus clock / 16
|
| 1380 |
|
|
#define _TC_TMR_ICLK_TIN 0x0006 // Input clock = TINx
|
| 1381 |
|
|
|
| 1382 |
|
|
// Timer/counter event register
|
| 1383 |
|
|
#define _TC_TER_REF 0x0002 // Reference event occurred
|
| 1384 |
|
|
#define _TC_TER_CAP 0x0001 // Capture event occurred
|
| 1385 |
|
|
|
| 1386 |
|
|
//
|
| 1387 |
|
|
// Routines which help manage the CPM
|
| 1388 |
|
|
//
|
| 1389 |
|
|
externC void _mpc8xxx_reset_cpm(void);
|
| 1390 |
|
|
externC unsigned int _mpc8xxx_allocBd(int len);
|
| 1391 |
|
|
|
| 1392 |
|
|
#endif // ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
|
