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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [powerpc/] [mpc8xxx/] [current/] [include/] [var_intr.h] - Blame information for rev 786

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1 786 skrzyp
#ifndef CYGONCE_VAR_INTR_H
2
#define CYGONCE_VAR_INTR_H
3
//=============================================================================
4
//
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//      var_intr.h
6
//
7
//      Variant HAL interrupt and clock support
8
//
9
//=============================================================================
10
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
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// -------------------------------------------                              
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// This file is part of eCos, the Embedded Configurable Operating System.   
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under    
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// the terms of the GNU General Public License as published by the Free     
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// Software Foundation; either version 2 or (at your option) any later      
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// version.                                                                 
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT      
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
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// for more details.                                                        
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//
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// You should have received a copy of the GNU General Public License        
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// along with eCos; if not, write to the Free Software Foundation, Inc.,    
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
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//
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// As a special exception, if other files instantiate templates or use      
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// macros or inline functions from this file, or you compile this file      
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// and link it with other works to produce a work based on this file,       
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// this file does not by itself cause the resulting work to be covered by   
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// the GNU General Public License. However the source code for this file    
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// must still be made available in accordance with section (3) of the GNU   
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// General Public License v2.                                               
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//
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// This exception does not invalidate any other reasons why a work based    
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// on this file might be covered by the GNU General Public License.         
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// -------------------------------------------                              
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// ####ECOSGPLCOPYRIGHTEND####                                              
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):   mtek, pfine
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// Contributors:nickg, jskov, jlarmour, hmt
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// Date:        2001-12-12
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// Purpose:     Variant interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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//              interrupts and the clock on the MPC8xxx PowerQUICCII CPU.
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// Usage:       Is included via the architecture interrupt header:
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//              #include <cyg/hal/hal_intr.h>
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//              ...
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//
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//####DESCRIPTIONEND####
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//
56
//=============================================================================
57
#include <pkgconf/hal.h>
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#include <cyg/hal/plf_intr.h>
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#include <cyg/hal/mpc8xxx.h>            // Memory map
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#include <cyg/infra/cyg_type.h>         // types
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#include <cyg/hal/hal_io.h>             // io macros
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#include <cyg/infra/cyg_ass.h>          // CYG_FAIL
63
 
64
#include <cyg/infra/diag.h>
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66
// Interrupts
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68
// The first level of external interrupts
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#define CYGNUM_HAL_INTERRUPT_I2C                 1
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#define CYGNUM_HAL_INTERRUPT_SPI                 2
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#define CYGNUM_HAL_INTERRUPT_RISC_TIMERS         3
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#define CYGNUM_HAL_INTERRUPT_SMC1                4
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#define CYGNUM_HAL_INTERRUPT_SMC2                5
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#define CYGNUM_HAL_INTERRUPT_IDMA1               6
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#define CYGNUM_HAL_INTERRUPT_IDMA2               7
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#define CYGNUM_HAL_INTERRUPT_IDMA3               8
77
#define CYGNUM_HAL_INTERRUPT_IDMA4               9
78
#define CYGNUM_HAL_INTERRUPT_SDMA               10
79
 
80
#define CYGNUM_HAL_INTERRUPT_TIMER1             12
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#define CYGNUM_HAL_INTERRUPT_TIMER2             13
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#define CYGNUM_HAL_INTERRUPT_TIMER3             14
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#define CYGNUM_HAL_INTERRUPT_TIMER4             15
84
#define CYGNUM_HAL_INTERRUPT_TMCNT              16
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#define CYGNUM_HAL_INTERRUPT_PIT                17
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87
#define CYGNUM_HAL_INTERRUPT_IRQ1               19
88
#define CYGNUM_HAL_INTERRUPT_IRQ2               20
89
#define CYGNUM_HAL_INTERRUPT_IRQ3               21
90
#define CYGNUM_HAL_INTERRUPT_IRQ4               22
91
#define CYGNUM_HAL_INTERRUPT_IRQ5               23
92
#define CYGNUM_HAL_INTERRUPT_IRQ6               24
93
#define CYGNUM_HAL_INTERRUPT_IRQ7               25
94
 
95
#define CYGNUM_HAL_INTERRUPT_FCC1               32
96
#define CYGNUM_HAL_INTERRUPT_FCC2               33
97
#define CYGNUM_HAL_INTERRUPT_FCC3               34
98
 
99
#define CYGNUM_HAL_INTERRUPT_MCC1               36
100
#define CYGNUM_HAL_INTERRUPT_MCC2               37
101
 
102
#define CYGNUM_HAL_INTERRUPT_SCC1               40
103
#define CYGNUM_HAL_INTERRUPT_SCC2               41
104
#define CYGNUM_HAL_INTERRUPT_SCC3               42
105
#define CYGNUM_HAL_INTERRUPT_SCC4               43
106
 
107
#define CYGNUM_HAL_INTERRUPT_PC15               48
108
#define CYGNUM_HAL_INTERRUPT_PC14               49
109
#define CYGNUM_HAL_INTERRUPT_PC13               50
110
#define CYGNUM_HAL_INTERRUPT_PC12               51
111
#define CYGNUM_HAL_INTERRUPT_PC11               52
112
#define CYGNUM_HAL_INTERRUPT_PC10               53
113
#define CYGNUM_HAL_INTERRUPT_PC9                54
114
#define CYGNUM_HAL_INTERRUPT_PC8                55
115
#define CYGNUM_HAL_INTERRUPT_PC7                56
116
#define CYGNUM_HAL_INTERRUPT_PC6                57
117
#define CYGNUM_HAL_INTERRUPT_PC5                58
118
#define CYGNUM_HAL_INTERRUPT_PC4                59
119
#define CYGNUM_HAL_INTERRUPT_PC3                60
120
#define CYGNUM_HAL_INTERRUPT_PC2                61
121
#define CYGNUM_HAL_INTERRUPT_PC1                62
122
#define CYGNUM_HAL_INTERRUPT_PC0                63
123
 
124
#define CYGNUM_HAL_INTERRUPT_ERROR          0
125
 
126
#define CYGNUM_HAL_ISR_MAX                   CYGNUM_HAL_INTERRUPT_PC0
127
 
128
//--------------------------------------------------------------------------
129
// Interrupt controller access
130
 
131
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
132
#ifdef CYGPKG_HAL_POWERPC_MPC8XXX
133
 
134
static __inline__ void
135
cyg_hal_interrupt_mask ( cyg_uint32 vector )
136
{
137
  volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
138
  cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h);
139
  cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l);
140
 
141
  switch (vector) {
142
 
143
  case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
144
    *reg_simr_h &= ~( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
145
    break;
146
 
147
  case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
148
    *reg_simr_h &= ~( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
149
    break;
150
 
151
  case CYGNUM_HAL_INTERRUPT_TMCNT:
152
    *reg_simr_h &= ~(0x00000004);
153
    break;
154
 
155
  case CYGNUM_HAL_INTERRUPT_PIT:
156
    *reg_simr_h &= ~(0x00000002);
157
    break;
158
 
159
  case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
160
    *reg_simr_l &= ~( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
161
    break;
162
 
163
  case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
164
    *reg_simr_l &= ~( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
165
    break;
166
 
167
  case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
168
    *reg_simr_l &= ~( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
169
    break;
170
 
171
  case  CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
172
    *reg_simr_l &= ~( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
173
    break;
174
 
175
  case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
176
    *reg_simr_l &= ~( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
177
    break;
178
 
179
  default:
180
    CYG_FAIL("Unknown Interrupt in mask !!!");
181
    break;
182
  }
183
 
184
}
185
 
186
static __inline__ void
187
cyg_hal_interrupt_unmask ( cyg_uint32 vector )
188
{
189
 
190
  volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
191
  cyg_uint32 *reg_simr_h = (cyg_uint32 *) &(IMM->ic_simr_h);
192
  cyg_uint32 *reg_simr_l = (cyg_uint32 *) &(IMM->ic_simr_l);
193
 
194
  switch (vector) {
195
 
196
  case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
197
    *reg_simr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
198
    break;
199
 
200
  case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
201
    *reg_simr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
202
    break;
203
 
204
  case CYGNUM_HAL_INTERRUPT_TMCNT:
205
    *reg_simr_h |= (0x00000004);
206
    break;
207
 
208
  case CYGNUM_HAL_INTERRUPT_PIT:
209
    *reg_simr_h |= (0x00000002);
210
    break;
211
 
212
  case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
213
    *reg_simr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
214
    break;
215
 
216
  case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
217
    *reg_simr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
218
    break;
219
 
220
  case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
221
    *reg_simr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
222
    break;
223
 
224
  case  CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
225
    *reg_simr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
226
    break;
227
 
228
  case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
229
    *reg_simr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
230
    break;
231
 
232
  default:
233
    CYG_FAIL("Unknown Interrupt in unmask !!!");
234
    break;
235
  }
236
 
237
}
238
 
239
static __inline__ void
240
cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
241
{
242
 
243
  volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) CYGARC_IMM_BASE;
244
  cyg_uint32 *reg_sipnr_h = (cyg_uint32 *) &(IMM->ic_sipnr_h);
245
  cyg_uint32 *reg_sipnr_l = (cyg_uint32 *) &(IMM->ic_sipnr_l);
246
 
247
  switch (vector) {
248
 
249
  case CYGNUM_HAL_INTERRUPT_PC15 ... CYGNUM_HAL_INTERRUPT_PC0:
250
    *reg_sipnr_h |= ( (0x00010000) << (vector - CYGNUM_HAL_INTERRUPT_PC15) );
251
    break;
252
 
253
  case CYGNUM_HAL_INTERRUPT_IRQ1 ... CYGNUM_HAL_INTERRUPT_IRQ7:
254
    *reg_sipnr_h |= ( (0x00004000) >> (vector - CYGNUM_HAL_INTERRUPT_IRQ1) );
255
    break;
256
 
257
  case CYGNUM_HAL_INTERRUPT_TMCNT:
258
    *reg_sipnr_h |= (0x00000004);
259
    break;
260
 
261
  case CYGNUM_HAL_INTERRUPT_PIT:
262
    *reg_sipnr_h |= (0x00000002);
263
    break;
264
 
265
  case CYGNUM_HAL_INTERRUPT_FCC1 ... CYGNUM_HAL_INTERRUPT_FCC3:
266
    *reg_sipnr_l |= ( (0x20000000) << (CYGNUM_HAL_INTERRUPT_FCC3 - vector) );
267
    break;
268
 
269
  case CYGNUM_HAL_INTERRUPT_MCC1 ... CYGNUM_HAL_INTERRUPT_MCC2:
270
    *reg_sipnr_l |= ( (0x08000000) >> (vector - CYGNUM_HAL_INTERRUPT_MCC1) );
271
    break;
272
 
273
  case CYGNUM_HAL_INTERRUPT_SCC1 ... CYGNUM_HAL_INTERRUPT_SCC4:
274
    *reg_sipnr_l |= ( (0x00800000) >> (vector - CYGNUM_HAL_INTERRUPT_SCC1) );
275
    break;
276
 
277
  case  CYGNUM_HAL_INTERRUPT_I2C ... CYGNUM_HAL_INTERRUPT_SDMA:
278
    *reg_sipnr_l |= ( (0x00008000) >> (vector - CYGNUM_HAL_INTERRUPT_I2C) );
279
    break;
280
 
281
  case CYGNUM_HAL_INTERRUPT_TIMER1 ... CYGNUM_HAL_INTERRUPT_TIMER4:
282
    *reg_sipnr_l |= ( (0x00000010) >> (vector - CYGNUM_HAL_INTERRUPT_TIMER1) );
283
    break;
284
 
285
  default:
286
    CYG_FAIL("Unknown Interrupt in unmask !!!");
287
    break;
288
  }
289
 
290
}
291
 
292
static __inline__ void
293
cyg_hal_interrupt_configure ( cyg_uint32 vector,
294
                              cyg_bool level,
295
                              cyg_bool up )
296
{
297
  // NOT IMPLEMENTED ...
298
}
299
 
300
 
301
static __inline__ void
302
cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level )
303
{
304
 
305
  // NOT IMPLEMENTED  ....
306
  // FACT : USER should not program the same interrupt to more than
307
  // one priority position. 
308
  // FACT : Every interrupt has an assigned default priority.
309
 
310
  // PROBLEM : One has to find the previous priority of the given vector
311
  // and swap(?) it with the requested priority owner (Not nice because
312
  // it changes another interrupt's priority inadvertently)
313
 
314
}
315
 
316
// The decrementer interrupt cannnot be masked, configured or acknowledged.
317
 
318
#define HAL_INTERRUPT_MASK( _vector_ )                    \
319
    CYG_MACRO_START                                       \
320
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
321
        cyg_hal_interrupt_mask ( (_vector_) );            \
322
    CYG_MACRO_END
323
 
324
#define HAL_INTERRUPT_UNMASK( _vector_ )                  \
325
    CYG_MACRO_START                                       \
326
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
327
        cyg_hal_interrupt_unmask ( (_vector_) );          \
328
    CYG_MACRO_END
329
 
330
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )             \
331
    CYG_MACRO_START                                       \
332
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))   \
333
        cyg_hal_interrupt_acknowledge ( (_vector_) );     \
334
    CYG_MACRO_END
335
 
336
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )              \
337
    CYG_MACRO_START                                                     \
338
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))                 \
339
        cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) );  \
340
    CYG_MACRO_END
341
 
342
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )            \
343
    CYG_MACRO_START                                             \
344
    if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_))         \
345
        cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \
346
    CYG_MACRO_END
347
 
348
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
349
 
350
#endif
351
#endif
352
 
353
 
354
 
355
//-----------------------------------------------------------------------------
356
#endif // ifndef CYGONCE_VAR_INTR_H
357
// End of var_intr.h

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