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//==========================================================================
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//
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// ppc405_pci.c
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//
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// HAL variant support code for PCI on PowerPC 405GP
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Gary Thomas <gary@mlbassoc.com>
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// Contributors:
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// Date: 2003-09-02
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// Purpose: HAL PCI support
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// Description: Implementations of HAL PCI interfaces
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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#include <pkgconf/hal.h>
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#include <pkgconf/system.h>
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#include CYGBLD_HAL_PLATFORM_H
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#include <cyg/infra/cyg_type.h> // base types
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/infra/diag.h> // diag_printf() and friends
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/hal/hal_arch.h> // Register state info
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_intr.h> // Interrupt names
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#include <cyg/hal/hal_cache.h>
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#include <cyg/hal/ppc_regs.h> // Hardware definitions
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#include <cyg/hal/hal_if.h> // calling interface API
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#include <pkgconf/io_pci.h>
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#include <cyg/io/pci_hw.h>
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#include <cyg/io/pci.h>
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// PCI support
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externC void
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hal_ppc405_pci_init(void)
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{
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static int _init = 0;
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cyg_uint8 next_bus;
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cyg_uint32 cmd_state, bridge_state;
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if (_init) return;
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_init = 1;
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// Configure PCI bridge
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HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0);
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HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0);
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HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE);
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HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001);
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HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0);
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HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0);
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HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001);
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// Indicate that the bridge has been configured
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HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
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bridge_state |= 0x0001;
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HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
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// Setup for bus mastering
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HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_COMMAND, cmd_state);
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cyg_pci_init();
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if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
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#if defined(CYGPKG_IO_PCI_DEBUG)
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diag_printf("Configure PCI bus\n");
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#endif
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HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_COMMAND,
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CYG_PCI_CFG_COMMAND_MEMORY |
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CYG_PCI_CFG_COMMAND_MASTER |
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CYG_PCI_CFG_COMMAND_PARITY |
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CYG_PCI_CFG_COMMAND_SERR);
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// Setup latency timer field
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HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
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CYG_PCI_CFG_LATENCY_TIMER, 32);
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// Configure PCI bus.
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next_bus = 1;
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cyg_pci_configure_bus(0, &next_bus);
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}
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#if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS)
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if (1) {
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cyg_uint8 req;
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cyg_uint8 devfn;
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cyg_pci_device_id devid;
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cyg_pci_device dev_info;
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int i;
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devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
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while (cyg_pci_find_next(devid, &devid)) {
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devfn = CYG_PCI_DEV_GET_DEVFN(devid);
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cyg_pci_get_device_info(devid, &dev_info);
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HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req);
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diag_printf("\n");
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diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid));
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diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn));
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diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn));
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diag_printf(" Vendor Id: 0x%04X", dev_info.vendor);
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diag_printf(", Device Id: 0x%04X", dev_info.device);
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diag_printf(", Command: 0x%04X", dev_info.command);
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diag_printf(", IRQ: %d\n", req);
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for (i = 0; i < dev_info.num_bars; i++) {
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diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
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diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
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dev_info.base_size[i], dev_info.base_map[i]);
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}
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}
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}
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#endif
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}
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externC void
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hal_ppc405_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
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{
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cyg_uint8 req;
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cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);
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if ((dev >= CYG_PCI_MIN_DEV) && (dev < CYG_PCI_MAX_DEV)) {
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HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req);
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if (0 != req) {
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#ifdef CYG_PCI_IRQ_MAP
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char pci_irq_table[][4] = CYG_PCI_IRQ_MAP;
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#else
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#error "Need platform defined IRQ map"
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#endif
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*vec = pci_irq_table[dev-CYG_PCI_MIN_DEV][req-1];
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*valid = (*vec != -1);
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} else {
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/* Device will not generate interrupt requests. */
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*valid = false;
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}
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#if defined(CYGPKG_IO_PCI_DEBUG)
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diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec);
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#endif
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} else {
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*valid = false; // Invalid device
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}
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}
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// PCI configuration space access
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#define _EXT_ENABLE 0x80000000 // Could be 0x80000000
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static __inline__ cyg_uint32
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_cfg_addr(int bus, int devfn, int offset)
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{
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return _EXT_ENABLE | (bus << 16) | (devfn << 8) | (offset << 0);
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}
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externC cyg_uint8
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hal_ppc405_pci_cfg_read_uint8(int bus, int devfn, int offset)
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{
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cyg_uint32 cfg_addr;
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cyg_uint8 cfg_val = (cyg_uint8) 0xFF;
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
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#endif // CYGPKG_IO_PCI_DEBUG
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cfg_addr = _cfg_addr(bus, devfn, offset);
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HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
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HAL_READ_UINT8LE(PCIC0_CFGDATA|(offset & 0x03), cfg_val);
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%x\n", cfg_val);
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#endif // CYGPKG_IO_PCI_DEBUG
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return cfg_val;
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}
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externC cyg_uint16
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hal_ppc405_pci_cfg_read_uint16(int bus, int devfn, int offset)
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{
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cyg_uint32 cfg_addr;
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cyg_uint16 cfg_val = (cyg_uint16) 0xFFFF;
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
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#endif // CYGPKG_IO_PCI_DEBUG
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cfg_addr = _cfg_addr(bus, devfn, offset);
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HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
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HAL_READ_UINT16LE(PCIC0_CFGDATA|(offset & 0x03), cfg_val);
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%x\n", cfg_val);
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#endif // CYGPKG_IO_PCI_DEBUG
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return cfg_val;
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}
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externC cyg_uint32
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hal_ppc405_pci_cfg_read_uint32(int bus, int devfn, int offset)
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{
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cyg_uint32 cfg_addr;
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cyg_uint32 cfg_val = (cyg_uint32) 0xFFFFFFFF;
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
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#endif // CYGPKG_IO_PCI_DEBUG
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cfg_addr = _cfg_addr(bus, devfn, offset);
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HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
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HAL_READ_UINT32LE(PCIC0_CFGDATA, cfg_val);
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%x\n", cfg_val);
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#endif // CYGPKG_IO_PCI_DEBUG
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return cfg_val;
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}
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externC void
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hal_ppc405_pci_cfg_write_uint8(int bus, int devfn, int offset, cyg_uint8 cfg_val)
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{
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cyg_uint32 cfg_addr;
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
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#endif // CYGPKG_IO_PCI_DEBUG
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cfg_addr = _cfg_addr(bus, devfn, offset);
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HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
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HAL_WRITE_UINT8LE(PCIC0_CFGDATA|(offset & 0x03), cfg_val);
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}
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externC void
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hal_ppc405_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
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{
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cyg_uint32 cfg_addr;
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
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#endif // CYGPKG_IO_PCI_DEBUG
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cfg_addr = _cfg_addr(bus, devfn, offset);
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HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
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HAL_WRITE_UINT16LE(PCIC0_CFGDATA|(offset & 0x03), cfg_val);
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}
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externC void
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hal_ppc405_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
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{
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| 273 |
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cyg_uint32 cfg_addr;
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| 274 |
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#ifdef CYGPKG_IO_PCI_DEBUG
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diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
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#endif // CYGPKG_IO_PCI_DEBUG
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cfg_addr = _cfg_addr(bus, devfn, offset);
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HAL_WRITE_UINT32LE(PCIC0_CFGADDR, cfg_addr);
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HAL_WRITE_UINT32LE(PCIC0_CFGDATA, cfg_val);
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}
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/*------------------------------------------------------------------------*/
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// EOF ppc405_pci.c
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