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1 786 skrzyp 
#ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
2 
#define CYGONCE_HAL_PPC_QUICC_PPC8XX_H
3 
 
4 
//==========================================================================
5 
//
6 
//      ppc8xx.h
7 
//
8 
//      PowerPC QUICC register definitions
9 
//
10 
//==========================================================================
11 
// ####ECOSGPLCOPYRIGHTBEGIN####
12 
// -------------------------------------------
13 
// This file is part of eCos, the Embedded Configurable Operating System.
14 
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
15 
//
16 
// eCos is free software; you can redistribute it and/or modify it under
17 
// the terms of the GNU General Public License as published by the Free
18 
// Software Foundation; either version 2 or (at your option) any later
19 
// version.
20 
//
21 
// eCos is distributed in the hope that it will be useful, but WITHOUT
22 
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24 
// for more details.
25 
//
26 
// You should have received a copy of the GNU General Public License
27 
// along with eCos; if not, write to the Free Software Foundation, Inc.,
28 
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
29 
//
30 
// As a special exception, if other files instantiate templates or use
31 
// macros or inline functions from this file, or you compile this file
32 
// and link it with other works to produce a work based on this file,
33 
// this file does not by itself cause the resulting work to be covered by
34 
// the GNU General Public License. However the source code for this file
35 
// must still be made available in accordance with section (3) of the GNU
36 
// General Public License v2.
37 
//
38 
// This exception does not invalidate any other reasons why a work based
39 
// on this file might be covered by the GNU General Public License.
40 
// -------------------------------------------
41 
// ####ECOSGPLCOPYRIGHTEND####
42 
//==========================================================================
43 
//#####DESCRIPTIONBEGIN####
44 
//
45 
// Author(s):    Red Hat
46 
// Contributors: hmt
47 
// Date:         1999-06-08
48 
// Purpose:      Provide PPC QUICC definitions
49 
// Description:  Provide PPC QUICC definitions
50 
// Usage:        THIS IS NOT AN EXTERNAL API
51 
//               This file is in the include dir to share it between
52 
//               QUICC serial code and MBX initialization code.
53 
//               #include <cyg/hal/quicc/ppc8xx.h>
54 
//               ...
55 
//
56 
//
57 
//####DESCRIPTIONEND####
58 
//
59 
//==========================================================================
60 
 
61 
#ifdef __ASSEMBLER__
62 
 
63 
#define SIUMCR     0x000        /* SIU Module configuration */
64 
#define SYPCR      0x004        /* SIU System Protection Control */
65 
#define SIPEND     0x010        /* SIU Interrupt Pending Register */
66 
#define SIMASK     0x014        /* SIU Interrupt MASK Register */
67 
#define SIEL       0x018        /* SIU Interrupt Edge/Level Register */
68 
#define SIVEC      0x01C        /* SIU Interrupt Vector Register */
69 
#define SDCR       0x030        /* SDMA Config Register */
70 
#define BR0        0x100        /* Base Register 0 */
71 
#define OR0        0x104        /* Option Register 0 */
72 
#define BR1        0x108        /* Base Register 1 */
73 
#define OR1        0x10C        /* Option Register 1 */
74 
#define BR2        0x110        /* Base Register 2 */
75 
#define OR2        0x114        /* Option Register 2 */
76 
#define BR3        0x118        /* Base Register 2 */
77 
#define OR3        0x11C        /* Option Register 2 */
78 
#define BR4        0x120        /* Base Register 2 */
79 
#define OR4        0x124        /* Option Register 2 */
80 
#define BR5        0x128        /* Base Register 2 */
81 
#define OR5        0x12C        /* Option Register 2 */
82 
#define BR6        0x130        /* Base Register 2 */
83 
#define OR6        0x134        /* Option Register 2 */
84 
#define BR7        0x138        /* Base Register 2 */
85 
#define OR7        0x13C        /* Option Register 2 */
86 
#define MAR        0x164        /* Memory Address */
87 
#define MCR        0x168        /* Memory Command */
88 
#define MAMR       0x170        /* Machine A Mode Register */
89 
#define MBMR       0x174        /* Machine B Mode Register */
90 
#define MPTPR      0x17A        /* Memory Periodic Timer Prescaler */
91 
#define MDR        0x17C        /* Memory Data */
92 
#define TBSCR      0x200        /* Time Base Status and Control Register */
93 
#define RTCSC      0x220        /* Real Timer Clock Status and Control */
94 
#define PISCR      0x240        /* PIT Status and Control */
95 
#define SCCR       0x280        /* System Clock Control Register */
96 
#define PLPRCR     0x284        /* PLL, Low power & Reset Control Register */
97 
#define RTCSCK     0x320
98 
#define RTCK       0x324
99 
#define RTSECK     0x328
100 
#define RTCALK     0x32C
101 
#define PADIR      0x950        /* Port A - Pin direction */
102 
#define PAPAR      0x952        /* Port A - Pin assignment */
103 
#define PAODR      0x954        /* Port A - Open Drain Control */
104 
#define PADAT      0x956        /* Port A - Data */
105 
 
106 
#else
107 
 
108 
#include <cyg/infra/cyg_type.h>
109 
 
110 
/*****************************************************************
111 
        Communications Processor Buffer Descriptor
112 
*****************************************************************/
113 
struct cp_bufdesc {
114 
    volatile unsigned short ctrl;       /* status/control register */
115 
    volatile unsigned short length;     /* buffer length */
116 
    volatile char           *buffer;    /* buffer pointer */
117 
};
118 
 
119 
/*****************************************************************
120 
        HDLC parameter RAM
121 
*****************************************************************/
122 
 
123 
struct hdlc_pram {
124 
    /*
125 
     * SCC parameter RAM
126 
     */
127 
    unsigned short      rbase;          /* RX BD base address */
128 
    unsigned short      tbase;          /* TX BD base address */
129 
    unsigned char       rfcr;           /* Rx function code */
130 
    unsigned char       tfcr;           /* Tx function code */
131 
    unsigned short      mrblr;          /* Rx buffer length */
132 
    unsigned long       rstate;         /* Rx internal state */
133 
    unsigned long       rptr;           /* Rx internal data pointer */
134 
    unsigned short      rbptr;          /* rb BD Pointer */
135 
    unsigned short      rcount;         /* Rx internal byte count */
136 
    unsigned long       rtemp;          /* Rx temp */
137 
    unsigned long       tstate;         /* Tx internal state */
138 
    unsigned long       tptr;           /* Tx internal data pointer */
139 
    unsigned short      tbptr;          /* Tx BD pointer */
140 
    unsigned short      tcount;         /* Tx byte count */
141 
    unsigned long       ttemp;          /* Tx temp */
142 
    unsigned long       rcrc;           /* temp receive CRC */
143 
    unsigned long       tcrc;           /* temp transmit CRC */
144 
 
145 
    /*
146 
     * HDLC specific parameter RAM
147 
     */
148 
    unsigned char       RSRVD1[4];
149 
    unsigned long       c_mask;         /* CRC constant */
150 
    unsigned long       c_pres;         /* CRC preset */
151 
    unsigned short      disfc;          /* discarded frame counter */
152 
    unsigned short      crcec;          /* CRC error counter */
153 
    unsigned short      abtsc;          /* abort sequence counter */
154 
    unsigned short      nmarc;          /* nonmatching address rx cnt */
155 
    unsigned short      retrc;          /* frame retransmission cnt */
156 
    unsigned short      mflr;           /* maximum frame length reg */
157 
    unsigned short      max_cnt;        /* maximum length counter */
158 
    unsigned short      rfthr;          /* received frames threshold */
159 
    unsigned short      rfcnt;          /* received frames count */
160 
    unsigned short      hmask;          /* user defined frm addr mask */
161 
    unsigned short      haddr1;         /* user defined frm address 1 */
162 
    unsigned short      haddr2;         /* user defined frm address 2 */
163 
    unsigned short      haddr3;         /* user defined frm address 3 */
164 
    unsigned short      haddr4;         /* user defined frm address 4 */
165 
    unsigned short      tmp;            /* temp */
166 
    unsigned short      tmp_mb;         /* temp */
167 
};
168 
 
169 
 
170 
/*****************************************************************
171 
        ASYNC HDLC parameter RAM
172 
*****************************************************************/
173 
 
174 
struct async_hdlc_pram {
175 
    /*
176 
     * SCC parameter RAM
177 
     */
178 
    unsigned short      rbase;          /* RX BD base address */
179 
    unsigned short      tbase;          /* TX BD base address */
180 
    unsigned char       rfcr;           /* Rx function code */
181 
    unsigned char       tfcr;           /* Tx function code */
182 
    unsigned short      mrblr;          /* Rx buffer length */
183 
    unsigned long       rstate;         /* Rx internal state */
184 
    unsigned long       rptr;           /* Rx internal data pointer */
185 
    unsigned short      rbptr;          /* rb BD Pointer */
186 
    unsigned short      rcount;         /* Rx internal byte count */
187 
    unsigned long       rtemp;          /* Rx temp */
188 
    unsigned long       tstate;         /* Tx internal state */
189 
    unsigned long       tptr;           /* Tx internal data pointer */
190 
    unsigned short      tbptr;          /* Tx BD pointer */
191 
    unsigned short      tcount;         /* Tx byte count */
192 
    unsigned long       ttemp;          /* Tx temp */
193 
    unsigned long       rcrc;           /* temp receive CRC */
194 
    unsigned long       tcrc;           /* temp transmit CRC */
195 
 
196 
    /*
197 
     * ASYNC HDLC specific parameter RAM
198 
     */
199 
    unsigned char       RSRVD1[4];
200 
    unsigned long       c_mask;         /* CRC constant */
201 
    unsigned long       c_pres;         /* CRC preset */
202 
    unsigned short      bof;            /* begining of flag character */
203 
    unsigned short      eof;            /* end of flag character */
204 
    unsigned short      esc;            /* control escape character */
205 
    unsigned char       RSRVD2[4];
206 
    unsigned short      zero;           /* zero */
207 
    unsigned char       RSRVD3[2];
208 
    unsigned short      rfthr;          /* received frames threshold */
209 
    unsigned char       RSRVD4[4];
210 
    unsigned long       txctl_tbl;      /* Tx ctl char mapping table */
211 
    unsigned long       rxctl_tbl;      /* Rx ctl char mapping table */
212 
    unsigned short      nof;            /* Number of opening flags */
213 
};
214 
 
215 
 
216 
/*****************************************************************
217 
        UART parameter RAM
218 
*****************************************************************/
219 
 
220 
/*
221 
 * bits in uart control characters table
222 
 */
223 
#define CC_INVALID      0x8000          /* control character is valid */
224 
#define CC_REJ          0x4000          /* don't store char in buffer */
225 
#define CC_CHAR         0x00ff          /* control character */
226 
 
227 
/* UART */
228 
struct uart_pram {
229 
    /*
230 
     * SCC parameter RAM
231 
     */
232 
    unsigned short      rbase;          /* RX BD base address */
233 
    unsigned short      tbase;          /* TX BD base address */
234 
    unsigned char       rfcr;           /* Rx function code */
235 
    unsigned char       tfcr;           /* Tx function code */
236 
    unsigned short      mrblr;          /* Rx buffer length */
237 
    unsigned long       rstate;         /* Rx internal state */
238 
    unsigned long       rptr;           /* Rx internal data pointer */
239 
    unsigned short      rbptr;          /* rb BD Pointer */
240 
    unsigned short      rcount;         /* Rx internal byte count */
241 
    unsigned long       rx_temp;        /* Rx temp */
242 
    unsigned long       tstate;         /* Tx internal state */
243 
    unsigned long       tptr;           /* Tx internal data pointer */
244 
    unsigned short      tbptr;          /* Tx BD pointer */
245 
    unsigned short      tcount;         /* Tx byte count */
246 
    unsigned long       ttemp;          /* Tx temp */
247 
    unsigned long       rcrc;           /* temp receive CRC */
248 
    unsigned long       tcrc;           /* temp transmit CRC */
249 
 
250 
    /*
251 
     * UART specific parameter RAM
252 
     */
253 
    unsigned char       RSRVD1[8];
254 
    unsigned short      max_idl;        /* maximum idle characters */
255 
    unsigned short      idlc;           /* rx idle counter (internal) */
256 
    unsigned short      brkcr;          /* break count register */
257 
 
258 
    unsigned short      parec;          /* Rx parity error counter */
259 
    unsigned short      frmer;          /* Rx framing error counter */
260 
    unsigned short      nosec;          /* Rx noise counter */
261 
    unsigned short      brkec;          /* Rx break character counter */
262 
    unsigned short      brkln;          /* Reaceive break length */
263 
 
264 
    unsigned short      uaddr1;         /* address character 1 */
265 
    unsigned short      uaddr2;         /* address character 2 */
266 
    unsigned short      rtemp;          /* temp storage */
267 
    unsigned short      toseq;          /* Tx out of sequence char */
268 
    unsigned short      cc[8];          /* Rx control characters */
269 
    unsigned short      rccm;           /* Rx control char mask */
270 
    unsigned short      rccr;           /* Rx control char register */
271 
    unsigned short      rlbc;           /* Receive last break char */
272 
};
273 
 
274 
 
275 
 
276 
/*****************************************************************
277 
        BISYNC parameter RAM
278 
*****************************************************************/
279 
 
280 
struct bisync_pram {
281 
    /*
282 
     * SCC parameter RAM
283 
     */
284 
    unsigned short      rbase;          /* RX BD base address */
285 
    unsigned short      tbase;          /* TX BD base address */
286 
    unsigned char       rfcr;           /* Rx function code */
287 
    unsigned char       tfcr;           /* Tx function code */
288 
    unsigned short      mrblr;          /* Rx buffer length */
289 
    unsigned long       rstate;         /* Rx internal state */
290 
    unsigned long       rptr;           /* Rx internal data pointer */
291 
    unsigned short      rbptr;          /* rb BD Pointer */
292 
    unsigned short      rcount;         /* Rx internal byte count */
293 
    unsigned long       rtemp;          /* Rx temp */
294 
    unsigned long       tstate;         /* Tx internal state */
295 
    unsigned long       tptr;           /* Tx internal data pointer */
296 
    unsigned short      tbptr;          /* Tx BD pointer */
297 
    unsigned short      tcount;         /* Tx byte count */
298 
    unsigned long       ttemp;          /* Tx temp */
299 
    unsigned long       rcrc;           /* temp receive CRC */
300 
    unsigned long       tcrc;           /* temp transmit CRC */
301 
 
302 
    /*
303 
     * BISYNC specific parameter RAM
304 
     */
305 
    unsigned char       RSRVD1[4];
306 
    unsigned long       crcc;           /* CRC Constant Temp Value */
307 
    unsigned short      prcrc;          /* Preset Receiver CRC-16/LRC */
308 
    unsigned short      ptcrc;          /* Preset Transmitter CRC-16/LRC */
309 
    unsigned short      parec;          /* Receive Parity Error Counter */
310 
    unsigned short      bsync;          /* BISYNC SYNC Character */
311 
    unsigned short      bdle;           /* BISYNC DLE Character */
312 
    unsigned short      cc[8];          /* Rx control characters */
313 
    unsigned short      rccm;           /* Receive Control Character Mask */
314 
};
315 
 
316 
/*****************************************************************
317 
        IOM2 parameter RAM
318 
        (overlaid on tx bd[5] of SCC channel[2])
319 
*****************************************************************/
320 
struct iom2_pram {
321 
    unsigned short      ci_data;        /* ci data */
322 
    unsigned short      monitor_data;   /* monitor data */
323 
    unsigned short      tstate;         /* transmitter state */
324 
    unsigned short      rstate;         /* receiver state */
325 
};
326 
 
327 
/*****************************************************************
328 
        SPI/SMC parameter RAM
329 
        (overlaid on tx bd[6,7] of SCC channel[2])
330 
*****************************************************************/
331 
 
332 
#define SPI_R   0x8000          /* Ready bit in BD */
333 
 
334 
struct spi_pram {
335 
    unsigned short      rbase;          /* Rx BD Base Address */
336 
    unsigned short      tbase;          /* Tx BD Base Address */
337 
    unsigned char       rfcr;           /* Rx function code */
338 
    unsigned char       tfcr;           /* Tx function code */
339 
    unsigned short      mrblr;          /* Rx buffer length */
340 
    unsigned long       rstate;         /* Rx internal state */
341 
    unsigned long       rptr;           /* Rx internal data pointer */
342 
    unsigned short      rbptr;          /* rb BD Pointer */
343 
    unsigned short      rcount;         /* Rx internal byte count */
344 
    unsigned long       rtemp;          /* Rx temp */
345 
    unsigned long       tstate;         /* Tx internal state */
346 
    unsigned long       tptr;           /* Tx internal data pointer */
347 
    unsigned short      tbptr;          /* Tx BD pointer */
348 
    unsigned short      tcount;         /* Tx byte count */
349 
    unsigned long       ttemp[2];       /* Tx temp */
350 
    unsigned short      rpbase;         /* Relocated param block pointer */
351 
    unsigned short      res;            /* unused */
352 
};
353 
 
354 
struct smc_uart_pram {
355 
    unsigned short      rbase;          /* Rx BD Base Address */
356 
    unsigned short      tbase;          /* Tx BD Base Address */
357 
    unsigned char       rfcr;           /* Rx function code */
358 
    unsigned char       tfcr;           /* Tx function code */
359 
    unsigned short      mrblr;          /* Rx buffer length */
360 
    unsigned long       rstate;         /* Rx internal state */
361 
    unsigned long       rptr;           /* Rx internal data pointer */
362 
    unsigned short      rbptr;          /* rb BD Pointer */
363 
    unsigned short      rcount;         /* Rx internal byte count */
364 
    unsigned long       rtemp;          /* Rx temp */
365 
    unsigned long       tstate;         /* Tx internal state */
366 
    unsigned long       tptr;           /* Tx internal data pointer */
367 
    unsigned short      tbptr;          /* Tx BD pointer */
368 
    unsigned short      tcount;         /* Tx byte count */
369 
    unsigned long       ttemp;          /* Tx temp */
370 
    unsigned short      max_idl;        /* Maximum IDLE Characters */
371 
    unsigned short      idlc;           /* Temporary IDLE Counter */
372 
    unsigned short      brkln;          /* Last Rx Break Length */
373 
    unsigned short      brkec;          /* Rx Break Condition Counter */
374 
    unsigned short      brkcr;          /* Break Count Register (Tx) */
375 
    unsigned short      r_mask;         /* Temporary bit mask */
376 
};
377 
 
378 
struct smc_trnsp_pram {
379 
    unsigned short      rbase;          /* Rx BD Base Address */
380 
    unsigned short      tbase;          /* Tx BD Base Address */
381 
    unsigned char       rfcr;           /* Rx function code */
382 
    unsigned char       tfcr;           /* Tx function code */
383 
    unsigned short      mrblr;          /* Rx buffer length */
384 
    unsigned long       rstate;         /* Rx internal state */
385 
    unsigned long       rptr;           /* Rx internal data pointer */
386 
    unsigned short      rbptr;          /* rb BD Pointer */
387 
    unsigned short      rcount;         /* Rx internal byte count */
388 
    unsigned long       rtemp;          /* Rx temp */
389 
    unsigned long       tstate;         /* Tx internal state */
390 
    unsigned long       tptr;           /* Tx internal data pointer */
391 
    unsigned short      tbptr;          /* Tx BD pointer */
392 
    unsigned short      tcount;         /* Tx byte count */
393 
    unsigned long       ttemp;          /* Tx temp */
394 
    unsigned short      RSRVD[5];       /* RSRVD */
395 
};
396 
 
397 
struct centronics_pram {
398 
    unsigned short      rbase;          /* Rx BD Base Address */
399 
    unsigned short      tbase;          /* Tx BD Base Address */
400 
    unsigned char       fcr;            /* function code */
401 
    unsigned char       smask;          /* Status Mask */
402 
    unsigned short      mrblr;          /* Rx buffer length */
403 
    unsigned long       rstate;         /* Rx internal state */
404 
    unsigned long       rptr;           /* Rx internal data pointer */
405 
    unsigned short      rbptr;          /* rb BD Pointer */
406 
    unsigned short      rcount;         /* Rx internal byte count */
407 
    unsigned long       rtemp;          /* Rx temp */
408 
    unsigned long       tstate;         /* Tx internal state */
409 
    unsigned long       tptr;           /* Tx internal data pointer */
410 
    unsigned short      tbptr;          /* Tx BD pointer */
411 
    unsigned short      tcount;         /* Tx byte count */
412 
    unsigned long       ttemp;          /* Tx temp */
413 
    unsigned short      max_sl;         /* Maximum Silence period */
414 
    unsigned short      sl_cnt;         /* Silence Counter */
415 
    unsigned short      char1;          /* CONTROL char 1 */
416 
    unsigned short      char2;          /* CONTROL char 2 */
417 
    unsigned short      char3;          /* CONTROL char 3 */
418 
    unsigned short      char4;          /* CONTROL char 4 */
419 
    unsigned short      char5;          /* CONTROL char 5 */
420 
    unsigned short      char6;          /* CONTROL char 6 */
421 
    unsigned short      char7;          /* CONTROL char 7 */
422 
    unsigned short      char8;          /* CONTROL char 8 */
423 
    unsigned short      rccm;           /* Rx Control Char Mask */
424 
    unsigned short      rccr;           /* Rx Char Control Register */
425 
};
426 
 
427 
struct idma_pram {
428 
    unsigned short      ibase;          /* IDMA BD Base Address */
429 
    unsigned short      ibptr;          /* IDMA buffer descriptor pointer */
430 
    unsigned long       istate;         /* IDMA internal state */
431 
    unsigned long       itemp;          /* IDMA temp */
432 
};
433 
 
434 
struct ethernet_pram {
435 
    /*
436 
     * SCC parameter RAM
437 
     */
438 
    unsigned short      rbase;          /* RX BD base address */
439 
    unsigned short      tbase;          /* TX BD base address */
440 
    unsigned char       rfcr;           /* Rx function code */
441 
    unsigned char       tfcr;           /* Tx function code */
442 
    unsigned short      mrblr;          /* Rx buffer length */
443 
    unsigned long       rstate;         /* Rx internal state */
444 
    unsigned long       rptr;           /* Rx internal data pointer */
445 
    unsigned short      rbptr;          /* rb BD Pointer */
446 
    unsigned short      rcount;         /* Rx internal byte count */
447 
    unsigned long       rtemp;          /* Rx temp */
448 
    unsigned long       tstate;         /* Tx internal state */
449 
    unsigned long       tptr;           /* Tx internal data pointer */
450 
    unsigned short      tbptr;          /* Tx BD pointer */
451 
    unsigned short      tcount;         /* Tx byte count */
452 
    unsigned long       ttemp;          /* Tx temp */
453 
    unsigned long       rcrc;           /* temp receive CRC */
454 
    unsigned long       tcrc;           /* temp transmit CRC */
455 
 
456 
    /*
457 
     * ETHERNET specific parameter RAM
458 
     */
459 
    unsigned long       c_pres;         /* preset CRC */
460 
    unsigned long       c_mask;         /* constant mask for CRC */
461 
    unsigned long       crcec;          /* CRC error counter */
462 
    unsigned long       alec;           /* alighnment error counter */
463 
    unsigned long       disfc;          /* discard frame counter */
464 
    unsigned short      pads;           /* short frame PAD characters */
465 
    unsigned short      ret_lim;        /* retry limit threshold */
466 
    unsigned short      ret_cnt;        /* retry limit counter */
467 
    unsigned short      mflr;           /* maximum frame length reg */
468 
    unsigned short      minflr;         /* minimum frame length reg */
469 
    unsigned short      maxd1;          /* maximum DMA1 length reg */
470 
    unsigned short      maxd2;          /* maximum DMA2 length reg */
471 
    unsigned short      maxd;           /* rx max DMA */
472 
    unsigned short      dma_cnt;        /* rx dma counter */
473 
    unsigned short      max_b;          /* max bd byte count */
474 
    unsigned short      gaddr1;         /* group address filter 1 */
475 
    unsigned short      gaddr2;         /* group address filter 2 */
476 
    unsigned short      gaddr3;         /* group address filter 3 */
477 
    unsigned short      gaddr4;         /* group address filter 4 */
478 
    unsigned long       tbuf0_data0;    /* save area 0 - current frm */
479 
    unsigned long       tbuf0_data1;    /* save area 1 - current frm */
480 
    unsigned long       tbuf0_rba0;
481 
    unsigned long       tbuf0_crc;
482 
    unsigned short      tbuf0_bcnt;
483 
    unsigned short      paddr_h;        /* physical address (MSB) */
484 
    unsigned short      paddr_m;        /* physical address */
485 
    unsigned short      paddr_l;        /* physical address (LSB) */
486 
    unsigned short      p_per;          /* persistence */
487 
    unsigned short      rfbd_ptr;       /* rx first bd pointer */
488 
    unsigned short      tfbd_ptr;       /* tx first bd pointer */
489 
    unsigned short      tlbd_ptr;       /* tx last bd pointer */
490 
    unsigned long       tbuf1_data0;    /* save area 0 - next frame */
491 
    unsigned long       tbuf1_data1;    /* save area 1 - next frame */
492 
    unsigned long       tbuf1_rba0;
493 
    unsigned long       tbuf1_crc;
494 
    unsigned short      tbuf1_bcnt;
495 
    unsigned short      tx_len;         /* tx frame length counter */
496 
    unsigned short      iaddr1;         /* individual address filter 1*/
497 
    unsigned short      iaddr2;         /* individual address filter 2*/
498 
    unsigned short      iaddr3;         /* individual address filter 3*/
499 
    unsigned short      iaddr4;         /* individual address filter 4*/
500 
    unsigned short      boff_cnt;       /* back-off counter */
501 
    unsigned short      taddr_h;        /* temp address (MSB) */
502 
    unsigned short      taddr_m;        /* temp address */
503 
    unsigned short      taddr_l;        /* temp address (LSB) */
504 
};
505 
 
506 
struct transparent_pram {
507 
    /*
508 
     * SCC parameter RAM
509 
     */
510 
    unsigned short      rbase;          /* RX BD base address */
511 
    unsigned short      tbase;          /* TX BD base address */
512 
    unsigned char       rfcr;           /* Rx function code */
513 
    unsigned char       tfcr;           /* Tx function code */
514 
    unsigned short      mrblr;          /* Rx buffer length */
515 
    unsigned long       rstate;         /* Rx internal state */
516 
    unsigned long       rptr;           /* Rx internal data pointer */
517 
    unsigned short      rbptr;          /* rb BD Pointer */
518 
    unsigned short      rcount;         /* Rx internal byte count */
519 
    unsigned long       rtemp;          /* Rx temp */
520 
    unsigned long       tstate;         /* Tx internal state */
521 
    unsigned long       tptr;           /* Tx internal data pointer */
522 
    unsigned short      tbptr;          /* Tx BD pointer */
523 
    unsigned short      tcount;         /* Tx byte count */
524 
    unsigned long       ttemp;          /* Tx temp */
525 
    unsigned long       rcrc;           /* temp receive CRC */
526 
    unsigned long       tcrc;           /* temp transmit CRC */
527 
 
528 
    /*
529 
     * TRANSPARENT specific parameter RAM
530 
     */
531 
    unsigned long       crc_p;          /* CRC Preset */
532 
    unsigned long       crc_c;          /* CRC constant */
533 
};
534 
 
535 
struct timer_pram {
536 
    /*
537 
     * RISC timers parameter RAM
538 
     */
539 
    unsigned short      tm_base;        /* RISC timer table base adr */
540 
    unsigned short      tm_ptr;         /* RISC timer table pointer */
541 
    unsigned short      r_tmr;          /* RISC timer mode register */
542 
    unsigned short      r_tmv;          /* RISC timer valid register */
543 
    unsigned long       tm_cmd;         /* RISC timer cmd register */
544 
    unsigned long       tm_cnt;         /* RISC timer internal cnt */
545 
};
546 
 
547 
struct ucode_pram {
548 
    /*
549 
     * RISC ucode parameter RAM
550 
     */
551 
    unsigned short      rev_num;        /* Ucode Revision Number */
552 
    unsigned short      d_ptr;          /* MISC Dump area pointer */
553 
    unsigned long       temp1;          /* MISC Temp1 */
554 
    unsigned long       temp2;          /* MISC Temp2 */
555 
};
556 
 
557 
struct i2c_pram {
558 
    /*
559 
     * I2C parameter RAM
560 
     */
561 
    unsigned short      rbase;          /* RX BD base address */
562 
    unsigned short      tbase;          /* TX BD base address */
563 
    unsigned char       rfcr;           /* Rx function code */
564 
    unsigned char       tfcr;           /* Tx function code */
565 
    unsigned short      mrblr;          /* Rx buffer length */
566 
    unsigned long       rstate;         /* Rx internal state */
567 
    unsigned long       rptr;           /* Rx internal data pointer */
568 
    unsigned short      rbptr;          /* rb BD Pointer */
569 
    unsigned short      rcount;         /* Rx internal byte count */
570 
    unsigned long       rtemp;          /* Rx temp */
571 
    unsigned long       tstate;         /* Tx internal state */
572 
    unsigned long       tptr;           /* Tx internal data pointer */
573 
    unsigned short      tbptr;          /* Tx BD pointer */
574 
    unsigned short      tcount;         /* Tx byte count */
575 
    unsigned long       ttemp[2];       /* Tx temp */
576 
    unsigned short      rpbase;         /* Relocated param block pointer */
577 
    unsigned short      res;            /* unused */
578 
};
579 
 
580 
/*
581 
 * definitions of EPPC memory structures
582 
 */
583 
typedef struct eppc {
584 
    /* BASE + 0x0000: INTERNAL REGISTERS */
585 
 
586 
    /* SIU */
587 
    volatile unsigned long      siu_mcr;        /* module configuration reg */
588 
    volatile unsigned long      siu_sypcr;      /* System protection cnt */
589 
    unsigned char               RSRVD58[0x6];
590 
    volatile unsigned short     siu_swsr;       /* sw service */
591 
    volatile unsigned long      siu_sipend;     /* Interrupt pend reg */
592 
    volatile unsigned long      siu_simask;     /* Interrupt mask reg */
593 
    volatile unsigned long      siu_siel;       /* Interrupt edge level mask reg */
594 
    volatile unsigned long      siu_sivec;      /* Interrupt vector */
595 
    volatile unsigned long      siu_tesr;       /* Transfer error status */
596 
    volatile unsigned char      RSRVD1[0xc];
597 
    volatile unsigned long      dma_sdcr;       /* SDMA configuration reg */
598 
    unsigned char               RSRVD55[0x4c];
599 
 
600 
    /* PCMCIA */
601 
    volatile unsigned long      pcmcia_pbr0;    /* PCMCIA Base Reg: Window 0 */
602 
    volatile unsigned long      pcmcia_por0;    /* PCMCIA Option Reg: Window 0 */
603 
    volatile unsigned long      pcmcia_pbr1;    /* PCMCIA Base Reg: Window 1 */
604 
    volatile unsigned long      pcmcia_por1;    /* PCMCIA Option Reg: Window 1 */
605 
    volatile unsigned long      pcmcia_pbr2;    /* PCMCIA Base Reg: Window 2 */
606 
    volatile unsigned long      pcmcia_por2;    /* PCMCIA Option Reg: Window 2 */
607 
    volatile unsigned long      pcmcia_pbr3;    /* PCMCIA Base Reg: Window 3 */
608 
    volatile unsigned long      pcmcia_por3;    /* PCMCIA Option Reg: Window 3 */
609 
    volatile unsigned long      pcmcia_pbr4;    /* PCMCIA Base Reg: Window 4 */
610 
    volatile unsigned long      pcmcia_por4;    /* PCMCIA Option Reg: Window 4 */
611 
    volatile unsigned long      pcmcia_pbr5;    /* PCMCIA Base Reg: Window 5 */
612 
    volatile unsigned long      pcmcia_por5;    /* PCMCIA Option Reg: Window 5 */
613 
    volatile unsigned long      pcmcia_pbr6;    /* PCMCIA Base Reg: Window 6 */
614 
    volatile unsigned long      pcmcia_por6;    /* PCMCIA Option Reg: Window 6 */
615 
    volatile unsigned long      pcmcia_pbr7;    /* PCMCIA Base Reg: Window 7 */
616 
    volatile unsigned long      pcmcia_por7;    /* PCMCIA Option Reg: Window 7 */
617 
    volatile unsigned char      RSRVD2[0x20];
618 
    volatile unsigned long      pcmcia_pgcra;   /* PCMCIA Slot A Control  Reg */
619 
    volatile unsigned long      pcmcia_pgcrb;   /* PCMCIA Slot B Control  Reg */
620 
    volatile unsigned long      pcmcia_pscr;    /* PCMCIA Status Reg */
621 
    volatile unsigned char      RSRVD2a[0x4];
622 
    volatile unsigned long      pcmcia_pipr;    /* PCMCIA Pins Value Reg */
623 
    volatile unsigned char      RSRVD2b[0x4];
624 
    volatile unsigned long      pcmcia_per;     /* PCMCIA Enable Reg */
625 
    volatile unsigned char      RSRVD2c[0x4];
626 
 
627 
    /* MEMC */
628 
    volatile unsigned long      memc_br0;       /* base register 0 */
629 
    volatile unsigned long      memc_or0;       /* option register 0 */
630 
    volatile unsigned long      memc_br1;       /* base register 1 */
631 
    volatile unsigned long      memc_or1;       /* option register 1 */
632 
    volatile unsigned long      memc_br2;       /* base register 2 */
633 
    volatile unsigned long      memc_or2;       /* option register 2 */
634 
    volatile unsigned long      memc_br3;       /* base register 3 */
635 
    volatile unsigned long      memc_or3;       /* option register 3 */
636 
    volatile unsigned long      memc_br4;       /* base register 3 */
637 
    volatile unsigned long      memc_or4;       /* option register 3 */
638 
    volatile unsigned long      memc_br5;       /* base register 3 */
639 
    volatile unsigned long      memc_or5;       /* option register 3 */
640 
    volatile unsigned long      memc_br6;       /* base register 3 */
641 
    volatile unsigned long      memc_or6;       /* option register 3 */
642 
    volatile unsigned long      memc_br7;       /* base register 3 */
643 
    volatile unsigned long      memc_or7;       /* option register 3 */
644 
    volatile unsigned char      RSRVD3[0x24];
645 
    volatile unsigned long      memc_mar;       /* Memory address */
646 
    volatile unsigned long      memc_mcr;       /* Memory command */
647 
    volatile unsigned char      RSRVD4[0x4];
648 
    volatile unsigned long      memc_mamr;      /* Machine A mode */
649 
    volatile unsigned long      memc_mbmr;      /* Machine B mode */
650 
    volatile unsigned short     memc_mstat;     /* Memory status */
651 
    volatile unsigned short     memc_mptpr;     /* Memory preidic timer prescalar */
652 
    volatile unsigned long      memc_mdr;       /* Memory data */
653 
    volatile unsigned char      RSRVD5[0x80];
654 
 
655 
    /* SYSTEM INTEGRATION TIMERS */
656 
    volatile unsigned short     simt_tbscr;     /* Time base stat&ctr */
657 
    volatile unsigned char      RSRVD100[0x2];
658 
    volatile unsigned long      simt_tbreff0;   /* Time base reference 0 */
659 
    volatile unsigned long      simt_tbreff1;   /* Time base reference 1 */
660 
    volatile unsigned char      RSRVD6[0x14];
661 
    volatile unsigned short     simt_rtcsc;     /* Realtime clk stat&cntr 1 */
662 
    volatile unsigned char      RSRVD110[0x2];
663 
    volatile unsigned long      simt_rtc;       /* Realtime clock */
664 
    volatile unsigned long      simt_rtsec;     /* Realtime alarm seconds */
665 
    volatile unsigned long      simt_rtcal;     /* Realtime alarm */
666 
    volatile unsigned char      RSRVD56[0x10];
667 
    volatile unsigned long      simt_piscr;     /* PIT stat&ctrl */
668 
    volatile unsigned long      simt_pitc;      /* PIT counter */
669 
    volatile unsigned long      simt_pitr;      /* PIT */
670 
    volatile unsigned char      RSRVD7[0x34];
671 
 
672 
    /* CLOCKS, RESET */
673 
    volatile unsigned long      clkr_sccr;      /* System clk cntrl */
674 
    volatile unsigned long      clkr_plprcr;    /* PLL reset&ctrl */
675 
    volatile unsigned long      clkr_rsr;       /* reset status */
676 
    volatile unsigned char      RSRVD66a[0x74];
677 
 
678 
    /* System Integration Timers Keys */
679 
    volatile unsigned long      simt_tbscrk;    /* Timebase Status&Ctrl Key */
680 
    volatile unsigned long      simt_tbreff0k;  /* Timebase Reference 0 Key */
681 
    volatile unsigned long      simt_tbreff1k;  /* Timebase Reference 1 Key */
682 
    volatile unsigned long      simt_tbk;       /* Timebase and Decrementer Key */
683 
    volatile unsigned char      RSRVD66b[0x10];
684 
    volatile unsigned long      simt_rtcsck;    /* Real-Time Clock Status&Ctrl Key */
685 
    volatile unsigned long      simt_rtck;      /* Real-Time Clock Key */
686 
    volatile unsigned long      simt_rtseck;    /* Real-Time Alarm Seconds Key */
687 
    volatile unsigned long      simt_rtcalk;    /* Real-Time Alarm Key */
688 
    volatile unsigned char      RSRVD66c[0x10];
689 
    volatile unsigned long      simt_piscrk;    /* Periodic Interrupt Status&Ctrl Key */
690 
    volatile unsigned long      simt_pitck;     /* Periodic Interrupt Count Key */
691 
    volatile unsigned char      RSRVD66d[0x38];
692 
 
693 
 
694 
    /* Clock and Reset Keys */
695 
    volatile unsigned long      clkr_sccrk;     /* System Clock Control Key */
696 
    volatile unsigned long      clkr_plprcrk;   /* PLL, Low Power and Reset Control Key */
697 
    volatile unsigned long      clkr_rsrk;      /* Reset Status Key */
698 
    volatile unsigned char      RSRVD66e[0x4b4];
699 
 
700 
    volatile unsigned long      lcd_lccr;       /* configuration Reg */
701 
    volatile unsigned long      lcd_lchcr;      /* Horizontal ctl Reg */
702 
    volatile unsigned long      lcd_lcvcr;      /* Vertical ctl Reg */
703 
    unsigned char               RSRVD67[4];
704 
    volatile unsigned long      lcd_lcfaa;      /* Frame buffer A Address */
705 
    volatile unsigned long      lcd_lcfba;      /* Frame buffer B Address */
706 
    volatile unsigned char      lcd_lcsr;       /* Status Reg */
707 
    volatile unsigned char      RSRVD9[0x7];
708 
 
709 
    /* I2C */
710 
    volatile unsigned char      i2c_i2mod;      /* i2c mode */
711 
    unsigned char               RSRVD59[3];
712 
    volatile unsigned char      i2c_i2add;      /* i2c address */
713 
    unsigned char               RSRVD60[3];
714 
    volatile unsigned char      i2c_i2brg;      /* i2c brg */
715 
    unsigned char               RSRVD61[3];
716 
    volatile unsigned char      i2c_i2com;      /* i2c command */
717 
    unsigned char               RSRVD62[3];
718 
    volatile unsigned char      i2c_i2cer;      /* i2c event */
719 
    unsigned char               RSRVD63[3];
720 
    volatile unsigned char      i2c_i2cmr;      /* i2c mask */
721 
    volatile unsigned char      RSRVD10[0x0b];
722 
    volatile unsigned char      i2c_spare_pram[0x80];  /* Used by patched ucode */
723 
 
724 
    /* DMA */
725 
    volatile unsigned char      RSRVD11[0x4];
726 
    volatile unsigned long      dma_sdar;       /* SDMA address reg */
727 
    volatile unsigned char      dma_sdsr;       /* SDMA status reg */
728 
    volatile unsigned char      RSRVD12[0x3];
729 
    volatile unsigned char      dma_sdmr;       /* SDMA mask reg */
730 
    volatile unsigned char      RSRVD13[0x3];
731 
    volatile unsigned char      dma_idsr1;      /* IDMA1 status reg */
732 
    volatile unsigned char      RSRVD14[0x3];
733 
    volatile unsigned char      dma_idmr1;      /* IDMA1 mask reg */
734 
    volatile unsigned char      RSRVD15[0x3];
735 
    volatile unsigned char      dma_idsr2;      /* IDMA2 status reg */
736 
    volatile unsigned char      RSRVD16[0x3];
737 
    volatile unsigned char      dma_idmr2;      /* IDMA2 mask reg */
738 
    volatile unsigned char      RSRVD17[0x13];
739 
 
740 
    /* CPM Interrupt Controller */
741 
    volatile unsigned short     cpmi_civr;      /* CP interrupt vector reg */
742 
    volatile unsigned char      RSRVD19[0xe];
743 
    volatile unsigned long      cpmi_cicr;      /* CP interrupt configuration reg */
744 
    volatile unsigned long      cpmi_cipr;      /* CP interrupt pending reg */
745 
    volatile unsigned long      cpmi_cimr;      /* CP interrupt mask reg */
746 
    volatile unsigned long      cpmi_cisr;      /* CP interrupt in-service reg */
747 
 
748 
    /* I/O port */
749 
    volatile unsigned short     pio_padir;      /* port A data direction reg */
750 
    volatile unsigned short     pio_papar;      /* port A pin assignment reg */
751 
    volatile unsigned short     pio_paodr;      /* port A open drain reg */
752 
    volatile unsigned short     pio_padat;      /* port A data register */
753 
    volatile unsigned char      RSRVD20[0x8];
754 
    volatile unsigned short     pio_pcdir;      /* port C data direction reg */
755 
    volatile unsigned short     pio_pcpar;      /* port C pin assignment reg */
756 
    volatile unsigned short     pio_pcso;       /* port C special options */
757 
    volatile unsigned short     pio_pcdat;      /* port C data register */
758 
    volatile unsigned short     pio_pcint;      /* port C interrupt cntrl reg */
759 
    unsigned char               RSRVD64[6];
760 
    volatile unsigned short     pio_pddir;      /* port D Data Direction reg */
761 
    volatile unsigned short     pio_pdpar;      /* port D pin assignment reg */
762 
    unsigned char               RSRVD65[2];
763 
    volatile unsigned short     pio_pddat;      /* port D data reg */
764 
    volatile unsigned char      RSRVD21[0x8];
765 
 
766 
    /* CPM Timer */
767 
    volatile unsigned short     timer_tgcr;     /* timer global configuration  reg */
768 
    volatile unsigned char      RSRVD22[0xe];
769 
    volatile unsigned short     timer_tmr1;     /* timer 1 mode reg */
770 
    volatile unsigned short     timer_tmr2;     /* timer 2 mode reg */
771 
    volatile unsigned short     timer_trr1;     /* timer 1 referance reg */
772 
    volatile unsigned short     timer_trr2;     /* timer 2 referance reg */
773 
    volatile unsigned short     timer_tcr1;     /* timer 1 capture reg */
774 
    volatile unsigned short     timer_tcr2;     /* timer 2 capture reg */
775 
    volatile unsigned short     timer_tcn1;     /* timer 1 counter reg */
776 
    volatile unsigned short     timer_tcn2;     /* timer 2 counter reg */
777 
    volatile unsigned short     timer_tmr3;     /* timer 3 mode reg */
778 
    volatile unsigned short     timer_tmr4;     /* timer 4 mode reg */
779 
    volatile unsigned short     timer_trr3;     /* timer 3 referance reg */
780 
    volatile unsigned short     timer_trr4;     /* timer 4 referance reg */
781 
    volatile unsigned short     timer_tcr3;     /* timer 3 capture reg */
782 
    volatile unsigned short     timer_tcr4;     /* timer 4 capture reg */
783 
    volatile unsigned short     timer_tcn3;     /* timer 3 counter reg */
784 
    volatile unsigned short     timer_tcn4;     /* timer 4 counter reg */
785 
    volatile unsigned short     timer_ter1;     /* timer 1 event reg */
786 
    volatile unsigned short     timer_ter2;     /* timer 2 event reg */
787 
    volatile unsigned short     timer_ter3;     /* timer 3 event reg */
788 
    volatile unsigned short     timer_ter4;     /* timer 4 event reg */
789 
    volatile unsigned char      RSRVD23[0x8];
790 
 
791 
    /* CP */
792 
    volatile unsigned short     cp_cr;          /* command register */
793 
    volatile unsigned char      RSRVD24[0x2];
794 
    volatile unsigned short     cp_rccr;        /* main configuration reg */
795 
    volatile unsigned char      RSRVD25;
796 
    volatile unsigned char      cp_resv1;       /* RSRVD reg */
797 
    volatile unsigned long      cp_resv2;       /* RSRVD reg */
798 
    volatile unsigned short     cp_rctr1;       /* ram break register 1 */
799 
    volatile unsigned short     cp_rctr2;       /* ram break register 2 */
800 
    volatile unsigned short     cp_rctr3;       /* ram break register 3 */
801 
    volatile unsigned short     cp_rctr4;       /* ram break register 4 */
802 
    volatile unsigned char      RSRVD26[0x2];
803 
    volatile unsigned short     cp_rter;        /* RISC timers event reg */
804 
    volatile unsigned char      RSRVD27[0x2];
805 
    volatile unsigned short     cp_rtmr;        /* RISC timers mask reg */
806 
    volatile unsigned char      RSRVD28[0x14];
807 
 
808 
    /* BRG */
809 
    volatile unsigned long      brgc1;          /* BRG1 configuration reg */
810 
    volatile unsigned long      brgc2;          /* BRG2 configuration reg */
811 
    volatile unsigned long      brgc3;          /* BRG3 configuration reg */
812 
    volatile unsigned long      brgc4;          /* BRG4 configuration reg */
813 
 
814 
    /* SCC registers */
815 
    struct scc_regs {
816 
        volatile unsigned long  scc_gsmr_l;     /* SCC Gen mode (LOW) */
817 
        volatile unsigned long  scc_gsmr_h;     /* SCC Gen mode (HIGH) */
818 
        volatile unsigned short scc_psmr;       /* protocol specific mode register */
819 
        volatile unsigned char  RSRVD29[0x2];
820 
        volatile unsigned short scc_todr;       /* SCC transmit on demand */
821 
        volatile unsigned short scc_dsr;        /* SCC data sync reg */
822 
        volatile unsigned short scc_scce;       /* SCC event reg */
823 
        volatile unsigned char  RSRVD30[0x2];
824 
        volatile unsigned short scc_sccm;       /* SCC mask reg */
825 
        volatile unsigned char  RSRVD31[0x1];
826 
        volatile unsigned char  scc_sccs;       /* SCC status reg */
827 
        volatile unsigned char  RSRVD32[0x8];
828 
    } scc_regs[4];
829 
 
830 
    /* SMC */
831 
    struct smc_regs {
832 
        volatile unsigned char  RSRVD34[0x2];
833 
        volatile unsigned short smc_smcmr;      /* SMC mode reg */
834 
        volatile unsigned char  RSRVD35[0x2];
835 
        volatile unsigned char  smc_smce;       /* SMC event reg */
836 
        volatile unsigned char  RSRVD36[0x3];
837 
        volatile unsigned char  smc_smcm;       /* SMC mask reg */
838 
        volatile unsigned char  RSRVD37[0x5];
839 
    } smc_regs[2];
840 
 
841 
    /* SPI */
842 
    volatile unsigned short     spi_spmode;     /* SPI mode reg */
843 
    volatile unsigned char      RSRVD38[0x4];
844 
    volatile unsigned char      spi_spie;       /* SPI event reg */
845 
    volatile unsigned char      RSRVD39[0x3];
846 
    volatile unsigned char      spi_spim;       /* SPI mask reg */
847 
    volatile unsigned char      RSRVD40[0x2];
848 
    volatile unsigned char      spi_spcom;      /* SPI command reg */
849 
    volatile unsigned char      RSRVD41[0x4];
850 
 
851 
    /* PIP */
852 
    volatile unsigned short     pip_pipc;       /* pip configuration reg */
853 
    volatile unsigned char      RSRVD42[0x2];
854 
    volatile unsigned short     pip_ptpr;       /* pip timing parameters reg */
855 
    volatile unsigned long      pip_pbdir;      /* port b data direction reg */
856 
    volatile unsigned long      pip_pbpar;      /* port b pin assignment reg */
857 
    volatile unsigned char      RSRVD43[0x2];
858 
    volatile unsigned short     pip_pbodr;      /* port b open drain reg */
859 
    volatile unsigned long      pip_pbdat;      /* port b data reg */
860 
    volatile unsigned char      RSRVD44[0x18];
861 
 
862 
    /* Serial Interface */
863 
    volatile unsigned long      si_simode;      /* SI mode register */
864 
    volatile unsigned char      si_sigmr;       /* SI global mode register */
865 
    volatile unsigned char      RSRVD45;
866 
    volatile unsigned char      si_sistr;       /* SI status register */
867 
    volatile unsigned char      si_sicmr;       /* SI command register */
868 
    volatile unsigned char      RSRVD46[0x4];
869 
    volatile unsigned long      si_sicr;        /* SI clock routing */
870 
    volatile unsigned long      si_sirp;        /* SI ram pointers */
871 
    volatile unsigned char      RSRVD47[0x10c];
872 
    volatile unsigned char      si_siram[0x200];/* SI routing ram */
873 
    volatile unsigned short     lcd_lcolr[256]; /* LCD Color RAM -- REV A.x */
874 
    volatile unsigned char      RSRVD48[0x1000];
875 
 
876 
    /* BASE + 0x2000: user data memory */
877 
    volatile unsigned char      udata_ucode[0x800];     /* user data bd's Ucode*/
878 
    volatile unsigned char      bd[0x700];              /* buffer descriptors, data */
879 
    volatile unsigned char      udata_ext[0x100];       /* extension area for downloaded ucode */
880 
    volatile unsigned char      RSRVD49[0x0C00];
881 
 
882 
    /* BASE + 0x3c00: PARAMETER RAM */
883 
    union {
884 
        struct scc_pram {
885 
            union {
886 
                struct hdlc_pram        h;
887 
                struct uart_pram        u;
888 
                struct bisync_pram      b;
889 
                struct transparent_pram t;
890 
                struct async_hdlc_pram  a;
891 
                unsigned char           RSRVD50[0x80];
892 
            } pscc;             /* scc parameter area (protocol dependent) */
893 
 
894 
            union {
895 
                struct {
896 
                    struct i2c_pram     i2c;
897 
                    unsigned char       RSRVD56[0x10];
898 
                    struct idma_pram    idma1;
899 
                } i2c_idma;
900 
                struct {
901 
                    struct spi_pram     spi;
902 
                    struct timer_pram   timer;
903 
                    struct idma_pram    idma2;
904 
                } spi_timer_idma;
905 
                struct {
906 
                    union {
907 
                        struct smc_uart_pram    u;
908 
                        struct smc_trnsp_pram   t;
909 
                        struct centronics_pram  c;
910 
                    } psmc;
911 
                    unsigned char       modem_param[0x40];
912 
                } smc_modem;
913 
                struct {
914 
                    unsigned char       RSRVD54[0x40];
915 
                    struct ucode_pram   ucode;
916 
                } pucode;
917 
            } pothers;
918 
        } scc;
919 
        struct ethernet_pram    enet_scc;
920 
        unsigned char           pr[0x100];
921 
    } pram[4];
922 
} EPPC;
923 
 
924 
 
925 
static inline EPPC *eppc_base(void)
926 
{
927 
    EPPC    *retval;
928 
 
929 
    asm volatile (
930 
        "mfspr   %0,638 \n\t"
931 
        "andis.  %0,%0,65535 \n\t"
932 
        : "=r" (retval)
933 
        : /* no inputs */  );
934 
 
935 
    return retval;
936 
}
937 
 
938 
// Function used to reset [only once!] the CPM
939 
__externC void _mpc8xx_reset_cpm(void);
940 
 
941 
// Function used to allocate space in shared memory area
942 
// typically used for buffer descriptors, etc.
943 
__externC unsigned short _mpc8xx_allocBd(int len);
944 
 
945 
// Function used to manage the pool of baud rate generators
946 
__externC unsigned long *_mpc8xx_allocate_brg(int port);
947 
 
948 
#define QUICC_BD_BASE               0x2000  // Start of shared memory
949 
#define QUICC_BD_END                0x3000  // End of shared memory
950 
 
951 
 
952 
#endif /* __ASSEMBLER__ */
953 
 
954 
/* Memory Periodic Timer Prescaler Register values */
955 
#define PTP_DIV2        0x2000
956 
#define PTP_DIV4        0x1000
957 
#define PTP_DIV8        0x0800
958 
#define PTP_DIV16       0x0400
959 
#define PTP_DIV32       0x0200
960 
#define PTP_DIV64       0x0100
961 
 
962 
// Command Processor Module (CPM)
963 
 
964 
// Buffer descriptor control bits
965 
#define QUICC_BD_CTL_Ready          0x8000  // Buffer contains data (tx) or is empty (rx)
966 
#define QUICC_BD_CTL_Wrap           0x2000  // Last buffer in list
967 
#define QUICC_BD_CTL_Int            0x1000  // Generate interrupt when empty (tx) or full (rx)
968 
#define QUICC_BD_CTL_Last           0x0800  // Last buffer in a sequence
969 
#define QUICC_BD_CTL_Frame          0x0010  // Framing Error
970 
#define QUICC_BD_CTL_Parity         0x0008  // Parity Error
971 
#define QUICC_BD_CTL_MASK           0xB000  // User settable bits
972 
 
973 
// Command register
974 
#define QUICC_CPM_CR_INIT_TXRX      0x0000  // Initialize both Tx and Rx chains
975 
#define QUICC_CPM_CR_INIT_RX        0x0100  // Initialize Rx chains
976 
#define QUICC_CPM_CR_INIT_TX        0x0200  // Initialize Tx chains
977 
#define QUICC_CPM_CR_HUNT_MODE      0x0300  // Start "hunt" mode
978 
#define QUICC_CPM_CR_STOP_TX        0x0400  // Stop transmitter
979 
#define QUICC_CPM_CR_RESTART_TX     0x0600  // Restart transmitter
980 
#define QUICC_CPM_CR_RESET          0x8000  // Reset CPM
981 
#define QUICC_CPM_CR_BUSY           0x0001  // Kick CPM - busy indicator
982 
 
983 
// CPM channels
984 
#define QUICC_CPM_SCC1              0x0000
985 
#define QUICC_CPM_I2C               0x0010
986 
#define QUICC_CPM_SCC2              0x0040
987 
#define QUICC_CPM_SCC3              0x0080
988 
#define QUICC_CPM_SMC1              0x0090
989 
#define QUICC_CPM_SCC4              0x00C0
990 
#define QUICC_CPM_SMC2              0x00D0
991 
 
992 
// SMC Events (interrupts)
993 
#define QUICC_SMCE_BRK              0x10  // Break received
994 
#define QUICC_SMCE_BSY              0x04  // Busy - receive buffer overrun
995 
#define QUICC_SMCE_TX               0x02  // Tx interrupt
996 
#define QUICC_SMCE_RX               0x01  // Rx interrupt
997 
 
998 
// SMC Mode Register
999 
#define QUICC_SMCMR_CLEN(n)   (n<<11)       // Character length + parity + stop bits
1000 
#define QUICC_SMCMR_SB(n)     ((n-1)<<10)   // Stop bits (1 or 2)
1001 
#define QUICC_SMCMR_PE(n)     (n<<9)        // Parity enable (0=disable, 1=enable)
1002 
#define QUICC_SMCMR_PM(n)     (n<<8)        // Parity mode (0=odd, 1=even)
1003 
#define QUICC_SMCMR_UART      (2<<4)        // UART mode
1004 
#define QUICC_SMCMR_TEN       (1<<1)        // Enable transmitter
1005 
#define QUICC_SMCMR_REN       (1<<0)        // Enable receiver
1006 
 
1007 
// SMC Commands
1008 
#define QUICC_SMC_CMD_InitTxRx  (0<<8)
1009 
#define QUICC_SMC_CMD_InitTx    (1<<8)
1010 
#define QUICC_SMC_CMD_InitRx    (2<<8)
1011 
#define QUICC_SMC_CMD_StopTx    (4<<8)
1012 
#define QUICC_SMC_CMD_RestartTx (6<<8)
1013 
#define QUICC_SMC_CMD_Reset     0x8000
1014 
#define QUICC_SMC_CMD_Go        0x0001
1015 
 
1016 
// SCC PSMR masks ....
1017 
#define QUICC_SCC_PSMR_ASYNC   0x8000
1018 
#define QUICC_SCC_PSMR_SB(n)   ((n-1)<<14)  // Stop bits (1=1sb, 2=2sb)
1019 
#define QUICC_SCC_PSMR_CLEN(n) ((n-5)<<12)  // Character Length (5-8)
1020 
#define QUICC_SCC_PSMR_PE(n)   (n<<4)       // Parity enable(0=disabled, 1=enabled)
1021 
#define QUICC_SCC_PSMR_RPM(n)  (n<<2)       // Rx Parity mode (0=odd,  1=low, 2=even, 3=high)
1022 
#define QUICC_SCC_PSMR_TPM(n)  (n)          // Tx Parity mode (0=odd,  1=low, 2=even, 3=high)
1023 
 
1024 
// SCC DSR masks
1025 
#define QUICC_SCC_DSR_FULL     0x7e7e
1026 
#define QUICC_SCC_DSR_HALF     0x467e
1027 
 
1028 
// SCC GSMR masks ...
1029 
#define QUICC_SCC_GSMR_H_INIT  0x00000060
1030 
#define QUICC_SCC_GSMR_L_INIT  0x00028004
1031 
#define QUICC_SCC_GSMR_L_Tx    0x00000010
1032 
#define QUICC_SCC_GSMR_L_Rx    0x00000020
1033 
 
1034 
// SCC Events (interrupts)
1035 
#define QUICC_SCCE_BRK         0x0040
1036 
#define QUICC_SCCE_BSY         0x0004
1037 
#define QUICC_SCCE_TX          0x0002
1038 
#define QUICC_SCCE_RX          0x0001
1039 
 
1040 
#endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H

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