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skrzyp |
//=============================================================================
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//
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// hal_aux.c
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//
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// HAL auxiliary objects and code; per platform
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt
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// Contributors:hmt, gthomas
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// Date: 1999-06-08
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// Purpose: HAL aux objects: startup tables.
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// Description: Tables for per-platform initialization
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include <cyg/hal/hal_mem.h> // HAL memory definitions
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/mpc8xxx.h> // For IMM structures
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#include <cyg/hal/hal_if.h>
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#include <cyg/hal/hal_intr.h>
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// FIXME
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static __inline__ unsigned long
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_le32(unsigned long val)
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{
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return (((val & 0x000000FF) << 24) |
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((val & 0x0000FF00) << 8) |
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((val & 0x00FF0000) >> 8) |
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((val & 0xFF000000) >> 24));
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}
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static __inline__ unsigned short
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_le16(unsigned short val)
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{
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return (((val & 0x000000FF) << 8) |
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((val & 0x0000FF00) >> 8));
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}
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#define HAL_WRITE_UINT32LE(_addr_, _val_) \
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HAL_WRITE_UINT32(_addr_, _le32(_val_))
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#define HAL_WRITE_UINT16LE(_addr_, _val_) \
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HAL_WRITE_UINT16(_addr_, _le16(_val_))
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#define HAL_WRITE_UINT8LE(_addr_, _val_) \
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HAL_WRITE_UINT8(_addr_, _val_)
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#define HAL_READ_UINT32LE(_addr_, _val_) \
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{ \
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HAL_READ_UINT32(_addr_, _val_); \
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_val_ = _le32(_val_); \
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}
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#define HAL_READ_UINT16LE(_addr_, _val_) \
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{ \
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HAL_READ_UINT16(_addr_, _val_); \
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_val_ = _le16(_val_); \
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}
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#define HAL_READ_UINT8LE(_addr_, _val_) \
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HAL_READ_UINT8(_addr_, _val_)
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// FIXME
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// The memory map is weakly defined, allowing the application to redefine
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// it if necessary. The regions defined below are the minimum requirements.
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CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
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// Mapping for the Rattler board
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CYGARC_MEMDESC_CACHE( 0x00000000, 0x01000000 ), // Main memory 60x SDRAM
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CYGARC_MEMDESC_CACHE( 0xFE000000, 0x00800000 ), // ROM region
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CYGARC_MEMDESC_NOCACHE( 0x80000000, 0x00100000 ), // Extended I/O
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CYGARC_MEMDESC_NOCACHE( 0xFF000000, 0x00100000 ), // IMMR registers
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CYGARC_MEMDESC_TABLE_END
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};
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//--------------------------------------------------------------------------
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// Platform init code.
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void
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hal_platform_init(void)
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{
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#ifndef CYGSEM_HAL_USE_ROM_MONITOR
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volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *)CYGARC_IMM_BASE;
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cyg_bool old_board_layout = *(unsigned long *)0xFE0000FC == 0;
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// Configure the I/O pins used by this board
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// + = PARx = 0, PSORx = 0, PDIRx = 0
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// A = PARX = 1, PSORx = 0, PDIRx = 0
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// B = PARX = 1, PSORx = 1, PDIRx = 0
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// C = PARX = 1, PSORx = 0, PDIRx = 1
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// D = PARX = 1, PSORx = 1, PDIRx = 1
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// Port A
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// 1111111111222222222233
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// 01234567890123456789012345678901
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// _______________________________________
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// B FCC1 - COL/MII
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// B- FCC1 - SRC/MII
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// D-- FCC1 - TX_ER/MII
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// D--- FCC1 - TX_EN/MII
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// B---- FCC1 - RX_DV/MII
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// B----- FCC1 - RX_ER/MII
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// +------
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// +-------
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// +--------
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// +---------
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// C---------- FCC1 - TX[3]/MII
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// C----------- FCC1 - TX[2]/MII
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// C------------ FCC1 - TX{1]/MII
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// C------------- FCC1 - TX[0]/MII
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// A-------------- FCC1 - RX[3]/MII
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// A--------------- FCC1 - RX[2]/MII
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// A---------------- FCC1 - RX[1]/MII
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// A----------------- FCC1 - RX[0]/MII
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// +------------------
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// +-------------------
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// +--------------------
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// +---------------------
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// +----------------------
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// +-----------------------
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// +------------------------
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// +-------------------------
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// +--------------------------
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// +---------------------------
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// +----------------------------
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// +----------------------------- LED2
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// +------------------------------ LED1
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// +------------------------------- LED0
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// ++++ ++++ ++++ ++AA AACC CC++ ++BB DDBB
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// 0000 0000 0000 0011 1111 1100 0011 1111 PAR
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// 0000 0000 0000 0000 0000 0000 0011 1111 SOR
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// 0000 0000 0000 0000 0011 1100 0000 1100 DIR
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IMM->io_regs[PORT_A].ppar = 0x0003FC3F;
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IMM->io_regs[PORT_A].psor = 0x0000003F;
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IMM->io_regs[PORT_A].pdir = 0xE0003C0C;
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IMM->io_regs[PORT_A].podr = 0x00000000;
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// Port B
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// 1111111111222222222233
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// 01234567890123456789012345678901
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// ________________________________
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// C FCC2 - TX_ER
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// A- FCC2 - RX_DV
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// D-- FCC2 - TX_EN
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// A--- FCC2 - RX_ER
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// A---- FCC2 - COL
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// A----- FCC2 - CRS
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// C------ FCC2 - TxD[3]
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// C------- FCC2 - TxD[2]
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// C-------- FCC2 - TxD[1]
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// C--------- FCC2 - TxD[0]
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// A---------- FCC2 - RxD[0]
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// A----------- FCC2 - RxD[1]
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// A------------ FCC2 - RxD[2]
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// A------------- FCC2 - RxD[3]
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// +--------------
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// +---------------
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// +----------------
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// +-----------------
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// +------------------
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// +-------------------
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// +--------------------
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// +---------------------
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// +----------------------
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// +-----------------------
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// +------------------------
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// +-------------------------
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// +--------------------------
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// +---------------------------
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// +----------------------------
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// +-----------------------------
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// +------------------------------
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// +-------------------------------
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// ++++ ++++ ++++ ++++ ++AA AACC CCAA ADAC
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// 0000 0000 0000 0000 0011 1111 1111 1111 PAR
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// 0000 0000 0000 0000 0000 0000 0000 0100 SOR
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// 0000 0000 0000 0000 0000 0011 1100 0101 DIR
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IMM->io_regs[PORT_B].ppar = 0x00003FFF;
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IMM->io_regs[PORT_B].psor = 0x00000004;
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IMM->io_regs[PORT_B].pdir = 0x000003C5;
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IMM->io_regs[PORT_B].podr = 0x00000000;
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// Port C
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// 1111111111222222222233
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// 01234567890123456789012345678901
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// ________________________________
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// +
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// +-
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// +--
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// +---
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// +----
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// +-----
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// +------
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// +-------
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// +--------
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// A--------- CLK10 (FCC1 Rx) [new board layout]
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// A---------- CLK11 (FCC1 Tx)
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// A----------- CLK12 (FCC1 Rx) [old board layout]
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// +------------
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// A------------- CLK14 (FCC2 Tx)
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// A-------------- CLK15 (FCC2 Rx)
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// +---------------
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// A---------------- SCC1 - CTS
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// A----------------- SCC1 - CD
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// +------------------
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// +-------------------
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| 240 |
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// +--------------------
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| 241 |
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// +---------------------
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| 242 |
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// +----------------------
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| 243 |
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// +-----------------------
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| 244 |
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// +------------------------
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| 245 |
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// +-------------------------
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| 246 |
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// +--------------------------
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| 247 |
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// +---------------------------
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| 248 |
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// +----------------------------
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| 249 |
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// +-----------------------------
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| 250 |
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// +------------------------------
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| 251 |
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// +-------------------------------
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| 252 |
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// ++++ ++++ ++++ ++AA +AA+ AAA+ ++++ ++++
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| 253 |
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// 0000 0000 0000 0011 0110 ?1?0 0000 0000 PAR (depending on board layout)
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// 0000 0000 0000 0000 0000 0000 0000 0000 SOR
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// 0000 0000 0000 0000 0000 0000 0000 0000 DIR
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| 256 |
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// #define SCC1_FULL_HANDSHAKE
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| 257 |
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#ifdef SCC1_FULL_HANDSHAKE
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IMM->io_regs[PORT_C].ppar = 0x00036000;
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| 259 |
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#else
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| 260 |
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IMM->io_regs[PORT_C].ppar = 0x00006000;
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| 261 |
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#endif
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| 262 |
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if (old_board_layout) {
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| 263 |
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IMM->io_regs[PORT_C].ppar |= 0x00000C00;
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| 264 |
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} else {
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| 265 |
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IMM->io_regs[PORT_C].ppar |= 0x00000600;
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| 266 |
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}
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| 267 |
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IMM->io_regs[PORT_C].psor = 0x00000000;
|
| 268 |
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IMM->io_regs[PORT_C].pdir = 0x00000000;
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| 269 |
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IMM->io_regs[PORT_C].podr = 0x00000000;
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| 270 |
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| 271 |
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// Port D
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| 272 |
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// 1111111111222222222233
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| 273 |
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// 01234567890123456789012345678901
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| 274 |
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// ________________________________
|
| 275 |
|
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// A SCC1 - RxD
|
| 276 |
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// D- SCC1 - TxD
|
| 277 |
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// C-- SCC1 - RTS
|
| 278 |
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// +---
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| 279 |
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// +----
|
| 280 |
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// +-----
|
| 281 |
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// +------
|
| 282 |
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// +-------
|
| 283 |
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// +--------
|
| 284 |
|
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// +---------
|
| 285 |
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// +----------
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| 286 |
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// +-----------
|
| 287 |
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// +------------
|
| 288 |
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// +-------------
|
| 289 |
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// +--------------
|
| 290 |
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// +---------------
|
| 291 |
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// +----------------
|
| 292 |
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// +-----------------
|
| 293 |
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// +------------------
|
| 294 |
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// +-------------------
|
| 295 |
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// +--------------------
|
| 296 |
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// +---------------------
|
| 297 |
|
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// C---------------------- SMC1 - TxD
|
| 298 |
|
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// A----------------------- SMC1 - RxD
|
| 299 |
|
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// +------------------------
|
| 300 |
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// +-------------------------
|
| 301 |
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// +--------------------------
|
| 302 |
|
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// +---------------------------
|
| 303 |
|
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// +----------------------------
|
| 304 |
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// +-----------------------------
|
| 305 |
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// +------------------------------
|
| 306 |
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// +-------------------------------
|
| 307 |
|
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// ++++ ++++ AC++ ++++ ++++ ++++ ++++ +CDA
|
| 308 |
|
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// 0000 0000 1100 0000 0000 0000 0000 0111 PAR
|
| 309 |
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// 0000 0000 0000 0000 0000 0000 0000 0010 SOR
|
| 310 |
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// 0000 0000 0100 0000 0000 0000 0000 0110 DIR
|
| 311 |
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#ifdef SCC1_FULL_HANDSHAKE
|
| 312 |
|
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IMM->io_regs[PORT_D].ppar = 0x00C00003;
|
| 313 |
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IMM->io_regs[PORT_D].psor = 0x00000002;
|
| 314 |
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IMM->io_regs[PORT_D].pdir = 0x00400006;
|
| 315 |
|
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IMM->io_regs[PORT_D].podr = 0x00000000;
|
| 316 |
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#else
|
| 317 |
|
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IMM->io_regs[PORT_D].ppar = 0x00C00007;
|
| 318 |
|
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IMM->io_regs[PORT_D].psor = 0x00000002;
|
| 319 |
|
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IMM->io_regs[PORT_D].pdir = 0x00400002;
|
| 320 |
|
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IMM->io_regs[PORT_D].podr = 0x00000000;
|
| 321 |
|
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#endif
|
| 322 |
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|
| 323 |
|
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// Misc I/O bits
|
| 324 |
|
|
IMM->io_regs[PORT_B].pdir |= 0x03000000; // PB7 = Reset FCC1 PHY
|
| 325 |
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// PB6 = Reset FCC2 PHY
|
| 326 |
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|
| 327 |
|
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IMM->io_regs[PORT_B].pdat |= 0x03000000;
|
| 328 |
|
|
|
| 329 |
|
|
IMM->io_regs[PORT_C].pdir |= 0x3C000000; // PC5 = FCC2 MDIO
|
| 330 |
|
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// PC4 = FCC2 MDC
|
| 331 |
|
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// PC3 = FCC1 MDIO
|
| 332 |
|
|
// PC2 = FCC1 MDC
|
| 333 |
|
|
IMM->io_regs[PORT_C].pdat |= 0x3C000000;
|
| 334 |
|
|
|
| 335 |
|
|
// Clock steering
|
| 336 |
|
|
IMM->cpm_mux_cmxuar = 0x00000000; // Utopia address reg
|
| 337 |
|
|
if (old_board_layout) {
|
| 338 |
|
|
// Mux for FCC
|
| 339 |
|
|
// --11 0111 --11 0101 ---- ---- ---- ----
|
| 340 |
|
|
// xx x FCC1 - Tx clock 11
|
| 341 |
|
|
// xxx FCC1 - Rx clock 12
|
| 342 |
|
|
// xx x FCC2 - Tx clock 14
|
| 343 |
|
|
// xxx FCC2 - Rx clock 15
|
| 344 |
|
|
IMM->cpm_mux_cmxfcr = 0x37350000;
|
| 345 |
|
|
} else {
|
| 346 |
|
|
// Mux for FCC
|
| 347 |
|
|
// --11 0101 --11 0101 ---- ---- ---- ----
|
| 348 |
|
|
// xx x FCC1 - Tx clock 11
|
| 349 |
|
|
// xxx FCC1 - Rx clock 10
|
| 350 |
|
|
// xx x FCC2 - Tx clock 14
|
| 351 |
|
|
// xxx FCC2 - Rx clock 15
|
| 352 |
|
|
IMM->cpm_mux_cmxfcr = 0x35350000;
|
| 353 |
|
|
}
|
| 354 |
|
|
// Mux for SCCx
|
| 355 |
|
|
// --00 0000 --00 1001 --01 0010 --01 1011
|
| 356 |
|
|
// xx x SCC1 - Rx clock BRG1
|
| 357 |
|
|
// xxx SCC1 - Tx clock BRG1
|
| 358 |
|
|
// xx x SCC2 - Rx clock BRG2
|
| 359 |
|
|
// xxx SCC2 - Tx clock BRG2
|
| 360 |
|
|
// xx x SCC3 - Rx clock BRG3
|
| 361 |
|
|
// xxx SCC3 - Tx clock BRG3
|
| 362 |
|
|
// xx x SCC4 - Rx clock BRG4
|
| 363 |
|
|
// xxx SCC4 - Tx clock BRG4
|
| 364 |
|
|
IMM->cpm_mux_cmxscr = 0x0009121B;
|
| 365 |
|
|
// Mux for SMCx
|
| 366 |
|
|
// --01 --01
|
| 367 |
|
|
// xx SMC1 - clock on BRG7
|
| 368 |
|
|
// xx SMC2 - clock on BRG8
|
| 369 |
|
|
IMM->cpm_mux_cmxsmr = 0x11;
|
| 370 |
|
|
#endif // CYGSEM_HAL_USE_ROM_MONITOR
|
| 371 |
|
|
|
| 372 |
|
|
// Start up system I/O
|
| 373 |
|
|
hal_if_init();
|
| 374 |
|
|
|
| 375 |
|
|
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
|
| 376 |
|
|
#ifdef CYGHWR_HAL_POWERPC_RATTLER_PCI
|
| 377 |
|
|
if ((IMM->clocks_sccr & 0x100) != 0) {
|
| 378 |
|
|
CYG_WORD16 pci_cfg;
|
| 379 |
|
|
|
| 380 |
|
|
HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000004);
|
| 381 |
|
|
HAL_WRITE_UINT16LE(&IMM->pci_cfg_data, 0);
|
| 382 |
|
|
// Configure PCI address registers
|
| 383 |
|
|
IMM->pcimsk1 = 0xC0000000;
|
| 384 |
|
|
IMM->pcibr1 = 0x80000001;
|
| 385 |
|
|
IMM->pcimsk0 = 0xFF800000;
|
| 386 |
|
|
IMM->pcibr0 = 0x48000001;
|
| 387 |
|
|
IMM->pci_gpcr = 0;
|
| 388 |
|
|
IMM->pci_picmr1 = 0xF0FF0FE0;
|
| 389 |
|
|
IMM->pci_picmr0 = 0xF0FF0FE0;
|
| 390 |
|
|
// Now disable CFG_LOCK to free bus
|
| 391 |
|
|
HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000044);
|
| 392 |
|
|
HAL_READ_UINT16LE(&IMM->pci_cfg_data, pci_cfg);
|
| 393 |
|
|
pci_cfg &= ~0x20; // Turn off CFG_LOCK
|
| 394 |
|
|
HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000044);
|
| 395 |
|
|
HAL_WRITE_UINT16LE(&IMM->pci_cfg_data, pci_cfg);
|
| 396 |
|
|
HAL_WRITE_UINT32LE(&IMM->pci_cfg_addr, 0x80000044);
|
| 397 |
|
|
HAL_READ_UINT16LE(&IMM->pci_cfg_data, pci_cfg);
|
| 398 |
|
|
} else {
|
| 399 |
|
|
diag_printf("*** Warning: PCI not responding - SCCR: %x\n", IMM->clocks_sccr);
|
| 400 |
|
|
}
|
| 401 |
|
|
#endif
|
| 402 |
|
|
#endif // CYGSEM_HAL_USE_ROM_MONITOR
|
| 403 |
|
|
}
|
| 404 |
|
|
|
| 405 |
|
|
//
|
| 406 |
|
|
// Cause the platform to reset
|
| 407 |
|
|
//
|
| 408 |
|
|
void
|
| 409 |
|
|
_rattler_reset(void)
|
| 410 |
|
|
{
|
| 411 |
|
|
unsigned long hid0, int_state;
|
| 412 |
|
|
|
| 413 |
|
|
// Need interrupts off to force checkstop
|
| 414 |
|
|
HAL_DISABLE_INTERRUPTS(int_state);
|
| 415 |
|
|
HAL_DISABLE_MACHINE_CHECK(int_state);
|
| 416 |
|
|
IMM->clocks_rmr |= 0x01; // Checkstop Reset Enable
|
| 417 |
|
|
// Force a checkstop by turning on parity which is not implemented
|
| 418 |
|
|
CYGARC_MFSPR(CYGARC_REG_HID0, hid0);
|
| 419 |
|
|
hid0 |= 0x30000000;
|
| 420 |
|
|
CYGARC_MTSPR(CYGARC_REG_HID0, hid0);
|
| 421 |
|
|
diag_printf("...RESET\n");
|
| 422 |
|
|
while (1) ;
|
| 423 |
|
|
}
|
| 424 |
|
|
|
| 425 |
|
|
//
|
| 426 |
|
|
// Display a value in the LEDs
|
| 427 |
|
|
// Note: the values used/returned by this function are positive
|
| 428 |
|
|
// i.e. a value of 0 is all LEDs off, 0x7 is all on
|
| 429 |
|
|
//
|
| 430 |
|
|
#define LED_SHIFT 29 // LEDs are in bits A0..A2
|
| 431 |
|
|
#define LED_MASK 7 // 3 bits total
|
| 432 |
|
|
int
|
| 433 |
|
|
_rattler_leds(int val)
|
| 434 |
|
|
{
|
| 435 |
|
|
volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *)CYGARC_IMM_BASE;
|
| 436 |
|
|
unsigned int old_val = ~(IMM->io_regs[PORT_A].pdat >> LED_SHIFT) & LED_MASK;
|
| 437 |
|
|
unsigned int new_val = (old_val & ~(LED_MASK<<LED_SHIFT)) | ((~val&LED_MASK)<<LED_SHIFT);
|
| 438 |
|
|
|
| 439 |
|
|
IMM->io_regs[PORT_A].pdat = new_val;
|
| 440 |
|
|
return old_val;
|
| 441 |
|
|
}
|
| 442 |
|
|
|
| 443 |
|
|
// EOF hal_aux.c
|
