OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [sh/] [arch/] [current/] [src/] [context.S] - Blame information for rev 817

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
##=============================================================================
2
##
3
##      context.S
4
##
5
##      SH context switch code
6
##
7
##=============================================================================
8
## ####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later
16
## version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT
19
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License
24
## along with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26
##
27
## As a special exception, if other files instantiate templates or use
28
## macros or inline functions from this file, or you compile this file
29
## and link it with other works to produce a work based on this file,
30
## this file does not by itself cause the resulting work to be covered by
31
## the GNU General Public License. However the source code for this file
32
## must still be made available in accordance with section (3) of the GNU
33
## General Public License v2.
34
##
35
## This exception does not invalidate any other reasons why a work based
36
## on this file might be covered by the GNU General Public License.
37
## -------------------------------------------
38
## ####ECOSGPLCOPYRIGHTEND####
39
##=============================================================================
40
#######DESCRIPTIONBEGIN####
41
##
42
## Author(s):   jskov
43
## Contributors:jskov, nickg
44
## Date:        1999-05-01
45
## Purpose:     SH context switch code
46
## Description: This file contains implementations of the thread context
47
##              switch routines. It also contains the longjmp() and setjmp()
48
##              routines.
49
##
50
######DESCRIPTIONEND####
51
##
52
##=============================================================================
53
 
54
#include 
55
 
56
#include 
57
#include 
58
#include            // CYG_LABEL_DEFN
59
 
60
#------------------------------------------------------------------------------
61
# Register allocation for the Hitachi calling convention:
62
#
63
#       r0              arg return
64
#       r1..r3          scratch
65
#       r4..r7          args in
66
#       r8..r13         call saved
67
#       r14             frame pointer/call saved
68
#       r15             stack pointer
69
#       ap              arg pointer (doesn''t really exist, always eliminated)
70
#       pr              subroutine return address
71
#       t               t bit
72
#       mach            multiply/accumulate result, high part
73
#       macl            multiply/accumulate result, low part.
74
#       fpul            fp/int communication register
75
#       rap             return address pointer register
76
#       fr0             fp arg return
77
#       fr1..fr3        scratch floating point registers
78
#       fr4..fr11       fp args in
79
#       fr12..fr15      call saved floating point registers
80
#------------------------------------------------------------------------------
81
 
82
 
83
#------------------------------------------------------------------------------
84
# hal_thread_switch_context
85
# Switch thread contexts
86
# R4 = address of sp of next thread to execute
87
# R5 = address of sp save location of current thread
88
 
89
# Need to save r8-r13, r14 (fp), r15 (sp), pr, mach, macl
90
 
91
FUNC_START(hal_thread_switch_context)
92
        mov     r15, r0                 ! R0 = saved stack pointer
93
 
94
        sts.l   pr,@-r15                ! save caller in PC slot so it looks
95
                                        ! sensible when GDB examines it
96
        stc     sr,r1
97
        mov.l   r1,@-r15
98
 
99
        sts.l   pr,@-r15                ! return address
100
 
101
#ifdef CYGHWR_HAL_SH_FPU
102
        sts.l   fpscr,@-r15
103
        sts.l   fpul,@-r15
104
#if CYGHWR_HAL_SH_FPU_REGS == 32
105
        frchg
106
        fmov.s  fr15,@-r15
107
        fmov.s  fr14,@-r15
108
        fmov.s  fr13,@-r15
109
        fmov.s  fr12,@-r15
110
        fmov.s  fr11,@-r15
111
        fmov.s  fr10,@-r15
112
        fmov.s  fr9,@-r15
113
        fmov.s  fr8,@-r15
114
        fmov.s  fr7,@-r15
115
        fmov.s  fr6,@-r15
116
        fmov.s  fr5,@-r15
117
        fmov.s  fr4,@-r15
118
        fmov.s  fr3,@-r15
119
        fmov.s  fr2,@-r15
120
        fmov.s  fr1,@-r15
121
        fmov.s  fr0,@-r15
122
        frchg
123
#endif
124
        fmov.s  fr15,@-r15
125
        fmov.s  fr14,@-r15
126
        fmov.s  fr13,@-r15
127
        fmov.s  fr12,@-r15
128
        fmov.s  fr11,@-r15
129
        fmov.s  fr10,@-r15
130
        fmov.s  fr9,@-r15
131
        fmov.s  fr8,@-r15
132
        fmov.s  fr7,@-r15
133
        fmov.s  fr6,@-r15
134
        fmov.s  fr5,@-r15
135
        fmov.s  fr4,@-r15
136
        fmov.s  fr3,@-r15
137
        fmov.s  fr2,@-r15
138
        fmov.s  fr1,@-r15
139
        fmov.s  fr0,@-r15
140
#endif
141
 
142
        sts.l   macl,@-r15              ! macl
143
        sts.l   mach,@-r15              ! mach
144
        mov.l   r0,@-r15                ! saved r15 (entry sp)
145
        mov.l   r14,@-r15               ! r14-r0
146
        mov.l   r13,@-r15
147
        mov.l   r12,@-r15
148
        mov.l   r11,@-r15
149
        mov.l   r10,@-r15
150
        mov.l   r9,@-r15
151
        mov.l   r8,@-r15
152
        mov.l   r7,@-r15
153
        mov.l   r6,@-r15
154
        mov.l   r5,@-r15
155
        mov.l   r4,@-r15
156
        mov.l   r3,@-r15
157
        mov.l   r2,@-r15
158
        mov.l   r1,@-r15
159
        mov.l   r0,@-r15
160
 
161
        mov.l   r15,@r5                 ! save SP into save location
162
 
163
        # Now load the destination thread by dropping through
164
        # to hal_thread_load_context
165
 
166
#------------------------------------------------------------------------------
167
# hal_thread_load_context
168
# Load thread context
169
# R4 = address of sp of next thread to execute
170
# Note that this function is also the second half of hal_thread_switch_context
171
# and is simply dropped into from it.
172
 
173
FUNC_START(hal_thread_load_context)
174
 
175
        mov.l   @r4,r0
176
 
177
        add     #4+4,r0                 ! skip r0 and r1
178
        !mov.l   @r0+,r0
179
        !mov.l   @r0+,r1
180
        mov.l   @r0+,r2
181
        mov.l   @r0+,r3
182
        mov.l   @r0+,r4
183
        mov.l   @r0+,r5
184
        mov.l   @r0+,r6
185
        mov.l   @r0+,r7
186
        mov.l   @r0+,r8
187
        mov.l   @r0+,r9
188
        mov.l   @r0+,r10
189
        mov.l   @r0+,r11
190
        mov.l   @r0+,r12
191
        mov.l   @r0+,r13
192
        mov.l   @r0+,r14
193
        mov.l   @r0+,r3                 ! New SP.
194
 
195
        lds.l   @r0+,mach               ! mach
196
        lds.l   @r0+,macl               ! macl
197
 
198
#ifdef CYGHWR_HAL_SH_FPU
199
        fmov.s  @r0+,fr0
200
        fmov.s  @r0+,fr1
201
        fmov.s  @r0+,fr2
202
        fmov.s  @r0+,fr3
203
        fmov.s  @r0+,fr4
204
        fmov.s  @r0+,fr5
205
        fmov.s  @r0+,fr6
206
        fmov.s  @r0+,fr7
207
        fmov.s  @r0+,fr8
208
        fmov.s  @r0+,fr9
209
        fmov.s  @r0+,fr10
210
        fmov.s  @r0+,fr11
211
        fmov.s  @r0+,fr12
212
        fmov.s  @r0+,fr13
213
        fmov.s  @r0+,fr14
214
        fmov.s  @r0+,fr15
215
#if CYGHWR_HAL_SH_FPU_REGS == 32
216
        frchg
217
        fmov.s  @r0+,fr0
218
        fmov.s  @r0+,fr1
219
        fmov.s  @r0+,fr2
220
        fmov.s  @r0+,fr3
221
        fmov.s  @r0+,fr4
222
        fmov.s  @r0+,fr5
223
        fmov.s  @r0+,fr6
224
        fmov.s  @r0+,fr7
225
        fmov.s  @r0+,fr8
226
        fmov.s  @r0+,fr9
227
        fmov.s  @r0+,fr10
228
        fmov.s  @r0+,fr11
229
        fmov.s  @r0+,fr12
230
        fmov.s  @r0+,fr13
231
        fmov.s  @r0+,fr14
232
        fmov.s  @r0+,fr15
233
        frchg
234
#endif
235
        lds.l   @r0+,fpul
236
        lds.l   @r0+,fpscr
237
#endif
238
 
239
        lds.l   @r0+,pr                 ! pr
240
 
241
        mov     r3,r15                  ! update stack pointer
242
 
243
        mov.l   @r0+,r2                 ! SR
244
        hal_cpu_int_merge r2,r0,r1      ! restore interrupt state
245
 
246
        rts                             ! and return
247
         nop
248
 
249
#------------------------------------------------------------------------------
250
# HAL longjmp, setjmp implementations
251
# hal_setjmp saves only to callee save registers r8-r13, r14(fp), r15(sp)
252
# and pr into buffer supplied in r4[arg0]
253
 
254
FUNC_START(hal_setjmp)
255
        mov.l   r15,@(CYGARC_JMPBUF_SP,r4)
256
        sts     pr,r0
257
        mov.l   r0,@(CYGARC_JMPBUF_PR,r4)
258
        mov.l   r8,@(CYGARC_JMPBUF_R8,r4)
259
        mov.l   r9,@(CYGARC_JMPBUF_R9,r4)
260
        mov.l   r10,@(CYGARC_JMPBUF_R10,r4)
261
        mov.l   r11,@(CYGARC_JMPBUF_R11,r4)
262
        mov.l   r12,@(CYGARC_JMPBUF_R12,r4)
263
        mov.l   r13,@(CYGARC_JMPBUF_R13,r4)
264
        mov.l   r14,@(CYGARC_JMPBUF_R14,r4)
265
 
266
        mov    #0,r0            ! return 0
267
        rts
268
         nop
269
 
270
# hal_longjmp loads state from r4[arg0] and returns
271
# argument supplied in r5[arg1]
272
 
273
FUNC_START(hal_longjmp)
274
        mov.l   @(CYGARC_JMPBUF_SP,r4),r15
275
        mov.l   @(CYGARC_JMPBUF_PR,r4),r0
276
        lds     r0,pr
277
        mov.l   @(CYGARC_JMPBUF_R8,r4),r8
278
        mov.l   @(CYGARC_JMPBUF_R9,r4),r9
279
        mov.l   @(CYGARC_JMPBUF_R10,r4),r10
280
        mov.l   @(CYGARC_JMPBUF_R11,r4),r11
281
        mov.l   @(CYGARC_JMPBUF_R12,r4),r12
282
        mov.l   @(CYGARC_JMPBUF_R13,r4),r13
283
        mov.l   @(CYGARC_JMPBUF_R14,r4),r14
284
 
285
        mov     r5,r0
286
        rts
287
         nop
288
 
289
#------------------------------------------------------------------------------
290
# end of context.S

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.