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#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
##      platform.inc
##
##      SH/CQ7750 board assembler header file
##
##=============================================================================
## ####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later
## version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License
## along with eCos; if not, write to the Free Software Foundation, Inc.,
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
##
## As a special exception, if other files instantiate templates or use
## macros or inline functions from this file, or you compile this file
## and link it with other works to produce a work based on this file,
## this file does not by itself cause the resulting work to be covered by
## the GNU General Public License. However the source code for this file
## must still be made available in accordance with section (3) of the GNU
## General Public License v2.
##
## This exception does not invalidate any other reasons why a work based
## on this file might be covered by the GNU General Public License.
## -------------------------------------------
## ####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   jskov
## Contributors:Ryozaburo Suzuki
## Date:        2000-04-18
## Purpose:     SH/CQ7750 board definitions.
## Description: This file contains various definitions and macros that are
##              useful for writing assembly code for the SH/CQ7750 board.
## Usage:
##              #include 
##              ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
 
#include 
#include 
 
#------------------------------------------------------------------------------
# Hardware initialization.
 
        .macro  hal_hardware_init
        // Set up the Bus State Controller
        mova     BSC_settings_table,r0
        mov      r0,r3
1:      mov.l    @r3+,r0                // Address (or zero)
        mov      r0,r2
        cmp/eq   #0,r0
        bt       4f
        mov.l    @r3+,r1                // data
        mov.l    @r3+,r0                // byte or word or long?
 
        cmp/eq   #0,r0   // byte
        bt       2f
 
        cmp/eq   #1,r0   // word
        bt       3f
 
        bra      1b      // long
        mov.l    r1,@r2  // delay slot
 
2:      bra      1b
        mov.b    r1,@r2  // delay slot
 
3:      bra      1b
        mov.w    r1,@r2  // delay slot
 
        .align  2
 
BSC_settings_table:
        # FRQCR:
        .long   CYGARC_REG_FRQCR
        .long   CYGARC_REG_FRQCR_INIT
        .long   2
 
        # BCR1:
        .long   CYGARC_REG_BCR1
        .long   0x0020000c
        .long   2
        # BCR2:
        .long   CYGARC_REG_BCR2
        .long   0x35F8
        .long   1
        # WCR1:
        .long   CYGARC_REG_WCR1
        .long   0x77117121
        .long   2
        # WCR2:
        .long   CYGARC_REG_WCR2
        .long   0xFC8AE520
        .long   2
        # WCR3:
        .long   CYGARC_REG_WCR3
        .long   0x07117101
        .long   2
        # PCR:
        .long   CYGARC_REG_PCR
        .long   0x0000
        .long   1
        # RTCNT:
        .long   CYGARC_REG_RTCNT
        .long   0xa500
        .long   1
        # RTCOR:
        .long   CYGARC_REG_RTCOR
        .long   0xa53b
        .long   1
        # RFCR:
        .long   CYGARC_REG_RFCR
        .long   0xa400
        .long   1
        # RTCSR:
        .long   CYGARC_REG_RTCSR
        .long   0xa508
        .long   1
        # MCR:
        .long   CYGARC_REG_MCR
        .long   0x10192194
        .long   2
        # SDMR2:
        .long   0xFF90008c
        .long   0xaa
        .long   0
        # MCR:
        .long   CYGARC_REG_MCR
        .long   0x50192194
        .long   2
        # SDMR2:
        .long   0xFF90008c
        .long   0xaa
        .long   0
        # Table end
        .long   0
 
        .align  2
4:
        .endm
 
#------------------------------------------------------------------------------
# Monitor initialization.
 
#ifndef CYGPKG_HAL_SH_MON_DEFINED
 
#if     defined(CYG_HAL_STARTUP_ROM) ||                 \
        (       defined(CYG_HAL_STARTUP_RAM) &&         \
                !defined(CYGSEM_HAL_USE_ROM_MONITOR))
 
        # If we are starting up from ROM, or we are starting in
        # RAM and NOT using a ROM monitor, initialize the VSR table.
 
        .macro  hal_mon_init
        mov.l   $hal_vsr_table,r3
        # Write exception vectors
        mov.l   $cyg_hal_default_exception_vsr,r4
        mov     #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
1:      mov.l   r4,@r3
        add     #4,r3
        dt      r5
        bf      1b
        # Write interrupt vector
        mov.l   $cyg_hal_default_interrupt_vsr,r4
        mov.l   $hal_vsr_table,r3
        add     #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
        mov.l   r4,@r3
        bra     2f
         nop
        .align  2
 
        SYM_PTR_REF(cyg_hal_default_exception_vsr)
        SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
        SYM_PTR_REF(hal_vsr_table)
2:
        .endm
 
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
        # Initialize the VSR table entries
        # We only take control of the interrupt vector,
        # the rest are left to the ROM for now...
 
        .macro  hal_mon_init
        # Write interrupt vector
        mov.l   $hal_vsr_table,r3
        mov.l   $cyg_hal_default_interrupt_vsr,r4
        add     #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
        mov.l   r4,@r3
        bra     2f
         nop
        .align  2
 
        SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
        SYM_PTR_REF(hal_vsr_table)
2:
        .endm
 
#else
 
        .macro  hal_mon_init
        .endm
 
#endif
 
 
#define CYGPKG_HAL_SH_MON_DEFINED
 
#endif // CYGPKG_HAL_SH_MON_DEFINED
 
#endif // CYGONCE_HAL_PLATFORM_INC

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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [sh/] [cq7750/] [current/] [include/] [platform.inc] - Blame information for rev 791

Line No.	Rev	Author	Line
1	786	skrzyp	`#ifndef CYGONCE_HAL_PLATFORM_INC`
2			`#define CYGONCE_HAL_PLATFORM_INC`
3			`##=============================================================================`
4			`##`
5			`## platform.inc`
6			`##`
7			`## SH/CQ7750 board assembler header file`
8			`##`
9			`##=============================================================================`
10			`## ####ECOSGPLCOPYRIGHTBEGIN####`
11			`## -------------------------------------------`
12			`## This file is part of eCos, the Embedded Configurable Operating System.`
13			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.`
14			`##`
15			`## eCos is free software; you can redistribute it and/or modify it under`
16			`## the terms of the GNU General Public License as published by the Free`
17			`## Software Foundation; either version 2 or (at your option) any later`
18			`## version.`
19			`##`
20			`## eCos is distributed in the hope that it will be useful, but WITHOUT`
21			`## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
22			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
23			`## for more details.`
24			`##`
25			`## You should have received a copy of the GNU General Public License`
26			`## along with eCos; if not, write to the Free Software Foundation, Inc.,`
27			`## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
28			`##`
29			`## As a special exception, if other files instantiate templates or use`
30			`## macros or inline functions from this file, or you compile this file`
31			`## and link it with other works to produce a work based on this file,`
32			`## this file does not by itself cause the resulting work to be covered by`
33			`## the GNU General Public License. However the source code for this file`
34			`## must still be made available in accordance with section (3) of the GNU`
35			`## General Public License v2.`
36			`##`
37			`## This exception does not invalidate any other reasons why a work based`
38			`## on this file might be covered by the GNU General Public License.`
39			`## -------------------------------------------`
40			`## ####ECOSGPLCOPYRIGHTEND####`
41			`##=============================================================================`
42			`#######DESCRIPTIONBEGIN####`
43			`##`
44			`## Author(s): jskov`
45			`## Contributors:Ryozaburo Suzuki`
46			`## Date: 2000-04-18`
47			`## Purpose: SH/CQ7750 board definitions.`
48			`## Description: This file contains various definitions and macros that are`
49			`## useful for writing assembly code for the SH/CQ7750 board.`
50			`## Usage:`
51			`## #include`
52			`## ...`
53			`##`
54			`##`
55			`######DESCRIPTIONEND####`
56			`##`
57			`##=============================================================================`
58
59			`#include`
60
61			`#include`
62			`#include`
63
64			`#------------------------------------------------------------------------------`
65			`# Hardware initialization.`
66
67			`.macro hal_hardware_init`
68			`// Set up the Bus State Controller`
69			`mova BSC_settings_table,r0`
70			`mov r0,r3`
71			`1: mov.l @r3+,r0 // Address (or zero)`
72			`mov r0,r2`
73			`cmp/eq #0,r0`
74			`bt 4f`
75			`mov.l @r3+,r1 // data`
76			`mov.l @r3+,r0 // byte or word or long?`
77
78			`cmp/eq #0,r0 // byte`
79			`bt 2f`
80
81			`cmp/eq #1,r0 // word`
82			`bt 3f`
83
84			`bra 1b // long`
85			`mov.l r1,@r2 // delay slot`
86
87			`2: bra 1b`
88			`mov.b r1,@r2 // delay slot`
89
90			`3: bra 1b`
91			`mov.w r1,@r2 // delay slot`
92
93			`.align 2`
94
95			`BSC_settings_table:`
96			`# FRQCR:`
97			`.long CYGARC_REG_FRQCR`
98			`.long CYGARC_REG_FRQCR_INIT`
99			`.long 2`
100
101			`# BCR1:`
102			`.long CYGARC_REG_BCR1`
103			`.long 0x0020000c`
104			`.long 2`
105			`# BCR2:`
106			`.long CYGARC_REG_BCR2`
107			`.long 0x35F8`
108			`.long 1`
109			`# WCR1:`
110			`.long CYGARC_REG_WCR1`
111			`.long 0x77117121`
112			`.long 2`
113			`# WCR2:`
114			`.long CYGARC_REG_WCR2`
115			`.long 0xFC8AE520`
116			`.long 2`
117			`# WCR3:`
118			`.long CYGARC_REG_WCR3`
119			`.long 0x07117101`
120			`.long 2`
121			`# PCR:`
122			`.long CYGARC_REG_PCR`
123			`.long 0x0000`
124			`.long 1`
125			`# RTCNT:`
126			`.long CYGARC_REG_RTCNT`
127			`.long 0xa500`
128			`.long 1`
129			`# RTCOR:`
130			`.long CYGARC_REG_RTCOR`
131			`.long 0xa53b`
132			`.long 1`
133			`# RFCR:`
134			`.long CYGARC_REG_RFCR`
135			`.long 0xa400`
136			`.long 1`
137			`# RTCSR:`
138			`.long CYGARC_REG_RTCSR`
139			`.long 0xa508`
140			`.long 1`
141			`# MCR:`
142			`.long CYGARC_REG_MCR`
143			`.long 0x10192194`
144			`.long 2`
145			`# SDMR2:`
146			`.long 0xFF90008c`
147			`.long 0xaa`
148			`.long 0`
149			`# MCR:`
150			`.long CYGARC_REG_MCR`
151			`.long 0x50192194`
152			`.long 2`
153			`# SDMR2:`
154			`.long 0xFF90008c`
155			`.long 0xaa`
156			`.long 0`
157			`# Table end`
158			`.long 0`
159
160			`.align 2`
161			`4:`
162			`.endm`
163
164			`#------------------------------------------------------------------------------`
165			`# Monitor initialization.`
166
167			`#ifndef CYGPKG_HAL_SH_MON_DEFINED`
168
169			`#if defined(CYG_HAL_STARTUP_ROM) \|\| \`
170			`( defined(CYG_HAL_STARTUP_RAM) && \`
171			`!defined(CYGSEM_HAL_USE_ROM_MONITOR))`
172
173			`# If we are starting up from ROM, or we are starting in`
174			`# RAM and NOT using a ROM monitor, initialize the VSR table.`
175
176			`.macro hal_mon_init`
177			`mov.l $hal_vsr_table,r3`
178			`# Write exception vectors`
179			`mov.l $cyg_hal_default_exception_vsr,r4`
180			`mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5`
181			`1: mov.l r4,@r3`
182			`add #4,r3`
183			`dt r5`
184			`bf 1b`
185			`# Write interrupt vector`
186			`mov.l $cyg_hal_default_interrupt_vsr,r4`
187			`mov.l $hal_vsr_table,r3`
188			`add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3`
189			`mov.l r4,@r3`
190			`bra 2f`
191			`nop`
192			`.align 2`
193
194			`SYM_PTR_REF(cyg_hal_default_exception_vsr)`
195			`SYM_PTR_REF(cyg_hal_default_interrupt_vsr)`
196			`SYM_PTR_REF(hal_vsr_table)`
197			`2:`
198			`.endm`
199
200			`#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)`
201
202			`# Initialize the VSR table entries`
203			`# We only take control of the interrupt vector,`
204			`# the rest are left to the ROM for now...`
205
206			`.macro hal_mon_init`
207			`# Write interrupt vector`
208			`mov.l $hal_vsr_table,r3`
209			`mov.l $cyg_hal_default_interrupt_vsr,r4`
210			`add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3`
211			`mov.l r4,@r3`
212			`bra 2f`
213			`nop`
214			`.align 2`
215
216			`SYM_PTR_REF(cyg_hal_default_interrupt_vsr)`
217			`SYM_PTR_REF(hal_vsr_table)`
218			`2:`
219			`.endm`
220
221			`#else`
222
223			`.macro hal_mon_init`
224			`.endm`
225
226			`#endif`
227
228
229			`#define CYGPKG_HAL_SH_MON_DEFINED`
230
231			`#endif // CYGPKG_HAL_SH_MON_DEFINED`
232
233			`#endif // CYGONCE_HAL_PLATFORM_INC`