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skrzyp |
#ifndef CYGONCE_HAL_PLATFORM_INC
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#define CYGONCE_HAL_PLATFORM_INC
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##=============================================================================
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##
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## platform.inc
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##
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## SH/EDK7708 board assembler header file
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): jskov
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## Contributors:jskov
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## Date: 2000-02-02
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## Purpose: SH/EDK7708 board definitions.
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## Description: This file contains various definitions and macros that are
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## useful for writing assembly code for the SH/EDK7708 board.
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## Usage:
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## #include
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## ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#include
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#------------------------------------------------------------------------------
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# Hardware initialization.
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.macro hal_hardware_init
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// Set up the Bus State Controller
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mova BSC_settings_table,r0
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mov r0,r3
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1: mov.w @r3+,r0 // Address (or zero)
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cmp/eq #0,r0
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bt 2f
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mov.w @r3+,r1 // data
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bra 1b
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mov.w r1,@r0 // delay slot
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.align 2
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BSC_settings_table:
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# These are the settings set by the Hitachi ROM Monitor.
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.word (CYGARC_REG_FRQCR & 0x0000FFFF)
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.word CYGARC_REG_FRQCR_INIT
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# BCR2: Bus size of areas 1-6 to 32 bits
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.word (CYGARC_REG_BCR2 & 0x0000FFFF)
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.word 0x3ffc
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# BCR1: Areas 2 and 3 are SDRAM
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.word (CYGARC_REG_BCR1 & 0x0000FFFF)
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.word 0x080c
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# BCR2: Bus size of areas 1-6 to 32 bits [note: second write!]
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.word (CYGARC_REG_BCR2 & 0x0000FFFF)
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.word 0x3ffc
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# WCR1: 3 wait-state cycles inserted for all areas
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.word (CYGARC_REG_WCR1 & 0x0000FFFF)
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.word 0x3fff
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# WCR2: extra wait states and full pitch for burst
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.word (CYGARC_REG_WCR2 & 0x0000FFFF)
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.word 0xffd7
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# MCR: RAS/CAS & burst timing area 2/3
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.word (CYGARC_REG_MCR & 0x0000FFFF)
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.word 0x963c
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# RTCNT: refresh counter (needs a5 in top byte to accept write)
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.word (CYGARC_REG_RTCNT & 0x0000FFFF)
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.word (0xa500 | 0x0000)
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# RTCOR: refresh time constant (needs a5 in top byte to accept write)
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.word (CYGARC_REG_RTCOR & 0x0000FFFF)
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.word (0xa500 | 0x003b)
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# RFCR: refresh count register (needs a4 in top byte to accept write)
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.word (CYGARC_REG_RFCR & 0x0000FFFF)
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.word (0xa400 | 0x0000)
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# RTCSR: refresh timer control (needs a5 in top byte to accept write)
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.word (CYGARC_REG_RTCSR & 0x0000FFFF)
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.word (0xa500 | 0x0008)
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# Set SDMR to 0x220
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.word 0xd880
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.word 0
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# Table end
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.word 0
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.align 2
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2:
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.endm
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#------------------------------------------------------------------------------
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# Monitor initialization.
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#ifndef CYGPKG_HAL_SH_MON_DEFINED
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#if !defined(CYG_HAL_STARTUP_RAM) || \
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( defined(CYG_HAL_STARTUP_RAM) && \
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!defined(CYGSEM_HAL_USE_ROM_MONITOR))
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# If we are not starting up from RAM, or we are starting in
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# RAM and NOT using a ROM monitor, initialize the VSR table.
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.macro hal_mon_init
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mov.l $hal_vsr_table,r3
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# Write exception vectors
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mov.l $cyg_hal_default_exception_vsr,r4
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mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
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1: mov.l r4,@r3
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add #4,r3
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dt r5
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bf 1b
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# Write interrupt vector
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mov.l $cyg_hal_default_interrupt_vsr,r4
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mov.l $hal_vsr_table,r3
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add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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mov.l r4,@r3
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bra 2f
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nop
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.align 2
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SYM_PTR_REF(cyg_hal_default_exception_vsr)
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SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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SYM_PTR_REF(hal_vsr_table)
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2:
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.endm
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#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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# Initialize the VSR table entries
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# We only take control of the interrupt vector,
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# the rest are left to the ROM for now...
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.macro hal_mon_init
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# Write interrupt vector
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mov.l $hal_vsr_table,r3
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mov.l $cyg_hal_default_interrupt_vsr,r4
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add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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mov.l r4,@r3
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bra 2f
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nop
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.align 2
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SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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SYM_PTR_REF(hal_vsr_table)
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2:
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.endm
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#else
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.macro hal_mon_init
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.endm
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#endif
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#define CYGPKG_HAL_SH_MON_DEFINED
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#endif // CYGPKG_HAL_SH_MON_DEFINED
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#endif // CYGONCE_HAL_PLATFORM_INC
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