OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [sh/] [se77x9/] [current/] [cdl/] [hal_sh_sh77x9_se77x9.cdl] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
# ====================================================================
2
#
3
#      hal_sh_sh77x9_se77x9.cdl
4
#
5
#      Hitachi SE77X9 board HAL package configuration data
6
#
7
# ====================================================================
8
## ####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later
16
## version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT
19
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License
24
## along with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26
##
27
## As a special exception, if other files instantiate templates or use
28
## macros or inline functions from this file, or you compile this file
29
## and link it with other works to produce a work based on this file,
30
## this file does not by itself cause the resulting work to be covered by
31
## the GNU General Public License. However the source code for this file
32
## must still be made available in accordance with section (3) of the GNU
33
## General Public License v2.
34
##
35
## This exception does not invalidate any other reasons why a work based
36
## on this file might be covered by the GNU General Public License.
37
## -------------------------------------------
38
## ####ECOSGPLCOPYRIGHTEND####
39
# ====================================================================
40
######DESCRIPTIONBEGIN####
41
#
42
# Author(s):      jskov
43
# Original data:  jskov
44
# Contributors:
45
# Date:           2001-05-25
46
#
47
#####DESCRIPTIONEND####
48
#
49
# ====================================================================
50
 
51
cdl_package CYGPKG_HAL_SH_SH77X9_SE77X9 {
52
    display       "Hitachi/SH77X9 SE77X9 board"
53
    parent        CYGPKG_HAL_SH
54
    requires      ! CYGHWR_HAL_SH_BIGENDIAN
55
    requires      CYGHWR_HAL_SH_IRQ_USE_IRQLVL
56
    define_header hal_sh_sh77x9_se77x9.h
57
    include_dir   cyg/hal
58
    description   "
59
        The SE77X9 HAL package provides the support needed to run
60
        eCos on a Hitachi/SH SE77X9 board."
61
 
62
    compile       hal_diag.c plf_misc.c ser16c550c.c
63
 
64
    implements    CYGINT_HAL_DEBUG_GDB_STUBS
65
    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
66
    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
67
    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
68
 
69
    define_proc {
70
        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   "
71
        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "
72
 
73
        puts $::cdl_header "#define CYGNUM_HAL_SH_SH3_SCIF_PORTS 1"
74
        puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x8c000000"
75
        puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x8c000100"
76
 
77
        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"SE77X9\""
78
        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
79
    }
80
 
81
    cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT {
82
        display       "Board variant"
83
        flavor        data
84
        legal_values  {"SE7709RP01" "SE7709SE01" "SE7729SE01"}
85
        default_value {"SE7709SE01"}
86
        no_define
87
        description   "
88
            Select the particular board variant used."
89
    }
90
 
91
    cdl_option CYGPRI_HAL_SH_SH77X9_SUPERIO {
92
        display       "Board variant has SuperIO controller"
93
        default_value 0
94
        compile       smsc37c93x.c
95
        description   "
96
            Set if the board has a SuperIO controller."
97
    }
98
 
99
 
100
    cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT_7709R {
101
        display       "SE7709RP01 board"
102
        active_if     { CYGPRI_HAL_SH_SH77X9_VARIANT == "SE7709RP01" }
103
        calculated    1
104
 
105
        requires      CYGPKG_HAL_SH_7709R
106
        requires      !CYGPKG_HAL_SH_7709S
107
        requires      !CYGPKG_HAL_SH_7729
108
        requires      !CYGPRI_HAL_SH_SH77X9_SUPERIO
109
        requires      { CYGNUM_HAL_SH_OOC_XTAL_DEFAULT == 20000000 }
110
        define_proc {
111
            puts $::cdl_header "#define HAL_PLATFORM_CPU    \"SH 7709R\""
112
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_CLOCK 14745000"
113
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_BASE 0xb0800000"
114
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_LEDS_BASE 0xb1800000"
115
        }
116
 
117
        description   "Settings for the 7709R variant of the board."
118
    }
119
 
120
    cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT_7709S {
121
        display       "SE7709SE01 board"
122
        active_if     { CYGPRI_HAL_SH_SH77X9_VARIANT == "SE7709SE01" }
123
        calculated    1
124
        requires      CYGPRI_HAL_SH_SH77X9_SUPERIO
125
        requires      !CYGPKG_HAL_SH_7709R
126
        requires      CYGPKG_HAL_SH_7709S
127
        requires      !CYGPKG_HAL_SH_7729
128
        define_proc {
129
            puts $::cdl_header "#define HAL_PLATFORM_CPU    \"SH 7709S\""
130
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_CLOCK 1846200"
131
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_BASE 0xb04007f0"
132
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_LEDS_BASE 0xb0c00000"
133
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP"
134
        }
135
 
136
        description   "Settings for the 7709S variant of the board."
137
    }
138
 
139
    cdl_option CYGPRI_HAL_SH_SH77X9_VARIANT_7729 {
140
        display       "SE7729SE01 board"
141
        active_if     { CYGPRI_HAL_SH_SH77X9_VARIANT == "SE7729SE01" }
142
        calculated    1
143
        requires      CYGPRI_HAL_SH_SH77X9_SUPERIO
144
        requires      !CYGPKG_HAL_SH_7709R
145
        requires      !CYGPKG_HAL_SH_7709S
146
        requires      CYGPKG_HAL_SH_7729
147
        define_proc {
148
            puts $::cdl_header "#define HAL_PLATFORM_CPU    \"SH 7729\""
149
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_CLOCK 1846200"
150
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_16550_BASE 0xb04007f0"
151
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_LEDS_BASE 0xb0c00000"
152
            puts $::cdl_header "#define CYGNUM_HAL_SH_SE77X9_SDRAM_SETUP"
153
        }
154
 
155
        description   "Settings for the 7729 variant of the board."
156
    }
157
 
158
 
159
    cdl_component CYG_HAL_STARTUP {
160
        display       "Startup type"
161
        flavor        data
162
        legal_values  {"RAM" "ROM" "ROMRAM" }
163
        default_value {"RAM"}
164
        no_define
165
        define -file system.h CYG_HAL_STARTUP
166
        description   "
167
           When targetting the SE77X9 board it is possible to build
168
           the system for either RAM bootstrap or ROM bootstrap.
169
           RAM bootstrap generally requires that the board
170
           is equipped with ROMs containing a suitable ROM monitor or
171
           equivalent software that allows GDB to download the eCos
172
           application on to the board. The ROM bootstrap typically
173
           requires that the eCos application be blown into EPROMs or
174
           equivalent technology. ROMRAM bootstrap is similar to ROM
175
           bootstrap, but everything is copied to RAM before execution
176
           starts thus improving performance, but at the cost of an
177
           increased RAM footprint."
178
    }
179
 
180
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
181
        display      "Number of communication channels on the board"
182
        flavor       data
183
        calculated   2
184
    }
185
 
186
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
187
        display          "Debug serial port"
188
        flavor data
189
        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
190
        default_value    0
191
        description      "
192
           The SE77X9 board has one serial port. This option
193
           chooses which port will be used to connect to a host
194
           running GDB."
195
    }
196
 
197
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
198
        display      "Default console channel."
199
        flavor       data
200
        calculated   0
201
    }
202
 
203
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
204
        display          "Diagnostic serial port"
205
        flavor data
206
        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
207
        default_value    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
208
        description      "
209
           The SE77X9 board has two serial ports.  This option
210
           chooses which port will be used for diagnostic output."
211
    }
212
 
213
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
214
        display       "Console/GDB serial port baud rate"
215
        flavor        data
216
        legal_values  9600 19200 38400 57600 115200
217
        default_value 38400
218
        define        CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
219
        description   "
220
            This option controls the default baud rate used for the
221
            Console/GDB connection."
222
    }
223
 
224
    cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
225
        display          "SH on-chip platform clock controls"
226
        description      "
227
            The various clocks used by the system are derived from
228
            these options."
229
        flavor        none
230
        no_define
231
 
232
        cdl_option CYGNUM_HAL_SH_OOC_XTAL_DEFAULT {
233
            display          "SH clock crystal default value"
234
            flavor           data
235
            default_value    33333300
236
            no_define
237
        }
238
 
239
        cdl_option CYGHWR_HAL_SH_OOC_XTAL {
240
            display          "SH clock crystal"
241
            flavor           data
242
            legal_values     8000000 to 50000000
243
            default_value    { CYGNUM_HAL_SH_OOC_XTAL_DEFAULT }
244
            no_define
245
            description      "
246
                This option specifies the frequency of the crystal all
247
                other clocks are derived from."
248
        }
249
 
250
        cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
251
            display          "SH clock PLL circuit 1"
252
            flavor           data
253
            default_value    4
254
            legal_values     { 0 1 2 3 4 6 8 }
255
            description      "
256
                This selects the multiplication factor provided by
257
                PLL1. If PLL1 is disabled via CAP1, this option should
258
                be set to zero."
259
        }
260
 
261
        cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
262
            display          "SH clock PLL circuit 2"
263
            flavor           data
264
            default_value    1
265
            legal_values     { 0 1 4 }
266
            no_define
267
            description      "
268
                This selects the multiplication factor provided by
269
                PLL2. If PLL2 is disabled via CAP2, this option should
270
                be set to zero."
271
        }
272
 
273
        cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
274
            display          "SH clock divider 1"
275
            flavor           data
276
            default_value    1
277
            legal_values     { 1 2 3 4 6 }
278
            description      "
279
                This divider option affects the CPU core clock."
280
        }
281
 
282
        cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_2 {
283
            display          "SH clock divider 2"
284
            flavor           data
285
            default_value    4
286
            legal_values     { 1 2 3 4 6 }
287
            description      "
288
                This divider option affects the peripheral clock."
289
        }
290
 
291
        cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
292
            display          "SH clock mode"
293
            flavor           data
294
            default_value    0
295
            legal_values     { 0 1 2 3 4 7 }
296
            description      "
297
                This option must mirror the clock mode hardwired on
298
                the MD0-MD2 pins of the CPU in order to correctly
299
                initialize the FRQCR register."
300
        }
301
    }
302
 
303
    cdl_component CYGBLD_GLOBAL_OPTIONS {
304
        display "Global build options"
305
        flavor  none
306
        parent  CYGPKG_NONE
307
        no_define
308
        description   "
309
            Global build options including control over
310
            compiler flags, linker flags and choice of toolchain."
311
 
312
 
313
        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
314
            display "Global command prefix"
315
            flavor  data
316
            no_define
317
            default_value { "sh-elf" }
318
            description "
319
                This option specifies the command prefix used when
320
                invoking the build tools."
321
        }
322
 
323
        cdl_option CYGBLD_GLOBAL_CFLAGS {
324
            display "Global compiler flags"
325
            flavor  data
326
            no_define
327
            default_value { CYGBLD_GLOBAL_WARNFLAGS .
328
                            (CYGHWR_HAL_SH_BIGENDIAN ? "-mb" : "-ml") .
329
                            " -m3 -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions"
330
            }
331
            description   "
332
                This option controls the global compiler flags which
333
                are used to compile all packages by
334
                default. Individual packages may define
335
                options which override these global flags."
336
        }
337
 
338
        cdl_option CYGBLD_GLOBAL_LDFLAGS {
339
            display "Global linker flags"
340
            flavor  data
341
            no_define
342
            default_value { (CYGHWR_HAL_SH_BIGENDIAN ? "-mb" : "-ml") . " -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
343
            description   "
344
                This option controls the global linker flags. Individual
345
                packages may define options which override these global flags."
346
        }
347
 
348
        cdl_option CYGBLD_BUILD_GDB_STUBS {
349
            display "Build GDB stub ROM image"
350
            default_value 0
351
            requires { CYG_HAL_STARTUP == "ROM" }
352
            requires CYGSEM_HAL_ROM_MONITOR
353
            requires CYGBLD_BUILD_COMMON_GDB_STUBS
354
            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
355
            requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
356
            requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
357
            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
358
            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
359
            no_define
360
            description "
361
                This option enables the building of the GDB stubs for the
362
                board. The common HAL controls takes care of most of the
363
                build process, but the final conversion from ELF image to
364
                binary data is handled by the platform CDL, allowing
365
                relocation of the data if necessary."
366
 
367
            make -priority 320 {
368
                /bin/gdb_module.bin : /bin/gdb_module.img
369
                $(OBJCOPY) -O binary $< $@
370
            }
371
        }
372
    }
373
 
374
    cdl_component CYGHWR_MEMORY_LAYOUT {
375
        display "Memory layout"
376
        flavor data
377
        no_define
378
        calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh77x9_se77x9_ram" : \
379
                     CYG_HAL_STARTUP == "ROM" ? "sh_sh77x9_se77x9_rom" : \
380
                                                "sh_sh77x9_se77x9_romram" }
381
 
382
        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
383
            display "Memory layout linker script fragment"
384
            flavor data
385
            no_define
386
            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
387
            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
388
                         CYG_HAL_STARTUP == "ROM" ? "" : \
389
                                                    "" }
390
        }
391
 
392
        cdl_option CYGHWR_MEMORY_LAYOUT_H {
393
            display "Memory layout header file"
394
            flavor data
395
            no_define
396
            define -file system.h CYGHWR_MEMORY_LAYOUT_H
397
            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
398
                         CYG_HAL_STARTUP == "ROM" ? "" : \
399
                                                    "" }
400
        }
401
    }
402
 
403
    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
404
        display       "Work with a ROM monitor"
405
        flavor        booldata
406
        legal_values  { "GDB_stubs" }
407
        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
408
        requires      { CYG_HAL_STARTUP == "RAM" }
409
        parent        CYGPKG_HAL_ROM_MONITOR
410
        description   "
411
            Support can be enabled for boot ROMs or ROM monitors which contain
412
            GDB stubs. This support changes various eCos semantics such as
413
            the encoding of diagnostic output, and the overriding of hardware
414
            interrupt vectors."
415
    }
416
 
417
    cdl_option CYGSEM_HAL_ROM_MONITOR {
418
        display       "Behave as a ROM monitor"
419
        flavor        bool
420
        default_value 0
421
        parent        CYGPKG_HAL_ROM_MONITOR
422
        requires      { CYG_HAL_STARTUP == "ROM" }
423
        description   "
424
            Enable this option if this program is to be used as a ROM monitor,
425
            i.e. applications will be loaded into RAM on the board, and this
426
            ROM monitor may process exceptions or interrupts generated from the
427
            application. This enables features such as utilizing a separate
428
            interrupt stack when exceptions are generated."
429
    }
430
 
431
    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
432
        display       "Redboot HAL options"
433
        flavor        none
434
        no_define
435
        parent        CYGPKG_REDBOOT
436
        active_if     CYGPKG_REDBOOT
437
        description   "
438
            This option lists the target's requirements for a valid Redboot
439
            configuration."
440
 
441
        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
442
            display       "Build Redboot ROM binary image"
443
            active_if     CYGBLD_BUILD_REDBOOT
444
            default_value 1
445
            no_define
446
            description "This option enables the conversion of the Redboot ELF
447
                         image to a binary image suitable for ROM programming."
448
 
449
            make -priority 325 {
450
                /bin/redboot.bin : /bin/redboot.elf
451
                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
452
                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
453
                $(OBJCOPY) --change-address 0x21000000 -O srec $< $(@:.bin=.eprom.srec)
454
                $(OBJCOPY) -O binary $< $@
455
            }
456
        }
457
    }
458
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.